CN108270402A - Voltage detecting and control circuit - Google Patents

Abstract

Voltage detecting and control circuit belong to Analogous Integrated Electronic Circuits technical field.Including reference voltage output buffer module, voltage operational module and comparator module, the input terminal connection reference voltage of reference voltage output buffer module, output terminal connects the second input terminal of voltage operational module；The external adjustment voltage of first input end connection of voltage operational module is handled to obtain the first input end that comparison signal is output to comparator module by the input signal to its first input end and the second input terminal；Second input terminal of comparator module connects voltage to be detected, and a control signal is obtained as voltage detecting and the output signal of control circuit by comparing voltage to be detected and comparison signal.Detection range of the present invention is big, applied widely；Dynamic amplifier is particularly suitable for, in certain variation range of supply voltage, obtains the dynamic amplifier amplification factor not changed with mains voltage variations, so as to obtain the gain stabilization dynamic amplifier of anti-mains fluctuations.

Description

Voltage detection and control circuit

technical field

The invention belongs to the technical field of analog integrated circuits, and relates to a voltage detection and control circuit, which is especially suitable for the detection of dynamic amplifier power supply voltage fluctuations and the correction of gain under power supply voltage fluctuations.

Background technique

The progress of integrated circuit technology has continuously increased the working speed of digital circuits, increased the integration density, and gradually reduced the power supply voltage. The data representing the comprehensive performance of digital circuits has been significantly improved; The performance that has the greatest impact is the amplifier. As a basic module widely used in analog circuits, on the one hand, technological progress has produced many non-ideal effects of CMOS devices, which have a greater impact on sensitive analog circuits; on the other hand, the reduction of power supply voltage has limited the choice of amplifier structures. In view of this, dynamic amplifiers have become a hot spot in design and research. Dynamic amplifiers have a simple structure and no static power consumption. They are well adapted to low power supply voltages and greatly reduce power consumption. Therefore, they are used in many circuits, such as analog However, the gain of the dynamic amplifier is easily affected by the fluctuation of the power supply voltage, and in the actual circuit, the fluctuation of the power supply voltage is unavoidable, which greatly limits the performance and scope of application of the dynamic amplifier , so when designing and using a dynamic amplifier, it is necessary to consider reducing or eliminating the influence of power supply voltage fluctuations on the gain.

A dynamic amplifier with common mode detection is shown in Figure 1. In Figure 1, the dynamic amplifier is mainly composed of the fourth PMOS transistor M1, the fifth PMOS transistor M2, and the sixth PMOS transistor M3 for reset, which are used as input The third NMOS transistor M4 and the fourth NMOS transistor M5 of the pair of tubes, the fifth NMOS transistor M6 and the sixth NMOS transistor M7 that control the amplification process are used to detect the output common-mode capacitance of the second capacitor C ₁ and the third capacitor C ₂ , composed of the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 that control the output access, and the fourth capacitor C _LN and the fifth capacitor C _LP representing the load. In the figure, the external clock signal clk controls the dynamic amplifier to switch between the reset and amplification phases. The common mode detector CMD detects the output common mode V _x . When the voltage of the V _x point is greater than the set fixed voltage, the output V _ctrl is high. Level, when the voltage at point V _x is less than the set fixed voltage, the output V _ctrl is low level; change the gate terminal voltage of the fifth NMOS transistor M6 through the output control signal V _ctrl to control the end of the amplification, and control the end of the amplification by controlling the first connected to the load The voltage-controlled switch SW1 and the second voltage-controlled switch SW2 disconnect the load and the dynamic amplifier output.

Among them, in the reset phase, the signal clk controlled by the external clock is low level, the fourth PMOS transistor M1, the fifth PMOS transistor M2, and the sixth PMOS transistor M3 used for reset are turned on, and the sixth NMOS transistor controlled by clk M7 is turned off, the internal nodes V ₁ , V ₂ , and V _x of the dynamic amplifier are charged to the power supply voltage, the V _ctrl output by the common mode detector CMD is high level, the fifth NMOS transistor M6 is turned on, and the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 are closed, and the fourth capacitor C _LN and the fifth capacitor C _LP of the output load are directly connected to the amplifier and charged to the power supply voltage, which is the reset state.

When the external clock signal clk becomes high level, the dynamic amplifier starts to amplify. The specific process is: the fourth PMOS transistor M1, the fifth PMOS transistor M2, and the sixth PMOS transistor M3 controlled by the external clock signal clk are directly turned off. When V _x keeps high resistance, the total charge of V _x node remains unchanged, the sixth NMOS transistor M7 controlled by clk is turned on, and the third NMOS transistor M7 controlled by input signals V _ip and V _in that remain unchanged during amplification M4 and the fourth NMOS transistor M5 start to discharge the two nodes of V ₁ and V ₂ , if the set common-mode voltage is considered to be V _det , the NMOS threshold voltage of the dynamic amplifier input pair transistor is V _th , β=C _ox * μ*W/L, where C _ox is the capacitance of the gate oxide layer per unit area, μ is the carrier mobility, W/L is the width-to-length ratio of the MOS tube, and the load capacitance C _LP ＝ _CLN ＝ _CL , then V _outn , The relationship between the voltage change of the two points of V _outp with the input signal and time is:

During the discharge process of V ₁ and V ₂ , the voltage at point V _x will follow the change of V ₁ and V ₂ through the second capacitor C ₁ and the third capacitor C ₂ , usually C ₁ =C ₂ , then during the discharge process V The expression of the voltage change at point _x is:

The voltage at point V _x drops continuously with the discharge of V ₁ and V ₂ , and when it drops to the set common-mode voltage, V _ctrl changes from high level to low level, thus controlling the fifth NMOS transistor M6 of the dynamic amplifier Turn off, cut off the discharge path of V ₁ and V ₂ , and at the same time disconnect the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2, so that the load capacitance and the output of the dynamic amplifier are disconnected, so as to save the amplified voltage and the amplified time The time t for _Vx to discharge from the supply voltage _VDD to the set common-mode voltage can be expressed as:

Accordingly, the gain can be determined by the amplification time:

In the above formula, V _cm is the common-mode level of input differential signals V _ip and V _in . When the difference between V _ip and V _in is small, the gain expression can be simplified as:

Obviously, through the gain expression, it can be found that the gain of the dynamic amplifier is related to V _DD . During the use of the actual circuit, the power supply voltage is very likely to be at a different DC voltage. Even if a voltage regulator is used for voltage stabilization, the power supply Voltage fluctuations will also affect the gain of the dynamic amplifier, which brings hidden dangers to circuit applications that require a fixed gain amplifier, resulting in changes in the amplification factor of the input signal.

Contents of the invention

In view of the above shortcomings, the present invention proposes a voltage detection and control circuit for detecting voltage and providing control signals through the detection results, especially suitable for power supply voltage fluctuation detection of dynamic amplifiers and correction of gain under power supply voltage fluctuations. The voltage detection and control circuit provided by the invention replaces the common mode detector CMD in the dynamic amplifier, and overcomes the influence of the change and fluctuation of the power supply voltage of the dynamic amplifier on the gain.

Technical scheme of the present invention is:

The voltage detection and control circuit includes a reference voltage output buffer module 402, a voltage operation module 403 and a comparator module 404,

The input end of the reference voltage output buffer module 402 is connected to the reference voltage, and its output end is connected to the second input end of the voltage operation module 403;

The first input terminal of the comparator module 404 is connected to the output terminal of the voltage calculation module 403, its second input terminal is connected to the voltage to be detected, and its output terminal is used as the output terminal of the voltage detection and control circuit;

The voltage calculation module 403 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a first capacitor _C3 , a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1 and the second PMOS tube MP2,

The source of the first PMOS transistor MP1 is used as the first input terminal of the voltage operation module 403 to connect to the external adjustment voltage, its gate is connected to the output terminal of the first inverter INV1, and its drain is connected to the first NMOS transistor MN1 and the first NMOS transistor MN1 and the first inverter INV1. The drain of the second PMOS transistor MP2 and the upper plate of the first capacitor _C3 ;

The input terminal of the second inverter INV2 is connected to the input terminal of the first inverter INV1 and connected to the external clock signal clk, and the output terminal thereof is connected to the gate of the first NMOS transistor MN1;

The source of the second PMOS transistor MP2 is connected to the source of the first NMOS transistor MN1 and serves as the second input terminal of the voltage operation module 403, and its gate is connected to the input terminal of the third inverter INV3 and connected to the external clock signal clk ;

The gate of the second NMOS transistor MN2 is connected to the output terminal of the third inverter INV3, its drain is connected to the lower plate of the first capacitor _C3 as the output terminal of the voltage calculation module 403, and its source is grounded.

Specifically, the reference voltage output buffer module 402 includes an operational amplifier, a first resistor R1 and a third PMOS transistor MP3,

The positive input terminal of the operational amplifier is connected to the reference voltage, and its negative input terminal is connected to the drain of the third PMOS transistor MP3 and one end of the first resistor R1 as the output terminal of the reference voltage output buffer module 402, which outputs The terminal is connected to the gate of the third PMOS transistor MP3, the source of the third PMOS transistor MP3 is connected to the power supply voltage, and the other end of the first resistor R1 is grounded.

Specifically, the comparator module 404 includes a comparator 405, the negative input terminal of the comparator 405 is connected to the output terminal of the voltage operation module 403, the positive input terminal is connected to the voltage to be detected, and its output terminal as the output terminal of the voltage detection and control circuit.

Specifically, the voltage value of the external adjustment voltage V _Y is greater than the voltage value V _refbuf of the output terminal of the reference voltage output buffer module 402 .

Working principle of the present invention is:

The reference voltage V _ref is an accurate voltage that does not change with the power supply voltage, temperature, and process. After passing through the reference voltage output buffer module 402, a buffered reference voltage V _refbuf is obtained; the voltage operation module 403 is controlled by the external clock signal clk. The external adjustment voltage V _Y and the buffer reference voltage V _refbuf are processed to obtain a comparison signal V _det = V _Y -V _refbuf ; the output control signal V _ctrl is controlled by comparing the voltage value of the voltage to be detected V _X and the comparison signal V _det to Low level or high level, the condition that the control signal V _ctrl is high level is adjusted by adjusting the value of the comparison signal V _det .

The beneficial effects of the present invention are: the voltage detection and control circuit provided by the present invention has a large detection range and a wide application range, and is especially suitable for dynamic amplifiers. By adjusting the voltage value of the comparison signal V _det under power supply voltage fluctuations, different power supplies can be adjusted. The amplification time of the dynamic amplifier under voltage, within a certain variation range of the power supply voltage, obtains the dynamic amplifier amplification factor that does not change with the power supply voltage change, thereby obtaining a gain-stabilized dynamic amplifier that is resistant to power supply voltage fluctuations.

Description of drawings

Figure 1 is a schematic circuit diagram of a conventional charge-transfer dynamic amplifier with common-mode detection.

FIG. 2 is a schematic circuit diagram of the voltage detection and control circuit provided by the present invention when it is suitable for correcting the gain of the charge-transfer dynamic amplifier.

FIG. 3 is a schematic diagram of the internal modules of the voltage detection and control circuit provided by the present invention.

Fig. 4 is a schematic diagram of the internal structure of the reference voltage output buffer module in the embodiment.

FIG. 5 is a schematic diagram of the internal structure of the voltage calculation module in the present invention.

Fig. 6 is a schematic diagram of the internal structure of the comparator module in the embodiment.

FIG. 7 is a schematic circuit diagram of applying the present invention to a charge-transfer dynamic amplifier to realize gain stability under voltage fluctuations in an embodiment.

Fig. 8 is a circuit schematic diagram when the present invention is used for voltage monitoring in an embodiment.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 3, the present invention includes a reference voltage output buffer module 402, a voltage operation module 403 and a comparator module 404, the input end of the reference voltage output buffer module 402 is connected to the reference voltage V _ref , and its output end outputs the buffer reference voltage V _refbuf To the second input terminal of the voltage calculation module 403; the first input terminal of the voltage calculation module 403 is connected to the external adjustment voltage V _Y , and the signals of its first input terminal and the second input terminal are processed under the control of the external clock signal clk, Obtain a comparison signal V _det =V _Y -V _refbuf output to the first input terminal of the comparator module 404; the second input terminal of the comparator module 404 is connected to the voltage V _X to be detected, by comparing the voltage V _X to be detected and the comparison signal The value of V _det gets a control signal V _ctrl .

The voltage detection and control circuit provided by the present invention obtains the values of different comparison signals V _det by adjusting the values of the reference voltage V _ref and the external adjustment voltage V _Y , so that the generation of the output control signal V _ctrl of different conditions can be realized as required, and the comparison signal The range of V _det can be 0-V _DD , and the detection range is large.

As shown in Figure 2 and Figure 7, the voltage detection and control circuit provided by the present invention can replace the common mode detector CMD in the traditional dynamic amplifier and be applied to the dynamic amplifier, and the first input end of the voltage detection and control circuit is connected to the dynamic amplifier The output common-mode voltage point, the second input terminal is connected to the power supply voltage V _DD , that is, the voltage to be detected V _X is the output common-mode voltage, the external adjustment voltage V _Y is the power supply voltage V _DD , and the output control signal V _ctrl controls the dynamic amplifier the amplification process. In the embodiment, the charge-transfer dynamic amplifier includes a fourth PMOS transistor M1, a fifth PMOS transistor M2, a sixth PMOS transistor M3, a third NMOS transistor M4, a fourth NMOS transistor M5, a fifth NMOS transistor M6, and a sixth NMOS transistor M7. , the second capacitor C ₁ , the third capacitor C ₂ , the fourth capacitor C _LN , the fifth capacitor C _LP , the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2. The third NMOS transistor M4 and the fourth NMOS transistor M5 are the input pair of the dynamic amplifier, the gate of the third NMOS transistor M4 is the positive phase input terminal of the dynamic amplifier, and the gate of the fourth NMOS transistor M5 is the negative phase input terminal of the dynamic amplifier , the source of the third NMOS transistor M4 is connected to the source of the fourth NMOS transistor M5 and the drain of the third NMOS transistor M6, the gate of the third NMOS transistor M6 is connected to the control signal V _ctrl , and its source is connected to the sixth NMOS transistor The drain of M7, the gate of the sixth NMOS transistor M7 are connected to the external clock signal clk, and the source of the sixth NMOS transistor M7 is grounded. The drain of the third NMOS transistor M4 is connected to the drain of the fourth PMOS transistor M1, the upper plate of the second capacitor _C1 and the input terminal of the first voltage-controlled switch SW1, which is the negative phase output terminal _V1 of the dynamic amplifier. The drain of the four NMOS transistor M5 is connected to the drain of the sixth PMOS transistor M3, the upper plate of the third capacitor _C2 and the input end of the second voltage-controlled switch SW2, which is the non-inverting output end _V2 of the dynamic amplifier, and the fifth The drain of the PMOS transistor M2 is connected to the lower plate of the second capacitor _C1 and the third capacitor _C2 and the first input end of the voltage detection and control circuit provided by the present invention, the fourth PMOS transistor M1, the fifth PMOS transistor M2 and The gates of the sixth PMOS transistor M3 are all connected to the external clock signal clk, the sources of the fourth PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 are all connected to the power supply voltage V _DD , and the control signal V _ctrl output by the present invention Control the closing and opening of the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2, the output end of the first voltage-controlled switch SW1 is connected to the upper plate of the fourth capacitor _CLN , and the output end of the second voltage-controlled switch SW2 is connected to The upper plate of the fifth capacitor C _LP , the lower plates of the fourth capacitor C _LN and the fifth capacitor C _LP are all grounded.

As shown in FIG. 4 , the circuit structure diagram of the reference voltage output buffer module 402 in this embodiment includes an operational amplifier, a first resistor R1 and a third PMOS transistor MP3. The positive input terminal of the operational amplifier is connected to the reference voltage V _ref , which The negative input terminal is connected to the drain of the third PMOS transistor MP3 and one end of the first resistor R1 and is used as the output terminal of the reference voltage output buffer module to output the buffered reference voltage V _refbuf , and its output terminal is connected to the gate of the third PMOS transistor MP3, The source of the third PMOS transistor MP3 is connected to the power supply voltage V _DD , and the other end of the first resistor R1 is grounded. Since the calculation operation process in the voltage calculation module 403 requires the buffered reference voltage V _refbuf to have a relatively high response speed, it is necessary to buffer the reference voltage V _ref to obtain the buffered reference voltage V _refbuf . Requirements for speed of response.

FIG. 5 is a schematic structural diagram of the voltage calculation module 403 in the present invention. Figure 6 shows the circuit structure diagram of the comparator module 404 in this embodiment, including a comparator 405, the negative input of the comparator 405 is connected to the output of the voltage calculation module, and its positive input is connected to The output terminal of the voltage to be detected V _X is used as the output terminal of the voltage detection and control circuit. When the voltage to be detected V _X is greater than the voltage value of the comparison signal V _det , the output of the control signal V _ctrl is a high level; When the voltage V _X is less than the voltage value of the comparison signal V _det , the output of the control signal V _ctrl is at a low level.

When the external clock signal clk is at a low level, the gates of the fourth PMOS transistor M1, the fifth PMOS transistor M2, and the sixth PMOS transistor M3 connected by the external clock signal clk are all at a low level, and the dynamic The fourth PMOS transistor M1, the fifth PMOS transistor M2, and the sixth PMOS transistor M3 in the amplifier are turned on, the gate of the sixth NMOS transistor M7 connected to the external clock signal clk is also at a low level, and the sixth NMOS transistor M7 is turned off , the negative phase output terminal V ₁ , the positive phase output terminal V ₂ and the internal node V _x of the dynamic amplifier are charged to the power supply voltage V _DD , and the same external clock signal clk is connected to the voltage operation module 403, wherein the external clock signal clk is connected to the first The grid of the fifth PMOS transistor M9 turns on the fifth PMOS transistor M9, the external control clock clk is connected to the input terminals of the first inverter INV1, the second inverter INV2, and the third inverter INV3, and the external control clock clk Make the gate of the first NMOS transistor MN1 connected to the output terminal of the second inverter INV2 be at a high level, thereby controlling the conduction of the first NMOS transistor MN1; the external clock signal clk makes the output terminal of the first inverter INV1 connected to the The gate of the first PMOS transistor MP1 is at a high level, thereby controlling the first PMOS transistor MP1 to be turned off; the external clock signal clk makes the gate of the second NMOS transistor MN2 connected to the output terminal of the third inverter INV3 be at a high level, Therefore, the second NMOS transistor MN2 is controlled to be turned on, and then the upper plate voltage of the first capacitor _C3 is charged to the reference buffer voltage V _refbuf output by the reference voltage output buffer module 402, and the lower plate voltage of the first capacitor _C3 is charged to discharge to the ground, then, the voltage of the internal node V _top and the comparison signal V _det of the voltage operation module 403 can be expressed as:

V _top = V _refbuf

V _det =0

The negative phase input terminal voltage of the comparator 405 inside the comparator module 404 is the comparison voltage V _det output by the voltage operation module 403. For the comparator 405, the drain of the fifth PMOS transistor M2 in the dynamic amplifier connected to the positive phase input terminal of the comparator module 404 is The terminal node, that is, the first input terminal V _x of the voltage detection and control circuit is charged to the power supply voltage V _DD , V _DD >V _det , the output terminal of the comparator 405 is connected to the output terminal of the comparator module 404, so that the output control signal The voltage of V _ctrl rises to a high level, thereby controlling the closing of the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2, so that the negative phase output terminal V ₁ of the dynamic amplifier is connected to the upper plate of the fourth capacitor C _LN , and the dynamic The non-inverting output terminal V ₂ of the amplifier is connected to the upper plate of the fifth capacitor C _LP , and the voltages of the upper plates of the fourth capacitor C _LN and the fifth capacitor C _LP are both the power supply voltage V _DD , which are connected to the control signal V _ctrl The gate voltage of the fifth NMOS transistor M6 of the dynamic amplifier is high level, then the fifth NMOS transistor M6 is turned on, but because the sixth NMOS transistor M7 is turned off, the entire dynamic amplifier is in the reset phase, and the positive voltage of the dynamic amplifier The voltages at the phase output and the negative phase output are:

V _outn =V ₁ =V _DD

V _outp =V ₂ =V _DD

When the external clock signal clk changes from low level to high level, the dynamic amplifier starts to amplify. The specific process is as follows: the gate of the fourth PMOS transistor M1 connected by the external clock signal clk, the gate of the fifth PMOS transistor M2, The gates of the sixth PMOS transistor M3 all change to a high level, controlling the fourth PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 to be turned off, and at the same time, the external clock signal clk makes the sixth NMOS transistor M7 The gate becomes high level, the sixth NMOS transistor M7 is turned on, the gates of the third NMOS transistor M4 and the fourth NMOS transistor M5 of the input pair are respectively connected to the positive-phase input voltage V _ip and the negative-phase input voltage V _in , and start Discharge the upper plate voltage V _outn of the fourth capacitor C _LN and the upper plate voltage V _outp of the fifth capacitor C _LP (the positive-phase input voltage V _ip and the negative-phase input voltage V _in remain unchanged during amplification), define the first The threshold voltages of the third NMOS transistor M4 and the fourth NMOS transistor M5 are equal and both are V _th , and the β=C _ox *μ*W/L of the two are also equal, and the relationship between the output voltage and the input voltage and time is as follows:

The same external clock signal clk is connected to the power supply voltage fluctuation detection module 403, wherein the external clock signal clk is connected to the gate of the second PMOS transistor MP2 to turn off the second PMOS transistor MP2, and the external clock signal clk is connected to the first inverter INV1, The input terminal of the second inverter INV2 and the third inverter INV3, the external clock signal clk makes the gate of the first NMOS transistor MN1 connected to the output terminal of the second inverter INV2 be low level, and controls the first NMOS transistor MN1 is turned off, the external clock signal clk makes the gate of the first PMOS transistor MP1 connected to the output terminal of the first inverter INV1 low level, thereby controlling the conduction of the first PMOS transistor MP1, and the external clock signal clk makes the third inverter The gate of the second NMOS transistor MN2 connected to the output terminal of the phase device INV3 is at a low level, and the second NMOS transistor MN2 is controlled to be turned off. Then, the upper plate voltage of the first capacitor C ₃ is charged to the power supply voltage V _DD , and the second NMOS transistor MN2 is turned off. The lower plate voltage V _det of the five capacitors C ₃ is expressed as:

V _det = V _DD - _{V refbuf}

The negative-phase input terminal voltage of the comparator 405 inside the comparator module 404 is the voltage of the comparison signal V _det of the output of the voltage operation module 403. For the comparator 405, its positive-phase input terminal is connected to the fifth PMOS transistor in the dynamic amplifier. The drain terminal V _x of M2, the voltage at the point V _x is expressed as:

During the amplification process, the positive-phase input terminal voltage V _x of the comparator 405 inside the comparator module 404 decreases with the amplification time, the negative-phase input terminal is the comparison signal V _det output by the voltage operation module 403, and the positive-phase input terminal of the comparator 405 The voltage V _x gradually decreases from V _DD , once the positive phase input voltage V _x of the comparator 405 is lower than the negative phase input terminal voltage V _det , the control signal V _ctrl output by the comparator 405 will change from high level to low level to control The first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 are turned off, disconnect the negative-phase output terminal of the dynamic amplifier and the connection of the upper plate of the fourth capacitor C _LN , and disconnect the positive-phase output terminal of the dynamic amplifier and the fifth capacitor C _LP is connected to the upper plate, and the fifth NMOS transistor M6 is turned off at the same time. The amplification time is determined by the time t when the voltage V _x of the non-inverting input terminal of the comparator 405 drops from V _DD to V _det :

After the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 are turned off, the upper plate voltages of the fourth capacitor C _LN and the fifth capacitor C _LP are the negative-phase output voltage and the positive-phase output voltage of the amplified dynamic amplifier, and It will not change until the next reset, and the corresponding gain of the dynamic amplifier is expressed as:

In the above formula, V _cm is the common-mode level of input differential signals V _ip and V _in . When the difference between V _ip and V _in is small, the gain expression can be simplified as:

Through the above series of operations, it can be found that the gain of the dynamic amplifier remains unchanged under the fluctuation of the power supply voltage. It should be noted that the non-inverting input terminal of the reference voltage output buffer module 402 is a reference voltage generated outside the module that does not change with the voltage. V _ref , the V _refbuf obtained by the reference voltage output buffer module 402 can be adjusted through different design structures and design parameters (design V _refbuf =V _ref in this embodiment).

To sum up, in this embodiment, the voltage detection and control circuit 401 replaces the common mode detector CMD in the traditional dynamic amplifier, detects the change of the power supply voltage through the voltage operation module 403 and obtains different values of the comparison signal V det, and obtains different values of the comparison signal V _det through The combination of the comparator module 404 and the corresponding operation of the dynamic amplifier changes the amplification time of the dynamic amplifier and corrects the amplification factor of the dynamic amplifier under power supply voltage fluctuations, thus obtaining a dynamic amplifier with stable gain characteristics under voltage fluctuations, which overcomes the traditional dynamic amplifier power supply The influence of voltage variation and fluctuation on the gain optimizes the performance of the dynamic amplifier to a certain extent and expands the application range of the dynamic amplifier.

It is worth noting that the voltage detection and control circuit provided by the present invention can not only be used in the dynamic amplifier to stabilize the gain of the dynamic amplifier, but also can be used in other suitable scenarios for detecting voltage and providing control signals as required. As shown in Figure 8, the present invention is applied to the field of voltage monitoring in the embodiment. The input end of the reference voltage output buffer module is connected to an external reference voltage V _ref2 , and its output end is connected to the second input end of the voltage operation module; the voltage operation module The first input terminal of the comparator module is connected to another external reference voltage V _ref1 , and its clock signal input terminal is connected to the external clock signal clk; the positive input terminal of the comparator module is connected to the output terminal of the voltage operation module, and its negative input terminal is connected to the external to-be-detected voltage V _i .

When the external clock signal clk is low level, the voltage detection and control circuit in the present embodiment is in the reset state, and the output signal V _det =0 of the voltage operation module, the external reference voltage V _ref1 and V can be selected voluntarily according to actual needs. After selecting the value of _ref2 , wait until it is stable, set the external clock signal clk to high level, and enable the monitoring function, then V _det obtained through the processing of the voltage operation module = V _ref1 -V _ref2 , at this time the basic function of the circuit It can be expressed as: under normal circumstances V _i >V _det , the output control signal V _ctrl is high level, once V _i <V _det occurs during the monitoring period, the output control signal V _ctrl becomes low level, the output can be used as The flag signal to judge the relationship between V _i and V _det cooperates with the peripheral circuit to realize the basic function of voltage monitoring.

The dynamic amplifier structure with a gain correction module in the above embodiments is applicable to various integrated circuit (IC) systems, and can also be used as an independent intellectual property IP (Intellectual Property).

Although the content of a dynamic amplifier gain correction circuit against voltage fluctuations of the present invention has been disclosed as an example, it is not intended to limit the present invention. If those skilled in the art do not depart from the spirit of the present invention, it is not essential Any changes or improvements should fall within the protection scope of the claims of the present invention.

Claims (4)

1. A voltage detection and control circuit, including a reference voltage output buffer module (402), a voltage operation module (403) and a comparator module (404), The input end of the reference voltage output buffer module (402) is connected to the reference voltage, and its output end is connected to the second input end of the voltage calculation module (403); The first input terminal of the comparator module (404) is connected to the output terminal of the voltage calculation module (403), the second input terminal thereof is connected to the voltage to be detected, and its output terminal is used as the output terminal of the voltage detection and control circuit ; It is characterized in that the voltage operation module (403) includes a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a first capacitor (C ₃ ), a first NMOS transistor (MN1), second NMOS transistor (MN2), first PMOS transistor (MP1) and second PMOS transistor (MP2), The source of the first PMOS transistor (MP1) is used as the first input terminal of the voltage calculation module (403) to connect to the external adjustment voltage, its gate is connected to the output terminal of the first inverter (INV1), and its drain is connected to the first inverter (INV1). The drains of an NMOS transistor (MN1) and the second PMOS transistor (MP2) and the upper plate of the first capacitor (C ₃ ); The input terminal of the second inverter (INV2) is connected to the input terminal of the first inverter (INV1) and connected to the external clock signal (clk), and its output terminal is connected to the gate of the first NMOS transistor (MN1); The source of the second PMOS transistor (MP2) is connected to the source of the first NMOS transistor (MN1) and used as the second input terminal of the voltage calculation module (403), and its gate is connected to the third inverter (INV3). The input terminal is connected to an external clock signal (clk); The gate of the second NMOS transistor (MN2) is connected to the output terminal of the third inverter (INV3), and its drain is connected to the lower plate of the first capacitor (C ₃ ) and used as the output of the voltage calculation module (403) terminal, its source is grounded. 2. The voltage detection and control circuit according to claim 1, characterized in that, the reference voltage output buffer module (402) comprises an operational amplifier, a first resistor (R1) and a third PMOS transistor (MP3), The positive input terminal of the operational amplifier is connected to the reference voltage, and its negative input terminal is connected to the drain of the third PMOS transistor (MP3) and one end of the first resistor (R1) as the reference voltage output buffer module (402) The output end of the resistor is connected to the gate of the third PMOS transistor (MP3), the source of the third PMOS transistor (MP3) is connected to the power supply voltage, and the other end of the first resistor (R1) is grounded. 3. The voltage detection and control circuit according to claim 1, characterized in that, the comparator module (404) comprises a comparator (405), and the negative input terminal of the comparator (405) is connected to the The output terminal of the voltage calculation module (403) is connected to the positive input terminal of the voltage to be detected, and its output terminal is used as the output terminal of the voltage detection and control circuit. 4. The voltage detection and control circuit according to claim 1, characterized in that, the voltage value of the external adjustment voltage is greater than the voltage value of the output terminal of the reference voltage output buffer module (402).