CN108233934A

CN108233934A - A kind of clock adjustment circuits for successive approximation analog-digital converter

Info

Publication number: CN108233934A
Application number: CN201711246882.XA
Authority: CN
Inventors: 赵英瑞; 陈艳; 杨颖�
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2017-12-01
Filing date: 2017-12-01
Publication date: 2018-06-29

Abstract

The invention discloses a kind of clock adjustment circuits for successive approximation analog-digital converter, which includes delay circuit, control logic circuit.The clock signal of successive approximation analog-digital converter enters comparator circuit after clock adjustment circuits, and control comparator carries out voltage comparison.By adjusting of the clock adjustment circuits to clock signal, conducive to the conversion speed of successive approximation analog-digital converter is improved, conducive to the power consumption of successive approximation analog-digital converter is reduced.

Description

A kind of clock adjustment circuits for successive approximation analog-digital converter

Technical field

The present invention relates to one kind for clock adjustment circuits, the analog-digital converter of clock signal is suitable for inclusion in, is especially fitted For successive approximation analog-digital converter.

Background technology

Analog-digital converter is the critical component of simulation system and digital display circuit interface, is widely used in always for a long time The fields such as communication, military and consumer electronics, with the fast development of computer and communications industry, analog-digital converter is set portable Standby upper application development is rapid, just gradually develops to high speed, high-precision and the direction of low-power consumption.Main modulus currently on the market Transducer type includes：Successive approximation (SAR), sigma-delta type, pipeline-type.Sigma-delta type can realize very high resolution ratio, Pipeline-type can realize very high sampling rate, both structures are designed to meet the market of particular demands.By Secondary approximant analog-digital converter be middle high-resolution, middling speed sample rate, low-power consumption application common structure.In face of what is quickly grown Portable market, successive approximation analog-digital converter obtain demand driving and fast-developing, to successive approximation analog-digital converter Operating rate will be promoted further, and power consumption needs further to decline.Clock adjustment circuits of the present invention, by adjusting gradually The clock signal of comparator in approximant analog-digital converter, conducive to the operating rate and drop of successive approximation analog-digital converter is improved Low-power consumption.

Invention content

The technical problem to be solved by the present invention is to improve a kind of clock adjustings for successive approximation analog-digital converter Circuit, it can improve the operating rate of successive approximation analog-digital converter and reduce the work of successive approximation analog-digital converter Power consumption.

The present invention a kind of clock adjustment circuits for successive approximation analog-digital converter, mainly include delay circuit with Control logic circuit, the delay circuit include the delay cell of several series connection, and the control logic circuit includes several switches. Delay cell of the clock input signal by series connection, exports a clock signal, each clock signal after each delay cell Connect the switch in a control logic circuit, each switch is by control signal behavior wherein switch conduction all the way, by this Road clock signal is connected to the comparator clock of the successive approximation analog-digital converter.

Above-mentioned delay circuit includes several delay cells, and delay cell can pass through MOS transistor, passive resistance, capacitance It realizes.Above-mentioned control logic circuit includes several switches, switchs and is realized by MOS transistor.

Description of the drawings

Fig. 1 is the approximant analog-digital converter structure figure of conventional successive

Fig. 2 is successive approximation analog-digital converter structure figure of the present invention

Fig. 3 is the detailed structure view of clock adjustment circuits according to the present invention

Fig. 4 is clock adjustment circuits working timing figure.

Specific embodiment

The present invention will be further described in detail with reference to the accompanying drawings and detailed description.

For one kind of the present invention for successive approximation analog-digital converter clock adjustment circuits, structure is concise, is conducive to improve The operating rate of successive approximation analog-digital converter advantageously reduces the power consumption of successive approximation analog-digital converter, with reference to Attached drawing introduces specific embodiment.

As shown in Figure 1, for the approximant analog-digital converter structure of conventional successive.Mainly include sampling hold circuit, comparator, Approach by inchmeal logic circuit, D/A converting circuit.Wherein input clock signal is connected to comparator and Approach by inchmeal logic circuit. The clock of comparator is synchronous with the clock of Approach by inchmeal logic circuit.This clock rising edge to failing edge high level Period, the voltage signal that D/A converting circuit is exported to comparator one end are established, and are adopted with coming from for the comparator other end The voltage of sample holding circuit is compared, and in clock falling edge, comparator completion voltage compares.Therefore, successive approximation is improved The operating rate of analog-digital converter needs to improve the frequency of input clock, and is to ensure that comparator is correctly completed electricity in shorter time Pressure ratio compared with, need increase comparator power consumption.Conversely, to reduce power consumption, correct establish for guarantee voltage is compared with correct, It then needs to reduce input clock frequency.

As shown in Fig. 2, for successive approximation analog-digital converter structure figure of the present invention.It is main to include sampling holding electricity Road, comparator, Approach by inchmeal logic circuit, D/A converting circuit and clock adjustment circuits.Wherein input clock signal is connected to Approach by inchmeal logic circuit and clock adjustment circuits, clock signal are input to comparator again after clock adjustment circuits are adjusted. Relative to the approximant analog-digital converter of conventional successive, successive approximation analog-digital converter of the present invention increases a clock tune Economize on electricity road, the clock of comparator and the clock of Approach by inchmeal logic circuit are asynchronous, but pass through the delay of certain time.This Sample will increase in the time that the constant successive approximation analog-digital converter of input clock frequency is completed Voltage Establishment and compared Add, conducive to the power consumption of comparator is reduced.Or in the case of keeping power consumption constant, the frequency of input clock is improved, improves and approaches The operating rate of formula analog-digital converter.

As shown in figure 3, the detailed construction of the clock adjustment circuits for successive approximation analog-digital converter of the present invention Figure mainly includes delay circuit and logic control circuit.Wherein delay circuit include several delay cells, delay cell by MOS transistor or passive resistance, capacitance are realized；Logic circuit includes several switches, and switch is realized by MOS transistor.By The clock signal of different delayed time unit selects output all the way as comparator clock by logic control circuit.Of delay cell Number and delay time, which can emulate or test according to specification demands, to be determined.Logic switch can be by single MOS transistor or CMOS transistor It realizes.

As shown in figure 4, the clock adjustment circuits working timing figure for successive approximation analog-digital converter of the present invention. T1 is time of the Approach by inchmeal logic circuit rising edge clock to failing edge, is compared for the approximant analog-digital converter of conventional successive Device input voltage is established and is compared, and the failing edge of Approach by inchmeal logic circuit clock is used to compare to the time between rising edge As a result output and the delay of logic circuit.T2 be Approach by inchmeal logic circuit rising edge clock to comparator clock falling edge when Between, it establishes and compares for successive approximation analog-digital converter comparator input voltage of the present invention, and comparator clock Failing edge is exported to the time between Approach by inchmeal logic circuit rising edge clock for comparison result and the delay of logic circuit. T3 is the time that T2 is differed with T1.T2 is longer T3 than the T1 times, and the length of T3 can be adjusted by clock adjustment circuits.Generally Successive approximation analog-digital converter input voltage is established and relatively required time is longer than comparator results output and logic circuit prolongs The slow time, therefore within a clock cycle of the approximant analog-digital converter of conventional successive, the time of high level half period is used In input voltage establish and compare be limit successive approximation analog-digital converter operating rate principal element.One kind of the present invention For successive approximation analog-digital converter clock adjustment circuits, comparator input can be increased in similary input clock frequency Voltage Establishment and the time compared, conducive to the input clock of successive approximation analog-digital converter is improved, conducive to Approach by inchmeal is reduced The power consumption of formula analog-digital converter.

Although the present invention is illustrated using specific embodiment, it is not intended to limit the present invention's to the explanation of embodiment Range.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention In the case of, it easily carry out various modifications or embodiment can be combined.

Claims

1. a kind of clock adjustment circuits for successive approximation analog-digital converter mainly include delay circuit and control logic electricity Road, the delay circuit include the delay cell of several series connection, and the control logic circuit includes several switches, clock input letter Delay cell number by series connection, exports a clock signal, each clock signal connects an institute after each delay cell The switch in control logic circuit is stated, each switch is by control signal behavior wherein switch conduction all the way, by the road clock signal It is connected to the comparator clock of the successive approximation analog-digital converter.

2. clock adjustment circuits as described in claim 1, it is characterised in that：The delay circuit includes several delay cells, Delay cell can be realized by MOS transistor, passive resistance, capacitance.

3. clock adjustment circuits as described in claim 1, it is characterised in that：The control logic circuit includes several switches, Switch is realized by MOS transistor.