CN108231731B - Bonding pad structure and manufacturing method thereof - Google Patents

Abstract

A pad structure includes a plurality of material pairs and a plurality of pads. The plurality of material pairs are stacked on a substrate to form a stepped structure. One step of the stepped structure includes a material pair. Each material pair includes a conductor layer and a dielectric layer located on the conductor layer. Each pad is embedded in one step of the stepped structure and exposed to the dielectric layer corresponding to the step and another step above the step. The thickness of one of the pads is greater than the thickness of one of the conductor layers.

Description

Pad structure and manufacturing method thereof

technical field

The present invention relates to a pad structure and a manufacturing method thereof, and more particularly, to a pad structure for a three-dimensional memory element and a manufacturing method thereof.

Background technique

As the integration of storage elements increases, in order to achieve the goals of high density and high performance, it has become a trend to replace two-dimensional storage elements with three-dimensional storage elements. The vertical storage element is one of the three-dimensional storage elements. Although vertical storage elements can increase the memory capacity per unit area, they also increase the difficulty of interconnecting the vertical storage elements.

Generally speaking, three-dimensional memory devices often use conductor layers with a stepped structure as pads, and use the pads and the contact windows thereon as interconnect structures, so as to facilitate the connection between elements in each layer and other elements. However, when the contact window etching process is performed, due to the height difference between the pads at different positions in the stepped structure and the top surface of the dielectric layer thereon, the top pad in the stepped structure is over-etched, and further This causes the contact opening to extend through the topmost pad and onto the conductor layer below it. In this way, the subsequently formed contact window will electrically connect the two pads or conductor layers, thereby causing electrical failure of the device. Therefore, how to provide a pad structure and a manufacturing method thereof so as to avoid excessive etching of the pad structure with the stepped structure is an important topic at present.

SUMMARY OF THE INVENTION

The present invention provides a pad structure with a stepped structure and a manufacturing method thereof, which can prevent the electrical failure problem caused by excessive etching during the contact opening process.

The present invention provides a pad structure with a stepped structure and a manufacturing method thereof, which can improve the process margin and increase the process yield.

The present invention provides a pad structure, which includes a plurality of material pairs and a plurality of pads. A plurality of material pairs are stacked on the substrate to form a stepped structure. The first order of the ladder structure consists of a material pair. Each material pair includes a conductor layer and a dielectric layer overlying the conductor layer. Each pad is embedded in a level of the stepped structure and exposed to the dielectric layer corresponding to the level and another level above the level. The thickness of one of the pads is greater than the thickness of one of the conductor layers.

In an embodiment of the present invention, the plurality of material pairs extend along the plane of the XY direction. One of the plurality of material pairs protrudes from a side of the other of the plurality of material pairs above it and exposes the corresponding surface of the pad.

In an embodiment of the present invention, the pad structure further includes a plurality of plugs extending along the Z direction and respectively disposed on the pad.

In an embodiment of the present invention, the width of each pad is larger than the bottom width of the corresponding plug.

In an embodiment of the present invention, the material of the plug is the same as the material of the pad.

In an embodiment of the present invention, the material of the plug is different from the material of the pad.

In an embodiment of the present invention, from a top view, the shape of the pad includes a square, a circle, a rectangle, a strip, or a combination thereof.

In an embodiment of the present invention, from a top view, when the shape of the pads is elongated, the pads are arranged along the X direction and extend along the Y direction.

In an embodiment of the present invention, the pad structure further includes a pad layer located between the stepped structure and the substrate.

The present invention provides a manufacturing method of a pad structure, the steps of which are as follows. A stacked structure is formed on the substrate. The stacked structure includes a plurality of material pairs stacked on each other. The plurality of material pairs include a first material pair to an Nth material pair from top to bottom, where N is an integer greater than 1. Each material pair includes a first layer and a second layer on the first layer. A plurality of first openings are formed in the first material pair. The first opening exposes the top surface of the second pair of materials. A patterning process is performed to pattern the stacked structure into a stepped structure, and a second opening is formed in each step of the stepped structure. The vertical projection positions of the second openings correspond to the positions of the first openings, respectively. A plurality of third layers are respectively filled into the second openings, wherein the thickness of one of the third layers is greater than that of one of the first layers.

In an embodiment of the present invention, after the third layers are respectively filled into the second openings, the following steps are further included. A dielectric layer is formed on the substrate. The dielectric layer covers the surface of the stepped structure and the top surface of the third layer. A plurality of contact openings are formed in the dielectric layer. The contact window openings expose the top surfaces of the third layers, respectively. A plurality of plugs are respectively filled into the openings of the contact windows, so that one of the plugs is connected to the corresponding third layer.

In an embodiment of the present invention, the material of the first layer includes silicon nitride, the material of the second layer includes silicon oxide, and the material of the third layer includes silicon nitride.

In an embodiment of the present invention, after the dielectric layer is formed on the substrate and before the contact opening is formed, a tungsten substitution process is further included to replace the material of the first layer and the material of the third layer with tungsten (W) .

In an embodiment of the present invention, the tungsten substitution process includes the following steps. At least one slit is formed in the dielectric layer and the stepped structure. At least one slit extends to the bottom surface of the stepped structure to expose a partial cross-section of the first layer of the plurality of material pairs. An etchant is applied in at least one slit to remove the first and third layers to form a plurality of voids. A deposition process is performed to form a plurality of tungsten layers in the voids, respectively.

In an embodiment of the present invention, the material of the first layer includes polysilicon, the material of the second layer includes silicon oxide, and the material of the third layer includes polysilicon.

In an embodiment of the present invention, the material of the plug includes tungsten (W).

In an embodiment of the present invention, the steps of performing the patterning process are as follows. A photoresist layer is formed on the stacked structure. The photoresist layer exposes one of the first openings. A first etching process is performed to remove a portion of the first material pair and a portion of the second material pair to transfer the shape of one of the first openings into the second material pair. The photoresist layer is trimmed to expose the other of the first openings. A second etching process is performed to remove a portion of the first material pair, a portion of the second material pair, and a portion of the third material pair to transfer the shape of the other of the first openings into the second material pair and the first openings The shape of one is transferred to the third material pair. The steps of trimming the photoresist layer and performing the second etching process are repeated until a stepped structure is formed.

In an embodiment of the present invention, the manufacturing method of the pad structure further includes forming a pad layer between the stepped structure and the substrate.

Based on the above, this embodiment can be achieved by forming a plurality of openings in the topmost material pair of the stacked structure. Next, the stacked structure is patterned into a stepped structure to transfer and form the openings in each step of the stepped structure. Then, conductive material is filled into the openings to form pads. Therefore, compared with the conventional pads, the thickness of the pads of the present embodiment is thicker, which can prevent electrical failures caused by excessive etching during the contact opening process. In addition, using a thicker pad as an etch stop layer for forming the contact opening can improve the process margin of the contact opening process and increase the process yield.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1 is a schematic top view of a memory device according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view taken along the line A-A' in Fig. 1 .

3A to 3O are schematic cross-sectional views of the manufacturing flow along the line A-A' of FIG. 1 .

4A to 4B are schematic top views of a manufacturing process of a pad structure according to the first embodiment of the present invention.

5A to 5B are schematic cross-sectional views taken along the line B-B' of FIGS. 4A to 4B, respectively.

6A to 6B are schematic top views of a manufacturing process of a pad structure according to a second embodiment of the present invention.

7A to 7B are schematic cross-sectional views taken along the line C-C' of FIGS. 6A to 6B, respectively.

8A to 8B are schematic top views of a manufacturing process of a pad structure according to a third embodiment of the present invention.

9A to 9B are schematic cross-sectional views taken along the line D-D' of FIGS. 8A to 8B, respectively.

【Symbol Description】

10: Pad area

20: Array area

30: Surrounding area

100: base

101: Cushion

102: Stacked Structure

102’: Ladder structure

102a, 102b, 102c, 102d, 102e, 102f, 132, 132a, 132b, 132c, 132d, 132e, 132f: Material pairs

103a, 103b, 103c, 103d, 103e, 103f: Openings

104a, 104b, 104c, 104d, 104e, 104f: first layer

105a, 105b, 105c, 105d, 105e, 105f: Openings

106a, 106b, 106c, 106d, 106e, 106f: second layer (dielectric layer)

108, 110: photoresist layer

112: Insulation layer

112a, 112b, 112c, 112d, 112e, 112f: the third layer

114a, 114b, 114c, 114d, 114e, 114f: conductor layers

116, 116a: Dielectric layer

120, 120a, 120b, 120c, 120d, 120e, 120f, 220, 320; degree pad

122a, 122b, 122c, 122d, 122e, 122f: Contact window openings

124, 124a, 124b, 124c, 124d, 124e, 124f: Plugs

X, Y, Z: direction

D1, D2: distance

H1, H2, H3: height

T1, T2, T3: Thickness

S: normative value

ECDc, ECDs: Width

Detailed ways

The present invention will be more fully explained with reference to the accompanying drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the figures may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the detailed description in the following paragraphs will not be repeated.

FIG. 1 is a schematic top view of a memory device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along the line A-A' in Fig. 1 .

Referring to FIG. 1 and FIG. 2 , a first embodiment of the present invention provides a memory device including a substrate 100 . From a top view, the substrate 100 includes a pad area 10 , an array area 20 and a peripheral area 30 . The pad area 10 is located between the array area 20 and the peripheral area 30 . In one embodiment, the array area 20 may be, for example, a memory cell array area. The peripheral region 30 may include a plurality of low-voltage semiconductor elements, such as low-voltage N-type metal-oxide-semiconductor (LV-NMOS) transistors, low-voltage P-type metal-oxide-semiconductor (LV-PMOS) transistors, or a combination thereof. From the cross-sectional view, as shown in FIG. 2 , the pad area 10 includes a plurality of material pairs 132 having a stepped structure, a plurality of pads 120 respectively embedded in the plurality of material pairs 132 , and respectively disposed in the plurality of pads 120 A plurality of plugs 124 on. The pads 120 and the plugs 124 can be used as interconnect structures to electrically connect elements at each stage of the ladder structure with other elements.

Specifically, referring to FIG. 1 and FIG. 2 simultaneously, a plurality of material pairs 132 extend from the array region 20 and terminate in the pad region 10 . The plurality of material pairs 132 extend along the plane of the XY direction and are stacked on each other to form a stepped structure. The first stage of the stepped structure includes a material pair. Each material pair includes a conductor layer (or first layer) and a dielectric layer (or second layer) on the conductor layer. For example, as shown in FIG. 2, the conductor layer 114a and the dielectric layer 106a can be regarded as a material pair 132a or the first stage of the stepped structure; and the conductor layer 114b and the dielectric layer 106b can be regarded as another material pair 132b Or another step of the ladder structure. The configurations of other material pairs are the same as the above, and are not repeated here. In one embodiment, the combination of the conductor layer 114a and the dielectric layer 106a can be regarded as the bottommost material pair 132a, which protrudes from one side of the material pair 132b formed by the conductor layer 114b and the dielectric layer 106b above it, so that The pads 120a embedded in the conductor layer 114a and the dielectric layer 106a are exposed. Similarly, the material pair 132b formed by the conductor layer 114b and the dielectric layer 106b protrudes from the side of the material pair 132c formed by the conductor layer 114c and the dielectric layer 106c above it, so as to be embedded in the conductor layer 114b and the dielectric layer 132c. Pads 120b in layer 106b are exposed. The stacking method of other material pairs is the same as the above, and will not be repeated here.

On the other hand, as shown in FIG. 2 , the plurality of plugs 124 extend along the Z direction and are respectively disposed on the plurality of pads 120 . For example, the plug 124a is configured and connected to the pad 120a, so that the plug 124a is electrically connected to the conductor layer 114a through the pad 120a. Similarly, the plug 124b is configured and connected to the pad 120b, so that the plug 124b is electrically connected to the conductor layer 114b through the pad 120b. The configurations and connection methods of other plugs are the same as those described above, and will not be repeated here.

In addition, the pad region 10 further includes a plurality of slits 130 extending from the array region 20 and terminating at the pad region 10 . In detail, the plurality of slits 130 extend along the X direction and are arranged along the Y direction, such that each slit 130 is located between two adjacent rows of plugs 124 (which extend along the X direction). Although only the plugs 124 and the three slits 130 arranged in a 7×4 array are shown in FIG. 1 , the present invention is not limited thereto. In other embodiments, the number and arrangement of the plugs 124 and the slits 130 can be adjusted according to the needs of the designer.

It should be noted that the pads 120a-120f are not only used to electrically connect the plugs 124a-124f and the conductor layers 114a-114f, but also serve as etch stop layers during the contact opening process. For example, as shown in the enlarged view of the pad 120a in FIG. 2, since the thickness T1 of the pad 120a is greater than the thickness T2 of the conductor layer 114a, the pad 120a with a thicker thickness can effectively block the contact window opening process. Over-etching. That is, even the topmost plug 124f does not penetrate through the topmost pad 120f and extend to the conductor layer 114e below it. Therefore, the thicker pads 120 in this embodiment can prevent electrical failures caused by over-etching during the contact opening process. The thickness T1 of the pad 120a may be, for example, 70 nanometers (nm) to 90 nm.

3A to 3O are schematic cross-sectional views of the manufacturing flow along the line A-A' of FIG. 1 .

Referring to FIG. 3A , first, a substrate 100 is provided. In one embodiment, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate. Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed by IVA group atoms, such as silicon carbide or germanium silicide, or a semiconductor compound formed by IIIA group atoms and VA group atoms, such as gallium arsenide.

Next, the pad layer 101 is formed on the substrate 100 . In one embodiment, the pad layer 101 may be a silicon oxide layer, which may be used to protect the surface of the substrate 100 .

After that, a stack structure 102 is formed on the pad layer 101 . In detail, the stack structure 102 includes a plurality of material pairs 102a-102f stacked on each other. As shown in FIG. 3A, material pair 102a may be considered the bottommost material pair; and material pair 102f may be considered the topmost material pair. The material pair 102a includes a first layer 104a and a second layer 106a on the first layer 104a. Similarly, material pair 102b includes a first layer 104b and a second layer 106b overlying the first layer 104b. The configurations of other material pairs 102c-102f are as described above, and will not be repeated here. In one embodiment, the first layers 104a-104f may be silicon nitride layers and the second layers 106a-106f may be silicon oxide layers. In one embodiment, one of the silicon nitride layers 104a-104f has a thickness of 20 nm to 40 nm, which may be, for example, 28 nm. The thickness of one of the silicon oxide layers 106a-106f is 40 nm to 60 nm, which may be, for example, 52 nm. In alternate embodiments, the first layers 104a-104f may be polysilicon layers, and the second layers 106a-106f may be silicon oxide layers. Although only 6 material pairs are shown in FIG. 3A , the present invention is not limited thereto. In other embodiments, the number of material pairs may include 8, 15, 21, 27, 33, 39, or more.

Then, a photoresist layer 108 is formed on the stacked structure 102 . The photoresist layer 108 has a plurality of openings 103a-103f. The openings 103a-103f expose the top surface of the stack structure 102 (or the second layer 106f). The positions of the openings 103a-103f correspond to the positions of the pads 120a-120f formed subsequently (as shown in FIG. 3O). That is to say, the vertical projection positions of the openings 103a-103f overlap with the positions of the subsequently formed pads 120a-120f, respectively.

Referring to FIG. 3A and FIG. 3B , using the photoresist layer 108 as a mask, an etching process is performed and a part of the material pair 102f is removed to form a plurality of openings 105a-105f in the material pair 102f. Openings 105a-105f expose the top surface of material pair 102e (or second layer 106e). In one embodiment, the etching process may include a dry etching process, such as reactive ion etching (Reactive Ion Etching, RIE).

Referring to FIG. 3B and FIG. 3C , the photoresist layer 108 is removed. In one embodiment, the method of removing the photoresist layer 108 may be to perform a wet cleaning process after ashing the photoresist layer 108 with a high-density plasma.

Referring to FIGS. 3C to 3I, a patterning process is performed to pattern the stacked structure 102 into a stepped structure 102'. In detail, referring to FIG. 3C and FIG. 3D first, a photoresist layer 110 is formed on the stacked structure 102 . The photoresist layer 110 exposes the opening 105a and covers the other openings 105b-105f. In one embodiment, the thickness or height H1 of the photoresist layer 110 may be, for example, 4000 nm to 6000 nm.

3D and FIG. 3E , a first etching process is performed using the photoresist layer 110 as a mask to remove part of the material pair 102f exposed to the photoresist layer 110 and part of the material pair 102e exposed to the opening 105a, The shape of the opening 105a is caused to transfer into the material pair 102e. Thus, the opening 105a transferred into the material pair 102e exposes the top surface of the material pair 102d (or the second layer 106d). At this time, as shown in FIG. 3E , the photoresist layer 110 is also etched, so that the thickness or height H2 of the photoresist layer 110 is reduced to 3950 nm to 5950 nm. In one embodiment, the first etching process may include a dry etching process, such as reactive ion etching. In one embodiment, the first etching process may be two etching steps. For example, the first etching process may use the first layer as an etch stop layer and remove material of the second layer. After that, the material of the first layer is removed by using the second layer as an etch stop layer. As such, a thickness of one material pair will be removed during the first etch process. However, the present invention is not limited to this, and in other embodiments, the process parameters of the first etching process can also be adjusted to remove the required thickness or quantity of the material pair.

Referring to FIGS. 3E and 3F, the photoresist layer 110 is trimmed to expose the openings 105b. The trimming refers to pulling back the photoresist layer 110 by a distance D1. In this case, as shown in FIG. 3F, the photoresist layer 110 exposes the openings 105a, 105b. In one embodiment, the distance D1 may be, for example, 400 nm to 600 nm. As the photoresist layer 110 is trimmed and retracted, the thickness of the photoresist layer 110 is also consumed. The thickness of the consumed photoresist layer 110 (ie, the value of the thickness H2 minus the thickness H3 ) is greater than the distance D1 . In one embodiment, the distance D1 may be, for example, 500 nm, and the thickness of the depleted photoresist layer 110 may be, for example, 625 nm. After trimming the photoresist layer 110, the thickness or height H3 of the photoresist layer 110 is reduced to 3325 nm to 5325 nm. That is to say, when the thickness or height H1 of the photoresist layer 110 is thicker, it can perform more patterning and photoresist trimming processes to form a more stepped structure. Therefore, the thickness or height H1 of the photoresist layer 110 can be adjusted as required.

Referring to FIGS. 3F and 3G, a second etching process is performed using the photoresist layer 110 as a mask to remove part of the material pair 102f, part of the material pair 102e, and part of the material pair 102d, so as to transfer the shape of the opening 105a to the into material pair 102d and transfer the shape of opening 105b into material pair 102e. In this case, as shown in Figure 3G, openings 105a transferred to material pair 102d expose the top surface of material pair 102c (or second layer 106c); while openings 105b transferred to material pair 102e expose material pairs 102d (or the top surface of the second layer 106d). At this time, as shown in FIG. 3G , the photoresist layer 110 is also etched, so that the thickness or height H4 of the photoresist layer 110 is reduced to 3275 nm to 5275 nm.

Referring to FIGS. 3G and 3H , the photoresist layer 110 is trimmed so that the photoresist layer 110 is retracted by a distance D2 to expose the opening 105c. In one embodiment, the distance D2 may be, for example, 400 nm to 600 nm.

Referring to FIG. 3H and FIG. 3I, the above-mentioned steps of performing the second etching process and trimming the photoresist layer 110 are repeated until the step structure 102' shown in FIG. 3I is formed. In this case, as shown in FIG. 3I, a plurality of openings 105a-105f are located in each step of the stepped structure 102', respectively.

Referring to FIG. 3I and FIG. 3J , an insulating layer 112 is formed on the substrate 100 . The insulating layer 112 covers the surface of the stepped structure 102' and fills the openings 105a-105f. In one embodiment, the thickness T3 of the insulating layer 112 may be greater than half the width ECDs of the opening 105a to ensure that the openings 105a-105f can be filled. On the other hand, as shown in FIG. 3J , the thickness T3 of the insulating layer 112 must be at least greater than the thickness of one material pair 102a to fill the opening 105a. In one embodiment, the material of the insulating layer 112 includes silicon nitride, and the formation method thereof may be chemical vapor deposition.

Referring to FIGS. 3J and 3K, part of the insulating layer 112 is removed to form third layers 112a-112f in the openings 105a-105f, respectively. In one embodiment, as shown in Figure 3K, the top surface of the third layer 112a is coplanar with the top surface of the material pair 102a. Similarly, the top surface of the third layer 112b is coplanar with the top surface of the material pair 102b. The top surfaces of the other third layers are also coplanar with the top surfaces of the corresponding material pairs, which will not be repeated here.

Referring to FIG. 3K and FIG. 3L , a dielectric layer 116 is formed on the substrate 100 . The dielectric layer 116 covers the surface of the stepped structure 102' and the top surfaces of the third layers 112a-112f. In one embodiment, the material of the dielectric layer 116 includes silicon oxide, and the method for forming the dielectric layer 116 may be to deposit a dielectric material layer on the substrate 100 by chemical vapor deposition. Next, a planarization process, such as chemical mechanical polishing (CMP), is performed to planarize the top surface of the dielectric material layer.

Referring to FIGS. 3L and 3M, a tungsten replacement process is performed to replace the materials of the first layers 104a-104f and the materials of the third layers 112a-112f with tungsten (W). In detail, the steps of the tungsten substitution process are as follows. First, slits 130 are formed in the dielectric layer 116 and the stepped structure 102'. It should be noted that although the cross section of FIG. 3M does not show the slit 130, it can be seen from FIG. 1 that the extending direction of the slit 130 is parallel to the direction of the A-A' line. The slit 130 extends to the bottom surface of the stepped structure 102' to expose a partial cross-section of the first layer 104a-104f of the material pair 102a-102f. An etchant is applied in the slits 130, and the first layers 104a-104f and the third layers 112a-112f are removed to form a plurality of voids (not shown). Next, a deposition process is performed to form a plurality of tungsten layers in the voids, respectively. In this case, as shown in FIG. 3M, after the tungsten replacement process, the first layers 104a-104f are replaced by conductor layers 114a-114f; and the third layers 112a-112f are replaced by pads 120a-120f. In this embodiment, the materials of the conductor layers 114a-114f are the same as those of the pads 120a-120f, which are all tungsten. In one embodiment, the etchant may be a combination of hydrofluoric acid and hot phosphoric acid. In one embodiment, hydrofluoric acid may be applied first, followed by hot phosphoric acid.

In an alternative embodiment, when the first layers 104a-104f are polysilicon layers and the second layers 106a-106f are silicon oxide layers, the tungsten substitution process may not be performed. At this time, the material of the pads 120a-120f may be, for example, polysilicon.

Referring to FIGS. 3M and 3N, a plurality of contact openings 122a-122f are formed in the dielectric layer 116a. The contact window openings 122a-122f expose the surfaces of the pads 120a-120f, respectively. As can be seen from FIG. 3N, the pads 120a-120f can be used as etch stop layers for forming the contact openings 122a-122f. Compared with the distance between the top surface of the pad 120a and the top surface of the dielectric layer 116a, the distance between the top surface of the pad 120f and the top surface of the dielectric layer 116a is shorter. During the process, the contact window opening 122f will first contact the top surface of the top pad 120f, so that the etching loss of the top pad 120f is relatively large. Compared with the thickness of the conventional pads, the thicker pads 120a-120f of the present embodiment can prevent over-etching during the contact opening process (especially over-etching for the topmost pad 120f), by This improves the process margin of the contact opening process and increases the process yield. Incidentally, other processes need to be performed before forming the contact openings 122a-122f. Therefore, the thickness of the dielectric layer 116a of FIG. 3N is thicker than that of the dielectric layer 116 of FIG. 3M.

3N and FIG. 3O, a plurality of plugs 124a-124f are respectively filled in the contact window openings 122a-122f, so that the plugs 124a-124f are respectively connected to the pads 120a-120f. Therefore, the plugs 124a-124f can be electrically connected to the conductor layers 114a-114f through the pads 120a-120f, respectively. The plugs 124a-124f and the pads 120a-120f can be used as interconnect structures to electrically connect the elements of each level of the material pair 132 with the stepped structure to other elements. In detail, the step of filling the plurality of plugs 124a-124f into the contact openings 122a-122f, respectively, includes performing a deposition process to fill the contact openings 122a-122f with a metal material and cover the top of the dielectric layer 116a noodle. Next, a planarization process is performed to remove the metal material on the top surface of the dielectric layer 116a. At this time, as shown in FIG. 3O, the top surfaces of the plugs 124a-124f are coplanar with the top surface of the dielectric layer 116a. In one embodiment, the metal material includes tungsten, and its formation method may be physical vapor deposition or chemical vapor deposition. The planarization process may be a chemical mechanical polishing (CMP) process. In one embodiment, the plugs 124a-124f are of the same material as the pads 120a-120f. In alternate embodiments, the material of the plugs 124a-124f may be different from the material of the pads 120a-120f.

4A to 4B are schematic top views of a manufacturing process of a pad structure according to the first embodiment of the present invention. 5A to 5B are schematic cross-sectional views taken along the line B-B' of FIGS. 4A to 4B, respectively. 6A to 6B are schematic top views of a manufacturing process of a pad structure according to a second embodiment of the present invention. 7A to 7B are schematic cross-sectional views taken along the line C-C' of FIGS. 6A to 6B, respectively. 8A to 8B are schematic top views of a manufacturing process of a pad structure according to a third embodiment of the present invention. 9A to 9B are schematic cross-sectional views taken along the line D-D' of FIGS. 8A to 8B, respectively.

It is worth mentioning that, from a top view, the shape of the pad includes a square (as shown in FIG. 4A ), a rectangle (as shown in FIG. 6A ), a long strip (as shown in FIG. 8A ) or combination. The width of one of the pads is greater than the bottom width of the corresponding plug (or contact window opening).

Please refer to FIG. 4A , FIG. 4B , FIG. 5A and FIG. 5B . In the first embodiment, the shape of the pad 120 is a square, and the shape of the corresponding contact window opening 122 is also a square. In one embodiment, the width ECDs of the pads 120 is greater than the width ECDc of the contact opening 122 plus 2 specification values S (ie, ECDs>ECDc+2S). The so-called specification value S refers to an overlay specification value or an overlay tolerable value, which depends on the exposure machine that performs the contact opening process. For example, when the exposure machine for forming the contact window opening 122 is a 193 nm argon fluoride (ArF) excimer laser stepper (manufacturer is ASML, machine model is 1450H), the specification value S can be, for example, 10 nm to 20nm. It should be noted that although the shape of the pads 120 shown in FIG. 4A is square, the pads 120 actually formed will be circular.

Please refer to FIGS. 6A , 6B, 7A and 7B. In the second embodiment, the shape of the pad 220 is a rectangle, and the shape of the corresponding contact window opening 122 is a square. In one embodiment, the width ECDs of the pads 220 is greater than the width ECDc of the contact opening 122 plus 2 specification values S (ie, ECDs>ECDc+2S).

Please refer to FIG. 8A , FIG. 8B , FIG. 9A and FIG. 9B . In the third embodiment, the shape of the pad 320 is a long strip, and the shape of the corresponding contact window opening 122 is a square. The elongated pads 320 are arranged along the X direction and extend along the Y direction. In one embodiment, the width ECDs of the pads 320 is greater than the width ECDc of the contact opening 122 plus 2 specification values S (ie, ECDs>ECDc+2S).

To sum up, this embodiment can be achieved by forming a plurality of openings in the topmost material pair of the stacked structure. Next, the stacked structure is patterned into a stepped structure to transfer and form the openings in each step of the stepped structure. Then, conductive material is filled into the openings to form pads. Therefore, compared with the conventional pads, the thickness of the pads of the present embodiment is thicker, which can prevent electrical failures caused by excessive etching during the contact opening process. In addition, using a thicker pad as an etch stop layer for forming the contact opening can improve the process margin of the contact opening process and increase the process yield.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person of ordinary skill in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the invention shall be determined by the claims.

Claims (9)

1. A pad structure, characterized in that, comprising: a plurality of material pairs stacked on a substrate to form a stepped structure, a first stage of the stepped structure includes a material pair, and each material pair includes a conductor layer and a dielectric layer on the conductor layer; and a plurality of pads, each of which is embedded in a step of the stepped structure and exposed to the dielectric layer corresponding to the step and another step above the step, wherein one of the pads has a thickness greater than that of the step thickness of one of the conductor layers; further comprising a pad layer between the stepped structure and the substrate; The width of the pad is greater than the width of the contact window opening plus 2 specification values, the specification value being determined by the exposure machine on which the contact window opening process is performed. 2 . The pad structure of claim 1 , wherein the plurality of material pairs extend along a plane in the XY direction, and one of the plurality of material pairs protrudes above the other of the plurality of material pairs. 3 . one side and expose the corresponding surface of the pad. 3 . The pad structure of claim 2 , further comprising a plurality of plugs extending along the Z direction and disposed on the pads respectively, wherein the width of each of the pads is larger than that of the corresponding pads. 4 . Bottom width of the plug. 4 . The pad structure according to claim 1 , wherein from a top view, when the pads are elongated in shape, the pads are arranged along the X direction and extend along the Y direction. 5 . 5. A method for manufacturing a pad structure, comprising: A stack structure is formed on a substrate, the stack structure includes a plurality of material pairs stacked on each other, the plurality of material pairs from top to bottom include a first material pair to an Nth material pair, N is an integer greater than 1, wherein each a material pair including a first layer and a second layer on the first layer; forming a plurality of first openings in the first material pair, the first openings exposing the top surface of the second material pair; A patterning process is performed to pattern the stacked structure into a stepped structure, and a second opening is formed in each step of the stepped structure, wherein the vertical projection positions of the second openings correspond to the first the position of an opening; and A plurality of third layers are respectively filled in the second openings, wherein the thickness of one of the third layers is greater than the thickness of one of the first layers. 6 . The manufacturing method of the pad structure according to claim 5 , wherein after filling the third layers into the second openings respectively, the method further comprises: 6 . forming a dielectric layer on the substrate, the dielectric layer covering the surface of the stepped structure and the top surfaces of the third layers; forming a plurality of contact window openings in the dielectric layer, the contact window openings respectively exposing the top surfaces of the third layers; and A plurality of plugs are respectively filled into the contact window openings, so that one of the plugs is connected to the corresponding third layer. 7 . The manufacturing method of the pad structure according to claim 6 , wherein the materials of the first layers comprise silicon nitride or polysilicon, the materials of the second layers comprise silicon oxide, and the materials of the third layers The materials include silicon nitride or polysilicon. 8 . The manufacturing method of the pad structure according to claim 7 , further comprising performing a tungsten substitution process after forming the dielectric layer on the substrate and before forming the contact openings. 9 . The materials of the first layers and the materials of the third layers are replaced with tungsten (W). 9 . The manufacturing method of the pad structure according to claim 5 , further comprising forming a cushion layer between the stepped structure and the substrate. 10 .

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