CN108154899A - Flush memory device and its method for deleting - Google Patents
Flush memory device and its method for deleting Download PDFInfo
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- CN108154899A CN108154899A CN201810168902.4A CN201810168902A CN108154899A CN 108154899 A CN108154899 A CN 108154899A CN 201810168902 A CN201810168902 A CN 201810168902A CN 108154899 A CN108154899 A CN 108154899A
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- erasing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
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Abstract
The present invention provides a kind of flush memory device and its method for deleting.The flush memory device includes：Multiple storage units, multiple storage unit are divided into multiple blocks；Multiple counters, multiple counter correspond respectively to each block, are counted for the erasing times to block；And control unit, for when carrying out erasing operation to each block, the erasing times of the block are read from the corresponding counter of block, and it further obtains and the corresponding erasing operation parameter of the erasing times, erasing operation carries out the block with the erasing operation parameter read, erasing operation parameter includes erasing voltage.
Description
Technical field
The present invention relates to a kind of semiconductor storage unit and its method for deleting more particularly to a kind of flush memory device and its erasings
Method.
Background technology
Semiconductor memory can be divided into two class of volatile memory and nonvolatile memory, after volatile memory power down
The data that can be lost the memory of, nonvolatile memory protect data even if in the case of cutting off the power.Flush memory device
It is typical nonvolatile semiconductor memory member.Structure based on memory cell array, flush memory device can be divided into NOR flash memory and
NAND flash memory device.The grid of flash cell has the knot for including tunnel insulation layer, floating gate electrode, dielectric layer and control gate
Structure.
In the flash memory of FGS floating gate structure, by floating gate electrode inject or discharge electronics come change storage unit (such as
MOS transistor) threshold voltage, so as to achieve the purpose that storage or release data.In erase process, erasing electrode is applied
Electronics is sucked out from floating gate electrode by tunnel-effect for high pressure.When performing read operation, the floating gate electrode according to accumulation is detected
On amount of electrons variation storage unit (such as MOS transistor) threshold voltage, by the level of the threshold voltage detected
Read data.
Flash memory is typically divided into multiple blocks (sector), and each block includes a certain number of storage units, for one
The flash memory of a little large capacities, is also divided into different bank, and each bank includes a certain number of sector.The erasing operation one of flash memory
As be all as unit of sector, bank or full wafer flash memory.
When write operation is carried out to flash memory (especially NOR flash memory), each position (bit) can be by programming by " 1 "
Become " 0 ", but cannot be revised as " 1 " by " 0 ".It, will before programming operation is performed in order to ensure the correctness of programming operation
Perform erasing operation.Erasing operation can entirely be revised as the value of a sector of flash memory, a bank or full wafer flash memory
“0xFF”.In this way, write operation can be correctly completed.
However, with the increase of P/E (program/erase) cycle-index, some electrons are captured by tunnel oxidation layer.Such as figure
Shown in 1 (A), in normal state, electronics E is stored in floating gate electrode FG.By be applied to the voltage on control grid CG come
Control electron injection or the release of floating gate electrode FG.However, with the increase of P/E cycle-indexes, as shown in Fig. 1 (B), wiping
Except period, tunnel oxidation layer 1 can capture a part of electronics E, these trapped electrons E can increase the potential barrier and drop of follow-up tunnelling
Low tunneling efficiency causes the threshold voltage of unit to increase, and efficiency of erasing is finally caused to reduce even erasing failure.
Meanwhile in the environment that flash memory is applied to high speed P/E, the time of erasing and voltage are usually fixed.This is just generated
The design of one contradiction, in order to ensure that flash memory can work the P/E cycles of 100K (1K=1000) or more number, erasing voltage
It cannot be too low, but excessively high erasing voltage can cause tunnel oxidation layer to capture excessive electronics again so that efficiency of erasing and follow
Ring persistence reduces.
In order to cope with this case, the mode of Erase-retry (erasing reattempts) was employed in the past.Specifically,
After completing an erasing pulse, entire block can do readings to each storage unit, and the threshold voltage to confirm each unit is
It is no to be less than a certain reference voltage, if there is the threshold voltage of some unit is more than the reference voltage, it will it is dynamic to perform erasing again
Make, until the threshold voltage of all devices is less than reference voltage, erasing move just terminates.
Fig. 2 is to represent the curve graph that the erasing under different erasing voltages is degenerated, and abscissa represents erasing voltage (V), indulges and sit
The distribution situation of mark reflection erasing voltage.As shown in Figure 2, the original state for not carrying out erasing is compared, with 11V or 12V
Voltage wipe 100K time after, threshold voltage is whole to generate to the right larger offset, and continuing to wipe required voltage becomes
Higher.And after using Erase-retry modes, as shown in Retry_100K curves, the degree deviated to the right becomes smaller, and changes speech
It, can inhibit the threshold voltage caused by tunnel oxidation layer trapped electron to increase.
Invention content
The technical problems to be solved by the invention
As described above, it can inhibit the phenomenon that threshold voltage integrally deviates to the right, but in which using Erase-retry
Under, once the threshold voltage for having some unit is more than reference voltage, then erasing move can be performed again, until the threshold of all devices
Threshold voltage is less than reference voltage, therefore has multiple threshold voltage and confirm (post-erase verify) and erasing pulse
(erase pulse), erasing speed is restricted.
The present invention completes to solve the above-mentioned problems, it is intended that it is lasting with good P/E to provide a kind of energy
The flush memory device and its method for deleting that degree, service life are long and erasing speed is fast.
Technological means used by solution technical problem
The flush memory device of the present invention includes：
Multiple storage units, multiple storage unit are divided into multiple blocks；
Multiple counters, multiple counter correspond respectively to each block, for the erasing of the block time
Number is counted；And
Control unit, for when carrying out erasing operation to each block, from the corresponding counter of the block
The middle erasing times for reading the block, and further acquisition and the corresponding erasing operation parameter of the erasing times, to read
Erasing operation parameter to the block carry out erasing operation, the erasing operation parameter include erasing voltage.
In at least embodiment of the present invention, erasing times-erasing operation parameter mapping table, the erasing have been pre-established
Storage has the correspondence of erasing times and erasing operation parameter in number-erasing operation parameter mapping table, according to the erasing time
Number-erasing operation parameter mapping table obtains and the corresponding erasing operation parameter of erasing times.
In at least embodiment of the present invention, in the erasing times-erasing operation parameter mapping table, the erasing time
Number is more, and the erasing voltage is higher.
In at least embodiment of the present invention, the erasing operation parameter further includes the erasing time, and the erasing times-
Also storage has the correspondence in erasing times and erasing time in erasing operation parameter mapping table.
In at least embodiment of the present invention, according to the threshold voltage of each area's storage unit in the block, change
The corresponding erasing voltage of erasing times and/or erasing time in the erasing times-erasing voltage mapping table.
In at least embodiment of the present invention, each block shares the erasing times-erasing voltage mapping table；
Or each block has corresponding erasing times-erasing voltage mapping table；Or each area in the block one
Partial Block shares the erasing times-erasing voltage mapping table.
In at least embodiment of the present invention, the counter is respectively by the memory block in each 16 in the block of area
It forms.
In the method for deleting of flush memory device of the present invention, which includes：Multiple storage units, multiple storage unit
It is divided into multiple blocks；The method for deleting includes：
The count value of the corresponding counter of current block is read, obtains the erasing times of the current block；The counter
It is counted for the erasing times to the current block；
According to the count value of the counter, obtain and the corresponding erasing operation parameter of the erasing times, the erasing
Operating parameter includes erasing voltage；
Erasing operation is carried out to the current block with the erasing operation parameter.
In at least embodiment of the present invention, erasing times-erasing operation parameter mapping table, the erasing time are pre-established
Storage has the correspondence of erasing times and erasing operation parameter in number-erasing operation parameter mapping table；According to the erasing times-
Erasing operation parameter mapping table obtains and the corresponding erasing operation parameter of erasing times.
In at least embodiment of the present invention, in the erasing times-erasing operation parameter mapping table, the erasing time
Number is more, and the erasing voltage is higher.
In at least embodiment of the present invention, the erasing operation parameter further includes the erasing time, and the erasing times-
Also storage has the correspondence in erasing times and erasing time in erasing operation parameter mapping table.
It is further current according to this after erasing operation is carried out to current block in at least embodiment of the present invention
The threshold voltage of area's storage unit in the block, judges whether the erasing move of the block is completed.
In at least embodiment of the present invention, the threshold voltage of all storage units in current block, which is respectively less than, joins
When examining voltage, the erasing move of the current block is completed；Otherwise set-up procedure is performed to obtain new erasing operation parameter, with new
Erasing operation parameter to the current block carry out erasing operation.
In at least embodiment of the present invention, the set-up procedure includes：Erasing times-the erasing voltage is improved to reflect
The corresponding erasing voltage of erasing times and/or extend erasing times pair in the erasing times-erasing voltage mapping table in firing table
The erasing time answered.
In at least embodiment of the present invention, the set-up procedure includes：Storage unit in current block
Threshold voltage increases the count value of the counter.
In at least embodiment of the present invention, each block shares the erasing times-erasing voltage mapping table；
Or each block has corresponding erasing times-erasing voltage mapping table；Or each area in the block one
Partial Block shares the erasing times-erasing voltage mapping table.
Invention effect
Flush memory device and its method for deleting according to the present invention, by counter additionally being set to record this each block
The erasing times of block are respectively adopted accordingly using erasing times-erasing voltage mapping table to be directed to different erasing times
Erasing voltage.So as to be greatly decreased or even eliminate when threshold voltage confirms, the threshold voltage of some storage unit is more than
The situation of reference voltage so as to reduce erasing times again, and then reduces erasing pulse, can finally improve erasing speed, and carry
High circulation persistence.It is suitable in erasing times-erasing voltage mapping table parameter setting, it is convenient to omit threshold voltage is true
Recognize step.
Further, since the changeable parameters of erasing times-erasing voltage mapping table are more, therefore confirm step performing threshold voltage
In the case of rapid, the parameter of erasing times-erasing voltage mapping table can suitably be adjusted according to confirmation result to be further reduced
Erasing pulse can further improve erasing speed.
In addition, in the case of there are the storage unit that threshold voltage is more than reference voltage, the storage unit can also be made
The count value of area's erasing times in the block at place increases so that the count value after increase is in erasing times-erasing voltage mapping
Corresponding erasing voltage and/or erasing time bigger in table, thus can be to the block application higher in erasing move next time
Erasing voltage or the erasing time.
In addition, in the case where being provided with multiple erasing times-erasing voltage mapping table, can respectively be adjusted for different blocks
Whole erasing times-erasing voltage mapping table, thus, it is possible to the abnormal threshold voltage because of individual block is avoided to lead to whole wiping
Except voltage raises.
Description of the drawings
Fig. 1 (A) and Fig. 1 (B) is the schematic diagram for the process for representing tunnel oxidation layer trapped electron.
Fig. 2 is the curve graph for showing erasing degenerate case.
Fig. 3 is the schematic diagram of the circuit structure for the flush memory device for representing embodiment of the present invention.
Fig. 4 is the flow chart of an example of the method for deleting for the flush memory device for representing embodiment of the present invention.
Fig. 5 is the schematic diagram for the erasing times-erasing voltage mapping table for representing embodiment of the present invention.
Fig. 6 is the schematic diagram of the variation for the erasing times-erasing voltage mapping table for representing embodiment of the present invention.
Fig. 7 is the schematic diagram of the variation for the erasing times-erasing voltage mapping table for representing embodiment of the present invention.
Fig. 8 is the flow chart of the variation of the method for deleting for the flush memory device for representing embodiment of the present invention.
Specific embodiment
In the following, the flush memory device of the present invention and its embodiment and its variation of method for deleting are said based on attached drawing
It is bright, identical label is marked to same or equivalent component, position to illustrate in the various figures.
The flush memory device of the present invention can be nand flash memory, NOR flash memory, embedded flash memory etc..
Fig. 3 is the schematic diagram of the circuit structure for the flush memory device for representing embodiment of the present invention, and Fig. 4 is to represent of the invention real
Apply the flow chart of an example of the method for deleting of the flush memory device of mode.In the flush memory device of present embodiment, a block
(sector) for example by 64 (bit；Position) storage unit composition.One block is only shown, it is apparent that can also include more in figure
A block.
In present embodiment, in order to solve to have multiple threshold voltage confirmation and erasing pulse under Erase-retry modes
The problem of, a counter 4 is additionally set to each block, to record the erasing times of the block.The counter 4 for example may be used
To be made of the data storage area (word) of one 16 (bits).
In addition, the flush memory device of present embodiment further includes erasing times-erasing voltage mapping table 3 and control unit 5.
Storage in advance has expression erasing times and suitable erasing operation ginseng in erasing times-erasing voltage mapping table 3
The correspondence of number, such as erasing voltage.In general, for the more block of the number wiped, due to threshold voltage
Increase needs the erasing voltage of bigger, and for the relatively small number of block of erasing times, then it can use relatively small erasing
Voltage.It can be prevented in this way to a certain block using excessive erasing voltage so as to slow down the speed that its threshold voltage becomes faster.
Fig. 5 shows an example of erasing times-erasing voltage mapping table 3.With reference to the table it is found that for different erasings
Number is provided with corresponding erasing voltage.Such as the initial stage just begun to use in flush memory device, (erasing times were about 0~30K
It is secondary), erasing times are relatively low, and the electronics of tunnel oxidation layer capture at this time is relatively fewer, therefore threshold voltage is relatively low, using relatively low
Erasing can be completed in voltage, such as 16V.With the increase of P/E cycle-indexes, when erasing times reach 30K~70K, tunnel
The electronics E of oxide layer capture increases, as shown in Fig. 2, threshold voltage distribution curve can be deviated gradually to the right, required threshold voltage
Also it is corresponding to increase.Best efficiency of erasing can be obtained to carry out erasing using the erasing voltage higher than 16V, such as 18V at this time.Into
One step when erasing times reach 70K~100K, needs higher erasing voltage, such as 21V.
Control unit 5 reads in the counter 4 of the block each block when carrying out block erasing operation (S1) respectively
Count value (erasing times) (S2), then from above-mentioned erasing times-erasing voltage mapping table 3 read it is opposite with the count value
The erasing voltage (S3) answered.Later, erasing operation (S4) is carried out to the erasing block with the erasing voltage read.Herein, it controls
Portion 5 processed can also be realized by hardware realization by software modes such as computer programs.
In this way, corresponding erasing voltage is set separately for different erasing times.Using Erase-retry modes
In the case of, it can be greatly decreased and even eliminate when threshold voltage confirms (post-erase verify), some storage unit
Threshold voltage is more than the situation of reference voltage, so as to reduce erasing times again, and then reduces erasing pulse (erase pulse),
Erasing speed can be improved, and improves cycle persistence.Certainly, it is suitable in erasing times -3 parameter setting of erasing voltage mapping table
In the case of, it can no longer carry out threshold voltage confirmation.
After above-mentioned erasing operation is completed, that is, the erasing move (S5) to the block is completed, then make corresponding counter 4
In count value automatically plus 1,.Next block is skipped to later, is repeated the above steps.
As a result, in the case of the difference of erasing times of each block, it can also be mapped according to erasing times-erasing voltage
Table 3 selects corresponding erasing voltage respectively for each block.Therefore, most suitable erasing voltage can be selected each block
It is wiped, the threshold voltage so as to farthest inhibit the phenomenon that storage unit (transistor) becomes larger, and can improve wiping
Except speed.
It is set properly in erasing times-erasing voltage mapping table 3, it is convenient to omit threshold voltage verification step,
After erasing voltage is read from erasing times-erasing voltage mapping table 3 and carries out erasing move with the erasing voltage, the area
The count value of counter in the block adds 1 automatically.But the present invention is not limited thereto, can also be performed after erasing move is carried out
Threshold voltage verification step under Erase-retry modes, to be confirmed whether the area all storage units (transistor) in the block
Threshold voltage be respectively less than reference voltage.In practical applications, reference voltage can predefine.In the control gate of storage unit
Apply the reference voltage on the CG of pole, then read the data of storage unit, if it is " 0 ", judge the threshold value of the storage unit
Voltage is less than the reference voltage, if it is " 1 ", judges that the threshold voltage of the storage unit is more than the reference voltage.
Said effect causes the flush memory device of the present invention to be particularly suitable for requiring the MCU of high speed high reliability
(Microcontroller Unit：Micro-control unit) etc..
The foregoing describe an embodiment of the invention, but technical staff can be in the premise for not departing from present subject matter
Under the present invention made various changes, combine.
For example, being housed in above-mentioned erasing times-erasing voltage mapping table 3, erasing times are corresponding with erasing voltage to close
System, but can also further store erasing times and other erasing operation parameters, the relationship in such as erasing time.Fig. 6 shows to wipe
Except a variation of number-erasing voltage mapping table 3.In the erasing times-erasing voltage mapping table 3, in addition to erasing voltage
In addition, the corresponding erasing time is alsied specify.
Certainly, the parameter of erasing times-erasing voltage mapping table 3 can change.Such as by flush memory device be applied to pair
During the more demanding occasion of erasing speed, can life of product be set as 100K P/E cycle as shown in Figure 6, wiped
During except number for 0~30K, erasing voltage 16V, erasing time 1ms, when erasing times are 30K~70K, erasing voltage
For 18V, erasing time 1ms, when erasing times are 70~100K, erasing voltage 21V, erasing time 1ms.And it is inciting somebody to action
When flush memory device is applied to the occasion higher to reliability requirement, such as can be with as shown in fig. 7, life of product is set as 200K
Secondary P/E cycles, when erasing times are 0~30K, erasing voltage is relatively low 14V, erasing time 1ms, in erasing time
When number is 30~70K, erasing voltage is relatively low 15V, erasing time 1ms, when erasing times are 70~100K, is wiped
Except voltage is relatively low 16V, erasing time 1ms, when erasing times are 100~150K, erasing voltage is relatively
Low 17V, erasing time 1ms, when erasing times are 150~200K, erasing voltage is relatively low 18V, during erasing
Between be 1ms.In this way, the different application scenarios parameter different with setting is required can be directed to.
The example according to use environment and the parameter of requirement change erasing times-erasing voltage mapping table 3 illustrated above,
But the present invention is not limited thereto.For example, threshold voltage verification step (S6) can also be performed after erasing move is carried out, such as judge
To be more than reference voltage in the block and the threshold voltage of not all storage unit is respectively less than reference voltage, i.e., there are threshold voltages
Storage unit, then the parameter of erasing times-erasing voltage mapping table 3 can be changed (S7).Fig. 8 is shown in this case
Flow chart.As the parameter modification mode of erasing times-erasing voltage mapping table 3, for example, can properly increase erasing voltage,
Erasing time.Alternatively, it is also possible to not change the parameter of erasing times-erasing voltage mapping table 3, and the threshold voltage is made to be more than base
Count value in the counter 4 of block where the storage unit of quasi- threshold voltage additionally increases, and can be further such that after increase
Count value in erasing times-erasing voltage mapping table 3 corresponding erasing voltage and/or erasing time bigger.Later again
The count value (S2) in counter 4 is read, corresponding erasing voltage (S3) is read from erasing times-erasing voltage mapping table,
It is wiped (S4) with the new erasing voltage read, performs threshold voltage verification step (S6) and above-mentioned change step
(S7).Repeat the above steps S2, S3, S4, S6, S7, joins until the threshold voltage of all storage units in the block is respectively less than
Until examining voltage.Certainly, in the mode of the count value in not changing counter 4, without re-reading the count value.
It is dynamic by taking Fig. 6 as an example, such as carrying out erasing to the block for having carried out 20K P/E cycle with the erasing voltage of 16V
It, can be with if being found when performing threshold voltage verification step there are the storage unit that threshold voltage is more than reference voltage after work
It will be revised as example from 16V in erasing times-erasing voltage mapping table 3, with the corresponding erasing voltages of 0~30K of erasing times
17V will be revised as such as 1.5ms with 0~30K of erasing times corresponding erasing times from 1ms, can also be by the block
In the count value of counter 4 be changed to such as 30K from 20K, so as in erasing move next time to block application more
High erasing voltage or erasing time.As a result, according to the result adjust automatically erasing times of threshold voltage verification step-erasing electricity
The parameter of mapping table 3 or the count value of counter 4 are pressed, so as to obtain best effect, further improves erasing speed.
In addition, each block illustrated above shares the example of same erasing times-erasing voltage mapping table 3, but also may be used
Different blocks is directed to be arranged as required to multiple erasing times-erasing voltage mapping table 3.Each block can have each
Self-corresponding erasing times-erasing voltage mapping table or each area a part of block in the block share an erasing time
Number-erasing voltage mapping table.In this way, especially according to threshold voltage verification step to erasing times-erasing voltage mapping table 3
In the case of being adjusted, erasing times-erasing voltage mapping table 3 can be adjusted respectively for different blocks, thus, it is possible to avoid
Because the abnormal threshold voltage of individual block causes whole erasing voltage to raise.
Certainly, present invention is also not necessarily limited to use erasing times-erasing voltage mapping table to determine erasing operation parameter.Such as
Corresponding erasing operation parameter can also be obtained according to erasing times, and can further basis using calculation formula, model etc.
Threshold voltage confirms result to change parameter of these calculation formula, model etc..It in brief, can be according to certain correspondence rule
Obtain erasing operation parameter.
In addition, the example of block erasing illustrated above, but for being wiped as unit of bank in the case of it is also same
Sample can be applicable in the present invention.
The preferred embodiment of the present invention has been described above in detail.It should be appreciated that the present invention is not departing from its broad sense essence
Various embodiments and deformation may be used in the case of god and range.Those of ordinary skill in the art are without creative work
It according to the present invention can conceive and make many modifications and variations.Therefore, all those skilled in the art are under this invention's idea
On the basis of existing technology by the available technical solution of logical analysis, reasoning, or a limited experiment, should all belong to
Determined by claims of the present invention in protection domain.
In some embodiments, the numerical parameter used in description and claims is approximation, the approximation root
It can change according to feature needed for separate embodiment.In some embodiments, numerical parameter is considered as defined significant digit
And the method retained using general digit.Although it is used to confirm the Numerical Range and ginseng of its range range in some embodiments of the application
Number is approximation, and in a particular embodiment, being set in for such numerical value is reported as precisely as possible in feasible region.
Label declaration
1 tunnel oxidation layer
FG floating gate electrodes
CG controls grid
E electronics
3 erasing times-erasing voltage mapping table
4 counters
5 control units
Claims (16)
1. a kind of flush memory device, which is characterized in that including：
Multiple storage units, multiple storage unit are divided into multiple blocks；
Multiple counters, multiple counter correspond respectively to each block, for the erasing times to the block into
Row counts；And
Control unit, for when carrying out erasing operation to each block, being read from the corresponding counter of the block
The erasing times of the block, and further acquisition and the corresponding erasing operation parameter of the erasing times are taken, with the wiping read
Division operation parameter carries out the block erasing operation, and the erasing operation parameter includes erasing voltage.
2. flush memory device as described in claim 1, which is characterized in that
Erasing times-erasing operation parameter mapping table has been pre-established, has been stored in the erasing times-erasing operation parameter mapping table
There is the correspondence of erasing times and erasing operation parameter,
According to the erasing times-erasing operation parameter mapping table, obtain and the corresponding erasing operation parameter of erasing times.
3. flush memory device as claimed in claim 2, which is characterized in that
In the erasing times-erasing operation parameter mapping table, the erasing times are more, and the erasing voltage is higher.
4. flush memory device as claimed in claim 2, which is characterized in that
The erasing operation parameter further includes the erasing time, and also being stored in the erasing times-erasing operation parameter mapping table has
Erasing times and the correspondence in erasing time.
5. flush memory device as claimed in claim 4, which is characterized in that
According to the threshold voltage of each area's storage unit in the block, change in the erasing times-erasing voltage mapping table
The corresponding erasing voltage of erasing times and/or erasing time.
6. the flush memory device as described in any one of claim 1 to 5, which is characterized in that
Each block shares the erasing times-erasing voltage mapping table；Or each block has respective correspond to
Erasing times-erasing voltage mapping table；Or each area a part of block in the block shares the erasing times-erasing
Voltage mapping table.
7. flush memory device as described in claim 1, which is characterized in that
The counter is made of respectively the memory block in each 16 in the block of area.
8. a kind of method for deleting of flush memory device, the flush memory device include：Multiple storage units, multiple storage unit are divided
Into multiple blocks；The method for deleting includes：
The count value of the corresponding counter of current block is read, obtains the erasing times of the current block；The counter is used for
The erasing times of the current block are counted；
According to the count value of the counter, obtain and the corresponding erasing operation parameter of the erasing times, the erasing operation
Parameter includes erasing voltage；
Erasing operation is carried out to the current block with the erasing operation parameter.
9. the method for deleting of flush memory device as claimed in claim 8, which is characterized in that
Erasing times-erasing operation parameter mapping table is pre-established, being stored in the erasing times-erasing operation parameter mapping table has
The correspondence of erasing times and erasing operation parameter；According to the erasing times-erasing operation parameter mapping table, obtain and wipe
The corresponding erasing operation parameter of number.
10. the method for deleting of flush memory device as claimed in claim 9, which is characterized in that
In the erasing times-erasing operation parameter mapping table, the erasing times are more, and the erasing voltage is higher.
11. the method for deleting of flush memory device as claimed in claim 9, which is characterized in that
The erasing operation parameter further includes the erasing time, and also being stored in the erasing times-erasing operation parameter mapping table has
Erasing times and the correspondence in erasing time.
12. the method for deleting of flush memory device as claimed in claim 11, which is characterized in that
After erasing operation is carried out to current block, further according to the threshold voltage for deserving proparea storage unit in the block, sentence
Whether the erasing move of the disconnected block is completed.
13. the method for deleting of flush memory device as claimed in claim 12, which is characterized in that
When the threshold voltage of all storage units in current block is respectively less than reference voltage, the erasing of the current block is completed
Action；Otherwise perform set-up procedure to obtain new erasing operation parameter, with new erasing operation parameter to the current block into
Row erasing operation.
14. the method for deleting of flush memory device as claimed in claim 13, which is characterized in that
The set-up procedure includes：The corresponding erasing voltage of erasing times in the erasing times-erasing voltage mapping table is improved,
And/or extend the erasing times corresponding erasing time in the erasing times-erasing voltage mapping table.
15. the method for deleting of flush memory device as claimed in claim 13, which is characterized in that
The set-up procedure includes：The threshold voltage of storage unit in current block increases the counting of the counter
Value.
16. the method for deleting of the flush memory device as described in any one of claim 8 to 15, which is characterized in that
Each block shares the erasing times-erasing voltage mapping table；Or each block has respective correspond to
Erasing times-erasing voltage mapping table；Or each area a part of block in the block shares the erasing times-erasing
Voltage mapping table.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810168902.4A CN108154899A (en) | 2018-02-28 | 2018-02-28 | Flush memory device and its method for deleting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN109256166A (en) * | 2018-08-22 | 2019-01-22 | 长江存储科技有限责任公司 | The method for deleting and flash memories of flash memories |
| CN111949201A (en) * | 2019-05-17 | 2020-11-17 | 北京兆易创新科技股份有限公司 | Storage device and control method and control device thereof |
| CN112241242A (en) * | 2019-07-17 | 2021-01-19 | 三星电子株式会社 | Memory controller and storage device including the same |
| CN113448496A (en) * | 2020-03-25 | 2021-09-28 | 旺宏电子股份有限公司 | Erasing method of multi-layer three-dimensional memory |
| CN113488096A (en) * | 2021-06-30 | 2021-10-08 | 恒烁半导体(合肥)股份有限公司 | Efficient erasing method and device applied to NOR flash memory and application thereof |
| CN115312103A (en) * | 2022-09-30 | 2022-11-08 | 芯天下技术股份有限公司 | Erasing voltage configuration method, device and equipment of flash memory chip and storage medium |
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| CN113488096B (en) * | 2021-06-30 | 2024-03-15 | 恒烁半导体(合肥)股份有限公司 | Efficient erasing method and device applied to NOR flash memory and application thereof |
| CN115312103A (en) * | 2022-09-30 | 2022-11-08 | 芯天下技术股份有限公司 | Erasing voltage configuration method, device and equipment of flash memory chip and storage medium |
| CN115312103B (en) * | 2022-09-30 | 2022-12-13 | 芯天下技术股份有限公司 | Erasing voltage configuration method, device and equipment of flash memory chip and storage medium |
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