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CN108074875A - Semiconductor packages and the method for manufacturing it - Google Patents

Semiconductor packages and the method for manufacturing it Download PDF

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Publication number
CN108074875A
CN108074875A CN201710334218.4A CN201710334218A CN108074875A CN 108074875 A CN108074875 A CN 108074875A CN 201710334218 A CN201710334218 A CN 201710334218A CN 108074875 A CN108074875 A CN 108074875A
Authority
CN
China
Prior art keywords
carrier
hole
sealant
chamber
semiconductor packages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710334218.4A
Other languages
Chinese (zh)
Inventor
房昱安
陈盈仲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN108074875A publication Critical patent/CN108074875A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention provides a kind of semiconductor packages, including a carrier, a lid, an electronic unit and a sealant.The carrier has a first surface and a second surface opposite with the first surface, and limits the hole that the second surface is extended to from the first surface.The lid is attached to the first surface of the carrier.The lid and the carrier limit a chamber.The electronic unit is attached to the first surface of the carrier and sets in the chamber.The sealant is attached to the second surface of the carrier and covers the hole.

Description

Semiconductor packages and the method for manufacturing it
Technical field
The present invention relates to a kind of semiconductor packages.More particularly, the present invention relates to the semiconductors for including a lid The method that device encapsulates and manufactures it.
Background technology
In semiconductor packages, using the bare die and other electronic devices for covering to protect on substrate from moisture, ash The influence of dirt, particle etc..Lid is attached to by glue on substrate to form semiconductor packages.However, due to thermal cycle Caused popcorn effect (pop-corn effect) with heating semiconductor (for example, can encapsulate to cure lid and substrate Between glue), lid may separate (detached) with substrate.
The content of the invention
In certain embodiments on the one hand, a kind of semiconductor packages, including a carrier, a lid, a ministry of electronics industry Part and a sealant.The carrier has a first surface and a second surface opposite with the first surface, and limit from this One surface extends to a hole of the second surface.The lid is attached to the first surface of the carrier.The lid and the carrier limit one Chamber.The electronic unit is attached to the first surface of the carrier and sets in the chamber.The sealant is attached to the carrier The second surface and cover the hole.
In certain embodiments on the one hand, a kind of method for manufacturing semiconductor device encapsulation, including：(a) provide One carrier limits a through hole；(b) electronic unit is attached to the carrier；(c) Jiang Yigai is attached to the carrier to cover this Electronic unit and with the carrier limit a chamber；And (d) applies a sealant material to cover the through hole on this carrier.
In certain embodiments on the one hand, a kind of method for manufacturing semiconductor device encapsulation, including：(a) provide One first vector limits a through hole；(b) electronic unit is attached to first first vector；(c) Jiang Yigai is attached to this First vector with cover the electronic unit and limit with the first vector a chamber；(d) apply in the first vector One sealant material is to cover the through hole；The chamber in generate than an environmental air pressure more smaller air pressure (e).
Description of the drawings
Fig. 1 is the sectional view of semiconductor packages according to some embodiments of the present invention.
Fig. 2 is the sectional view of another semiconductor packages according to some embodiments of the present invention.
Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D, Fig. 3 E and Fig. 3 F show manufacture half according to some embodiments of the present invention The method of conductor device encapsulation.
Through schema and it is described in detail using common reference manuals to indicate same or like element.The embodiment of the present invention It described in detail below will be become readily apparent from from what is carried out with reference to attached drawing.
Specific embodiment
Describe to improve the technology of the attachment of the lid of semiconductor packages in the present invention.Moreover, these technologies can To avoid the popcorn effect caused by thermal cycle, lid is made to be separated with substrate.
Compared with a certain plane of the group of the group or component or component of a certain component or component, designated space describes, Such as " on ", " under ", " on ", "left", "right", " under ", " top ", " bottom ", " vertical ", " level ", " side ", " higher " " lower part ", " top ", " top ", " lower section " etc., for orienting as being associated the component shown in figure.It is to be understood that herein Used in spatial description be only in order at the purpose of explanation, and the actual implementation of structure described herein can be with any fixed To or mode be spatially arranged, restrictive condition is therefore not arranged deviation for the advantages of the embodiment of the present invention.
Fig. 1 is the sectional view of semiconductor packages 1 according to some embodiments of the present invention.Semiconductor packages 1 Including carrier 10, lid 40, closing line 22, electronic unit 20 and 21, pad 50, sealant 70, solder ball pad 52, surface mounting technology (SMT) pad 54 and adhesive layer 30.Semiconductor packages 1 shown in FIG. 1 are formed in before it is split on panel (panel) One illustrates unit, and panel includes multiple such units.
Carrier 10 has upper surface 101 and the lower surface 102 opposite with upper surface 101.In some embodiments, carrier 10 May include silicon, ceramic material, organic material (such as bismaleimide-triazine (bismaleimide-triazine (BT) or Glass-reinforced epoxy material (such as FR-4)) or another suitable material.Through hole 60 is formed simultaneously from the upper surface of carrier 10 101 Extend to lower surface 102.In some embodiments, metal layer can be arranged on the side wall of through hole 60.In some embodiments, The side wall of through hole 60 can be omitted the metal layer being disposed thereon.It although is not shown in Fig. 1, it is contemplated that carrier 10 can include electricity Road, such as include the redistribution structure of conductive trace, pad, through hole etc..
Lid 40 is via adhesive layer 30 or via the upper surface 101 for being attached to carrier 10.Lid 40 and carrier 10 limit together Chamber A is determined, lid 40 and carrier 10 can be sealed by adhesive layer 30 or via welded seals, and it can be gas-tight seal to seal (hermetic seal).It is gas-tight seal can be engaged via metal, glass frit (glass frit), anodic bonding, eutectic key Close (eutectic bonding) or melting engagement (fusion bonding) formation.In the manufacture of semiconductor packages 1 During journey, adhesive layer 30 cures via heating operation from such as gel (gel), glue (glue) or other jointing materials.
Electronic unit 20 and 21 (for example, semiconductor bare chip, passive component etc.) is arranged on upper surface 101.Electronic unit 20 and 21 are arranged in chamber A.20 and 21 Electricity of electronic unit is connected to the circuit of carrier 10 by closing line 22.In some embodiments In, closing line 22 can include golden (Au), copper (Cu) or other suitable conductive material.
Pad 50 is arranged on the lower surface 102 of carrier 10.Solder ball pad 52 is formed on lower surface 102, and pad 54 is formed in On lower surface 102.Pad 50 surrounds through hole 60.Pad 50 has or limits the through hole 62 connected with through hole 60.Pad 50 has or limits The through hole 62 being aligned with through hole 60.Pad 50 has cast or annular (ring or an annular shape).In some implementations In example, air ring 50 may include Cu-Pd (palladium)-Au, Cu, nickel (Ni), Pd, Au or its combination or other suitable materials.
Sealant 70 can include but is not limited to such as solder, can include tin (Sn), Xi-silver (SnAg), Xi-silver- Copper (SnAgCu) or other suitable materials.Sealant 70 is arranged on pad 50.Joint element 72 can include but is not limited to example Such as solder, Sn or SnAg, SnAgCu or other suitable materials can be included.In some embodiments, 72 (example of joint element Such as, soldered ball) it can be arranged on solder ball pad 52.In some embodiments, sealant 70 and joint element 72 can include identical Material.
Pad 50 is arranged between sealant 70 and the lower surface 102 of carrier 10.The transverse direction of the sealant 70 adjacent with pad 50 Size (for example, width) be more than through hole 62 lateral dimension (for example, width), and more than through hole 60 lateral dimension (for example, Width).In some embodiments, the entirety of the substantially opening of covering through hole 62 of sealant 70, and substantially covering through hole 60 Opening entirety.Sealant 70 seals through hole 60 and 62.It is logical that sealant 70 airtightly seals (hermetically seals) Hole 60 and 62.Sealant 70 electronic unit 20 and 21 (it is located in chamber A) can be protected without damage or pollution (for example, Grain, moisture etc.).
Sealant 70 includes extending to the protrusion (protrusion) 71 in through hole 60.Protrusion 71 has bending or arc End.Protrusion 71 airtightly seals through hole 60.Pressure in chamber A may be relatively lower than environmental air pressure, and in chamber A Pressure can be to avoid the popcorn effect during various thermal cycles in the fabrication process.
In some embodiments, electronic unit 28 (for example, passive component) be arranged on the lower surface 102 of carrier 10 and It is electrically connected to pad 54.The thickness of passive component 28 and the thickness of sealant 70 can be less than the thickness of joint element 72 so that when When semiconductor packages 1 are joined to motherboard (mother board) by joint element 72, passive component 28 and sealing Agent 70 will be accommodated in the space that is limited by joint element 72, carrier 10 and motherboard (not shown).In some embodiments, half Electronic unit 20 and 21 in conductor device encapsulation 1 can isolate with air/external environment.In transmit process (delivery Process in), using the structure of semiconductor packages 1 electronic unit 20 and 21 can be protected from that may cause partly to lead The influence of moisture, dust, the particle of sensitivity decrease of body device encapsulation 1 etc..
Fig. 2 is the sectional view of another semiconductor packages 2 according to some embodiments of the present invention.Except carrier 10' Outside sunk part (recessed portion), the structures of semiconductor packages 2 in some aspects with semiconductor device The structure of part encapsulation 1 is similar.Semiconductor packages 2 shown in Fig. 2 are the illustration units being formed in before it is split on panel, And panel includes multiple such units.
Carrier 10' may include ceramic substrate (ceramic substrate).Cover the sunk part of 40' covering carriers 10'. Lid 40' can include silicon, glass or other suitable materials.Covering 40' and carrier 10' can be by adhesive layer 30 or by welding It seals, and it can be gas-tight seal to seal.It is gas-tight seal can be engaged by metal, glass frit, anode combine, eutectic key It closes or melting engagement is formed.
Through hole 60 forms from the upper surface 101' of carrier 10' and extends to lower surface 102'.Metal layer 52 includes three portions Point, wherein first portion 521 is arranged on the upper surface 101' of carrier 10', second portion 522 is arranged on the side wall of carrier 10' Upper, Part III 523 is arranged on the lower surface 102' of carrier 10'.Sealant 70 covers first portion 521,522 and of second portion Part III 523.
When semiconductor packages 2 are bonded to motherboard by joint element 72, passive component 28 and sealant 70 can be contained in the space limited by joint element 72, carrier 10' and motherboard (not shown).In some embodiments, Electronic unit 20 and 21 in semiconductor packages 2 can isolate with air/external environment.In transmit process, it can make Protect electronic unit 20 and 21 from the sensitive of semiconductor packages 2 may be caused with the structure of semiconductor packages 2 Spend the influence of moisture, dust, the particle reduced etc..
The method that Fig. 3 A-3F show manufacture semiconductor device encapsulation 1 according to some embodiments of the present invention.With reference to Fig. 3 A provide carrier 10.Carrier 10 has surface 101 and the surface 102 opposite with surface 101.In some embodiments, carry Body 10 can include silicon, ceramic material, organic material (such as BT or FR-4) or other suitable material.Solder ball pad 52 is formed in On surface 102.Pad 53 is formed on surface 102.
Through hole 60 forms from the surface of carrier 10 102 and extends to surface 101.Through hole 60 is by mechanical drilling techniques (machine drilling techniques) or laser drilling processes are formed.By electroplating technology on the surface of carrier 10 102 Upper formation air ring (annular pad) 50.Air ring 50 has surface 501 and around the opening of through hole 60.Air ring 50 Have or limit the through hole 62 by mechanical drilling techniques or laser drilling processes formation.Through hole 62 is connected with through hole 60.One In a little embodiments, air ring 50 can include Cu-Pd-Au, Cu, Ni, Pd, Au or combination thereof or other suitable materials. In some embodiments, solder mask layer (solder mask layer) (not shown) can cover air ring 50.In some realities It applies in example, air ring 50 can form and extend to cover the part on the surface 101 of carrier 10, the side wall and carrier of through hole 60 The part on 10 surface 102.
With reference to figure 3B, electronic unit 20 and 21 is attached to the surface 101 of carrier 10.Closing line 22 is electrically connected to electronic unit 20 and 21.The one end of each closing line 22 is attached to the surface 101 of carrier 10, and the other end of closing line 22 is attached to phase The electronic unit 20 or 21 answered.
With reference to figure 3C, lid 40 is attached to the surface 101 of carrier 10 via adhesive layer 30, with overlay electronic component 20 and 21. Lid 40 and 10 limit chamber A of carrier.During a thermal cycle of the manufacturing process of semiconductor packages 1, adhesive layer 30 passes through Cured by heating process from such as gel, glue or other jointing materials.In some embodiments, the jointing material of adhesive layer 30 It can be engaged by metal, glass frit, anode combine, eutectic bonding or melting engagement substitution.
With reference to figure 3D, sealing material 70'(is for example, solder) it is applied on the surface 501 of air ring 50 and covers logical Hole 60 and 62.In some embodiments, sealing material 70' can be the solder for including Sn or other suitable materials.Soldering paste 74 can To be applied to by screen printing technique (screen printing techniques) on pad 53.Sealing material 70' and soldering paste 74 can be applied in the identical stage (stage), and air ring 50 and pad 53 can be applied to by screen printing technique On.
With reference to figure 3E, passive component 28 is arranged on by surface mounting technology (SMT) on soldering paste 74.It is set in passive component 28 After putting on pad 53, heating operation is carried out to the structure shown in Fig. 3 E.Apply fluxing agent (flux) to sealing material 70' to help Sealing material 70' is helped to melt.Sealing material 70' softens during heating operation.During heating operation, the air in chamber A It will expansion；Therefore, the pressure in chamber A is more than external air pressure.Air in the chamber A heated can expand to pass through Sealing material 70' is to form through hole 64.Through hole 60,62 and 64 allows the air of demi-inflation to leave chamber A.Due to sealing material Material 70' be in molten condition (molten state) and is in liquid, it is possible to by through hole 60,62 and 64 by chamber A In drive air or discharge (expelled or vented out) chamber A.
It, can be to avoid popcorn effect by the air that through hole 60,62 and 64 discharges from chamber A during heating operation. Due to the expanded air during thermal cycle by the release of through hole 60,62 and 64 to avoid popcorn effect, lid 40 and carrier Engagement between 10 may not be damaged.Due to the structure feature of carrier 10, pad 50 and sealing material 70', lid 40 Engagement between carrier 10 may not damage.
With reference to shown in figure 3F, when the little or no air of the air in chamber A comes out via sealing material 70', sealing The shape of material 70' can change into the shape of sealing 70 ", such as circular or hemispherical (round or hemispherical shape).When heating temperature reaches about 260 DEG C to 280 DEG C, sealing material 70' can change into the shape of sealing 70 ", such as Circular or hemispherical.Joint element 72 is formed on solder ball pad 52.The overall thickness of passive component 28, soldering paste 74 and pad 53 can be small In the thickness of joint element 72.Since metal soaks (metal wetting), soldering paste 74 and pad 53 with reference to and form SMT pads 54.
Sealant 70 " covers or sealing through hole 60 and 62.When the temperature drops, air in chamber A during cooling down operation Pressure is less than external air pressure (for example, smaller pressure is generated in chamber A).Upon a drop in temperature, sealant 70 " becomes Cure (solid), and due to the relatively small air pressure in chamber A, a part of of sealant 70 " can be inhaled into Semiconductor packages 1 in through hole 60 and 62 to form protrusion 71 to form as shown in Figure 1.Due to sealed solid agent 70 " Therefore covering, extraneous air cannot enter chamber A.
After the curing of sealant 70 ", semiconductor packages 1 seal air/external environment.Semiconductor devices seals Motherboard can be attached to by the reflux (reflowing) of welding assembly 72 by filling 1.Due in refluxing stage not to sealant 70 " apply fluxing agent, and sealant 70 " has oxide in its surface, therefore the fusing point of sealant 70 " is more than joint part The fusing point of part 72.Therefore, during refluxing stage, sealant 70 " is non-fusible so that semiconductor packages 1 keep to air/ The sealing of external environment.
It is contemplated that semiconductor packages 1 can be attached to another carrier (such as the system board being not shown in figure), And semiconductor packages 1 can carry out another heating operation.Semiconductor packages 1 are being attached to the behaviour of system board In work, the air (it is with relatively low pressure) in chamber A is heated.Semiconductor packages 1 are being attached to system In the operation of plate, the expansion of the air (it is with relatively low pressure) in chamber A is compensated.By opposite in chamber A Relatively low pressure avoids popcorn effect.
In addition, semiconductor packages 1 keep the sealing to air/external environment during the cutting operation of panel.This Outside, in subsequent packing stage and subsequent transmit process, semiconductor packages 1 are kept to the close of air/external environment It seals (for example, gas-tight seal state), and will not be damaged due to subsequent transmit process.
As shown in Fig. 2, similar method can be used for manufacture semiconductor packages 2, wherein being arranged on the upper of carrier 10' The first portion 521 of metal layer 52 on the 101' of surface and the 3rd of the metal layer 52 on the lower surface 102' of carrier 10' the Apply sealing material in 523 the two of part.
As it is used herein, singular references " one ", "one" and "the" can include plural referents, unless context It is otherwise explicitly indicated.
As used herein, word " approx ", " generally ", " substantive " and " about " is describing and illustrate small change Change.When being used in combination with event or situation, the word can refer to the situation that event or situation clearly occur and event or situation Pole is similar to situation about occurring.For example, when with reference to numerical value in use, the word can refer to less than or equal to that numerical value ± 10% excursion, e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, be less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1% or less than or equal to ± 0.05%.For example, if difference between two values is less than or equal to ± the 10% of the average value of described value (for example, small In or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%th, less than or equal to ± 0.5%, less than or equal to ± 0.1% or less than or equal to ± 0.05%), then it is believed that described two A numerical value is " generally " identical.
In the description of some embodiments, another component " on " or " top " provide component may include that previous component is straight The situation and wherein one or more intermediate members for being connected in latter part (for example, entity or contact directly) are located at forepart Example between component and back component.
In addition, press range format presentation amount, ratio and other numerical value herein sometimes.It is to be understood that such range format It is to be convenient and uses for purpose of brevity, and should be interpreted flexibly to not only include the numerical value for being expressly specified as range limit, and Also comprising all individual numbers or the subrange being covered by the range of that, just as clearly specified each numerical value and subrange one As.
Although having referred to the particular embodiment of the present invention to describe and illustrate the present invention, these descriptions and explanation are not intended to limit The present invention.Those skilled in the art will appreciate that the true of the present invention as defined by the appended claims is not being departed from In the case of spirit and scope, it can be variously modified and available equivalents substitute.Illustrate to be not drawn necessarily to scale.Attribution Difference may be present between art recurring and actual device in technique and tolerance limit, the present invention.Not certain illustrated may be present Other embodiments of the invention.This specification and schema should be considered as illustrative and not restrictive.It can modify, so that special Shape, material, material composition, method or the technique of pledging love are adapted to the target of the present invention, spirit and scope.All modifications are anticipated It is intended in the scope of appended claims herein.Although it is described herein referring to the specific operation being performed in a specific order Disclosed in method, it should be appreciated that in the case where not departing from teachings of the present invention, can be combined, divide again or re-sequence this It is a little to operate to form equivalent method.Therefore, unless specific instruction herein, the order otherwise operated and grouping are not to the present invention Limitation.

Claims (20)

1. a kind of semiconductor packages, including：
One carrier has a first surface and a second surface opposite with the first surface, and limits from the first surface Extend to a hole of the second surface；
One lid, is attached to the first surface of the carrier, and the lid and the carrier limit a chamber；
One electronic unit is attached to the first surface of the carrier and sets in the chamber；With
One sealant is attached to the second surface of the carrier and covers the hole.
2. semiconductor packages according to claim 1, the wherein sealant include the protrusion in the hole.
3. semiconductor packages according to claim 2, the wherein protrusion include a bending or curved end.
4. there is a width to be more than the one wide of the hole for semiconductor packages according to claim 1, the wherein sealant Degree.
5. semiconductor packages according to claim 1 further comprise on the second surface of the carrier One pad in the hole, the wherein pad are arranged between the sealant and the second surface of the carrier.
6. semiconductor packages according to claim 5, the wherein pad limit a hole, and the sealant has a width More than a width in the hole limited by the pad.
7. a kind of method for manufacturing semiconductor device encapsulation, including：
(a) carrier is provided, limits a through hole；
(b) electronic unit is attached to the carrier；
(c) Jiang Yigai is attached to the carrier to cover the electronic unit and limit a chamber with the carrier；With
(d) sealant material is applied on this carrier to cover the through hole.
8. according to the method described in claim 7, it further comprises that (e) performs a heating operation.
9. according to the method described in claim 8, wherein (e) includes applying a fluxing agent (flux) to the sealant material.
10. according to the method described in claim 8, wherein the sealant material softens during the heating operation, and the chamber In a hole of the air in the sealant material of the softening and discharged from the chamber.
11. according to the method described in claim 8, wherein forming a sealant by the sealant material seals the through hole.
12. according to the method described in claim 8, it further comprises that (f) performs a cooling down operation (cooling operation)。
13. according to the method for claim 12, the wherein sealant material is pulled into the through hole in (f) to seal The through hole.
14. according to the method described in claim 7, it further comprises before (d), formed on this carrier around the through hole A pad.
15. according to the method for claim 14, wherein the sealant material is applied on the pad in (d).
16. a kind of method for manufacturing an electronic equipment, including：
(a) first vector is provided, limits a through hole；
(b) electronic unit is attached to first first vector；
(c) Jiang Yigai is attached to the first vector to cover the electronic unit and limit the chamber with the first vector；
(d) sealant material is applied in the first vector to cover the through hole；With
(e) air pressure more smaller than environmental air pressure is generated in the chamber.
17. according to the method for claim 16, wherein (e) includes performing one first heating operation.
18. according to the method for claim 17, wherein wherein (e) further comprises performing after first heating operation One cooling down operation.
19. according to the method for claim 17, wherein performing first heating operation includes applying to the sealant material One fluxing agent.
20. according to the method for claim 17, further comprise (f) by perform one second heating operation by this first Carrier is joined to a Second support.
CN201710334218.4A 2016-11-09 2017-05-12 Semiconductor packages and the method for manufacturing it Pending CN108074875A (en)

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US20200194328A1 (en) * 2018-12-12 2020-06-18 Advanced Semiconductor Engineering, Inc. Device packages and method of manufacturing the same
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US5893726A (en) * 1997-12-15 1999-04-13 Micron Technology, Inc. Semiconductor package with pre-fabricated cover and method of fabrication
US20020097562A1 (en) * 2000-12-18 2002-07-25 Tdk Corporation Electronic device and manufacturing same
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