CN107966838B - Liquid crystal display panel and display device - Google Patents
Liquid crystal display panel and display device Download PDFInfo
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- CN107966838B CN107966838B CN201711368609.4A CN201711368609A CN107966838B CN 107966838 B CN107966838 B CN 107966838B CN 201711368609 A CN201711368609 A CN 201711368609A CN 107966838 B CN107966838 B CN 107966838B
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 38
- 238000012544 monitoring process Methods 0.000 claims abstract description 12
- 239000011159 matrix material Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention provides a liquid crystal panel, the actual pixel units of the display area are arranged and distributed in a determinant matrix, and virtual pixel units and corresponding virtual data lines thereof are distributed on at least one side of two sides of a horizontal line; and setting main pixel and sub-pixel electrodes in virtual pixel units corresponding to the row to be tested of all the actual pixel units to be simultaneously connected with the data line of a certain column of actual pixel units and also simultaneously connected with a virtual data line, so that after the row to be tested is lightened, the optimal common electrode voltage and the optimal data signal input time and level value of the row are determined by monitoring the virtual data line voltage connected with the virtual pixel units of the lightened row. By implementing the invention, on the premise of not changing the boundary of the liquid crystal panel, the pixel units capable of monitoring the actual voltage are added to determine the optimal common electrode voltage and the optimal data signal input time and level value of any row of pixel units in the display area, thereby reducing the risks of the problems of picture flicker, image retention, uneven display and the like.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a liquid crystal panel and a display device.
Background
The pixels of the liquid crystal panel are usually designed based on a standard three-transistor (3T) active pixel structure, which can improve the problem of color shift at large viewing angles, but because the charge in the sub-Thin Film Transistor (TFT) is discharged to a common electrode array plate, the common electrode voltage (Vcom) on the main pixel (main pixel) and the sub-pixel (sub-pixel) in the same pixel unit is different, which causes the problems of image flicker, image retention, display non-uniformity and the like of the liquid crystal panel.
In order to overcome the problems caused by the liquid crystal panel, the following steps are adopted: (1) early-stage simulation: setting a rough gamma voltage value through early-stage electrical simulation, so that the common electrode voltage (Vcom) on a main pixel electrode and a sub-pixel electrode in the same pixel unit is similar; (2) actually adjusting the data signal input time and level values in the pixel unit: by measuring the flicker degree of the picture, the flicker degree of the picture under different gray scales is as small as possible under the condition of finally determined data signal input time and level value.
However, in practical application of the liquid crystal panel, since the actual positions of the main pixel electrode and the sub-pixel electrode in the same pixel unit cannot be monitored, there is no way to determine the optimal common electrode voltage and the optimal data signal input time and level value of any row of pixel units.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a liquid crystal panel and a display device, which can add pixel units capable of monitoring an actual voltage on the premise of not changing the boundary of the liquid crystal panel as much as possible, and determine the optimal common electrode voltage and the optimal data signal input time and level value of any row of pixel units in a display area by detecting the actual voltage of the added pixel units, thereby reducing the risk of the problems of flicker, image retention, display unevenness, and the like.
In order to solve the above technical problem, an embodiment of the present invention provides a liquid crystal panel, including a display area for displaying an image and a virtual pixel area disposed at a periphery of the display area, where actual pixel units of the display area are arranged and distributed in a matrix of rows and columns, and at least one virtual pixel unit belonging to the virtual pixel area is correspondingly distributed on at least one of two sides of each row of actual pixel units disposed along a horizontal row direction, and a corresponding virtual data line is distributed on one side of each virtual pixel unit away from the display area;
each virtual pixel unit corresponding to all rows to be tested of the actual pixel units in the display area is set to be a specific structure virtual pixel unit, and a main pixel electrode and a sub-pixel electrode in each specific structure virtual pixel unit are simultaneously connected to a data line of a certain column of actual pixel units in the display area and are also simultaneously connected to a corresponding virtual data line, so that after a certain row to be tested of the actual pixel units in the display area is lightened, the optimal common electrode voltage and the optimal data signal input time and level value of the actual pixel units of the lightened row can be determined by monitoring the voltage of virtual data lines connected to the horizontally distributed specific structure virtual pixel units corresponding to the actual pixel units of the lightened row.
The display area is provided with a plurality of virtual pixel units of a specific structure, each virtual pixel unit of the specific structure is correspondingly arranged on a row to be tested of each actual pixel unit, and the virtual pixel units of the specific structure are correspondingly arranged on the row to be tested of each actual pixel unit in the display area and are simultaneously positioned on one side of the display area and are regularly connected to a corresponding virtual data line in an equal interval distribution manner.
The display area comprises a display area, a display area and a control area, wherein one specific structure virtual pixel unit is arranged corresponding to each actual pixel unit row to be tested in the display area, and all specific structure virtual pixel units are arranged corresponding to all actual pixel unit rows to be tested in the display area and are distributed on two sides of the display area in a staggered mode; the virtual pixel units with the specific structures on one side of the display area are simultaneously connected with one corresponding virtual data line, and the virtual pixel units with the specific structures on the other side of the display area are simultaneously connected with the other corresponding virtual data line.
Each specific-structure virtual pixel unit is correspondingly provided with a preset common electrode array plate, a first grid metal and a second grid metal, wherein the first grid metal and the second grid metal are connected to corresponding virtual data lines of the specific-structure virtual pixel unit; wherein,
one end of a main pixel electrode and one end of a sub-pixel electrode in each virtual pixel unit with a specific structure are simultaneously connected with a data line of a corresponding column of actual pixel units in the display area;
the other end of the main pixel electrode in each virtual pixel unit with the specific structure and a corresponding preset public electrode array plate form a first through hole, and then are respectively connected with one end, far away from the virtual data line, of the corresponding first grid metal through a conductive metal oxide extending into the corresponding first through hole;
and the other end of the sub-pixel electrode in each virtual pixel unit with the specific structure is respectively connected with one end, far away from the virtual data line, of the corresponding second grid metal through the conductive metal oxide extending into the corresponding second through hole after the second through hole is formed by the sub-pixel electrode and the corresponding preset public electrode array plate.
And one end of the main pixel electrode and one end of the sub-pixel electrode in each virtual pixel unit with the specific structure are simultaneously connected with the data lines of a corresponding column of actual pixel units in the display area through three shared thin film transistors arranged on a corresponding preset common electrode array plate.
Wherein the corresponding first gate metal and second gate metal in each of the specific-structure dummy pixel units are welded together with their corresponding dummy data lines by laser light at the same time.
Wherein the conductive metal oxide is indium tin oxide.
And all the virtual pixel units except each pixel unit with a specific structure in the virtual pixel area are disconnected with any virtual data line connected with the pixel units with the specific structure.
The embodiment of the invention also provides a display device which comprises the liquid crystal panel.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, because the virtual pixel units are arranged on at least one side of two sides of each row of actual pixel units in the horizontal direction, and the virtual pixel units corresponding to the row to be detected are set to be in a specific structure, the main pixel electrodes and the sub-pixel electrodes in the virtual pixel units with the specific structure are simultaneously connected to the data lines of a certain row of actual pixel units in the display area and are also simultaneously connected to a corresponding virtual data line, after a certain row to be detected of the actual pixel units in the display area is lightened, the optimal common electrode voltage of the lightened row and the optimal data signal input time and level value can be determined by monitoring the voltage of the virtual data lines connected to the virtual pixel units with the specific structure which are horizontally distributed corresponding to the lightened row, so that the pixel units capable of monitoring the actual voltage (the virtual pixel units with the specific structure) are added and detected to determine the optimal common electrode voltage and the optimal data signal input time and level value in any row in the display area on the premise of not changing the boundary of the liquid crystal panel The optimal common electrode voltage of the pixel unit and the optimal data signal input time and level value reduce the risks of the problems of picture flicker, image retention, uneven display and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
Fig. 1 is a schematic partial connection diagram of a liquid crystal panel according to an embodiment of the invention;
fig. 2 is another partial connection diagram of a liquid crystal panel according to an embodiment of the invention;
fig. 3 is a schematic diagram illustrating another partial connection of a liquid crystal panel according to an embodiment of the invention;
fig. 4 is a schematic diagram illustrating a further partial connection of a liquid crystal panel according to an embodiment of the invention;
fig. 5 is a schematic plan view of a single actual pixel unit in a display area of a liquid crystal panel according to an embodiment of the present invention;
fig. 6 is a schematic plan structure view of a single specific-structure dummy pixel unit in a dummy pixel area of a liquid crystal panel according to an embodiment of the present invention;
fig. 7 is a schematic plan view of a single dummy pixel unit in a dummy pixel area of a liquid crystal panel, except for a dummy pixel unit with a specific structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, a liquid crystal panel according to a first embodiment of the present invention includes a display area AA for displaying an image and a virtual pixel area BB disposed at a periphery of the display area AA, where actual pixel units a of the display area AA are arranged and distributed in a matrix of rows and columns, at least one virtual pixel unit belonging to the virtual pixel area BB is correspondingly distributed on at least one of two sides of each row of actual pixel units disposed along a horizontal row direction, and a corresponding virtual data line DDL is distributed on a side of each virtual pixel unit away from the display area AA;
each virtual pixel unit corresponding to all the actual pixel units to be tested in the display area AA is set to be a specific structure virtual pixel unit B, and the main pixel electrode M and the sub-pixel electrode S in each specific structure virtual pixel unit B are simultaneously connected to the data line DL of a certain column of actual pixel units in the display area AA and are also simultaneously connected to a corresponding virtual data line DDL, so that after a certain line to be tested of the actual pixel units in the display area AA is lighted, the optimal common electrode voltage and the optimal data signal input time and level value of the lighted line heating actual pixel units can be determined by monitoring the voltage of the virtual data lines DDL connected to the specific structure virtual pixel units B which are horizontally distributed and corresponding to the actual pixel units of the lighted line.
It can be understood that, in order to facilitate monitoring the voltage of the virtual data lines DDL connected to the horizontally distributed virtual pixel units B of the specific structure corresponding to the actual pixel units of the lighting row, each virtual pixel unit B of the specific structure may be connected to a separate virtual data line DDL, so that the optimal common electrode voltage and the optimal data signal input time and level value of the lighting row in the display area AA are determined by adding the virtual pixel units B of the specific structure capable of monitoring the actual voltage, and the risk of the problems of flicker, image retention, display non-uniformity, etc. is reduced. Of course, in order to determine the accuracy of the actual voltage detected by the dummy data line DDL connected to the dummy pixel units B of the specific structure on the lighting row more conveniently, a plurality of dummy pixel units B of the specific structure on the lighting row are provided.
It should be noted that, in fig. 1, all the dummy pixel units except for each specific structure pixel unit B in the dummy pixel region BB are represented by dummy pixel units C, and any dummy pixel unit C is provided to be disconnected from any dummy data line DDL connected to the specific structure pixel unit B, and is not connected to the data line DL of any column of real pixel units in the display region AA. At this time, the detected actual voltage of the specific structure dummy pixel unit B includes the optimal common electrode voltage reflected by the main pixel electrode and the sub-pixel electrode in the specific structure dummy pixel unit B, and the input time (i.e., charging time) and level value (i.e., charging voltage magnitude) of the data signal conducted by the dummy data line DDL.
It should be noted that the row scan signals of the display area AA are output through the row scan lines driven by the GOAs, and the column data signals are output through the data lines DL driven by the plurality of source drivers. Therefore, the row scanning signals of the dummy pixel regions BB are also boosted by the row scanning lines in the same row, and the column data signals are provided by the dummy data lines DDL.
In order to reduce the wiring range of the dummy data lines DDL without changing the boundary of the liquid crystal panel as much as possible, one dummy pixel unit B with a specific structure is set for each row, the dummy pixel units are connected by the common dummy data lines DDL as much as possible, and in the process of detecting the voltage, the actual pixel units in the rows of the lighting display area AA are lighted in batches to observe the voltage reflected by the dummy pixel units B with the specific structure corresponding to the lighted rows.
In an embodiment, as shown in fig. 2 and 3, there is one specific-structure virtual pixel unit B correspondingly disposed on each actual pixel unit row to be tested in the display area AA, and the specific-structure virtual pixel units B correspondingly disposed on each actual pixel unit row to be tested in the display area AA are both located on one side of the display area AA (including the left side of fig. 2 and the right side of fig. 3) and connected to a corresponding virtual data line DDL at equal intervals, so that the situation of confusion caused by over-dense specific-structure virtual pixel units B can be avoided.
In another embodiment, as shown in fig. 4, there is one specific-structure virtual pixel unit B corresponding to each actual pixel unit row to be tested in the display area AA, and the specific-structure virtual pixel units B corresponding to all actual pixel unit rows to be tested in the display area AA are distributed in a staggered manner on two sides of the display area AA; the specific structure dummy pixel unit B on one side of the display area AA is connected to a corresponding dummy data line DDL, and the specific structure dummy pixel unit B on the other side is connected to another corresponding dummy data line DDL, so that voltages detected by corresponding lighting rows can be distinguished by two different dummy data lines DDL.
In the embodiment of the present invention, each actual pixel cell a of the display area AA has a structure as shown in fig. 5, and the main pixel electrode 51 and the sub-pixel electrode 52 in each actual pixel cell a are simultaneously connected to the data line DL of a corresponding column of actual pixel cells in the display area AA through three common thin film transistors 54 disposed on the corresponding preset common electrode array plate 53.
In the embodiment of the present invention, each specific-structure dummy pixel unit B of the dummy pixel region BB is configured as shown in fig. 6, and each specific-structure dummy pixel unit B has a corresponding preset common electrode array plate 63, and a corresponding first gate metal 64 and second gate metal 65 connected to its corresponding dummy data line DDL; wherein,
one end of the main pixel electrode 61 and one end of the sub-pixel electrode 62 in each virtual pixel unit B with a specific structure are both simultaneously connected to the data lines DL of a corresponding column of actual pixel units in the display area AA; for example, as with each actual pixel cell a in the display area AA, the data lines DL of a corresponding column of actual pixel cells in the display area AA are simultaneously connected through three common thin film transistors 66 disposed on the corresponding preset common electrode array plate 63 thereof;
the other end of the main pixel electrode 61 in each virtual pixel unit B with a specific structure is respectively connected with one end, far away from the connected virtual data line DDL, of the corresponding first gate metal 64 through the conductive metal oxide extending into the corresponding first via hole 611 after the first via hole 611 is formed by the other end of the main pixel electrode 61 and the corresponding preset common electrode array plate 63;
the other end of the sub-pixel electrode 62 in each virtual pixel unit B with a specific structure is connected to one end of the corresponding second gate metal 65, which is far away from the connected virtual data line DDL, through the conductive metal oxide extending into the corresponding second via hole 621 after the second via hole 621 is formed by the sub-pixel electrode 62 and the corresponding preset common electrode array plate 63.
It should be noted that the corresponding first gate metal 64 and second gate metal 65 in each of the specific-structure dummy pixel units B are both fused together with their corresponding dummy data lines DDL by laser light at the same time. And the conductive metal oxide connected to the first gate metal 64 and the second gate metal 65 includes, but is not limited to, indium tin oxide ITO, etc.
In the embodiment of the present invention, all the dummy pixel units C except for each specific structure pixel unit B in the dummy pixel region BB are structured as shown in fig. 7, and all the dummy pixel units C are set to be disconnected from any one of the dummy data lines DDL connected to the specific structure pixel units B, i.e., the three common thin film transistors 74, which are disposed on the corresponding preset common electrode array plate 73 of all the dummy pixel units C, disconnect the dummy data lines DDL from the main pixel electrode 71 and the sub-pixel electrode 72 thereon. Of course, all the dummy pixel cells C should not be connected to the data lines DL of any column of real pixel cells in the display area AA.
The liquid crystal panel in the first embodiment of the present invention has a working principle that a row to be tested of an actual pixel unit in a display area AA is determined and lit, and an optimal common electrode voltage of the lit row and an optimal data signal input time and level value of the lit row are reflected by detecting an actual voltage of a virtual data line DDL connected to a virtual pixel unit B of a specific structure corresponding to the lit row, so that risks of problems of flicker of a picture, image retention, display unevenness, and the like are reduced.
Corresponding to the liquid crystal panel in the first embodiment of the present invention, a second embodiment of the present invention provides a display device, which includes the liquid crystal panel in the first embodiment of the present invention, and has the same structure and connection relationship as the liquid crystal panel in the first embodiment of the present invention, so please refer to the relevant contents in the first embodiment of the present invention specifically, and details are not repeated here.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, because the virtual pixel units are arranged on at least one side of two sides of each row of actual pixel units in the horizontal direction, and the virtual pixel units corresponding to the row to be detected are set to be in a specific structure, the main pixel electrodes and the sub-pixel electrodes in the virtual pixel units with the specific structure are simultaneously connected to the data lines of a certain row of actual pixel units in the display area and are also simultaneously connected to a corresponding virtual data line, after a certain row to be detected of the actual pixel units in the display area is lightened, the optimal common electrode voltage of the lightened row and the optimal data signal input time and level value can be determined by monitoring the voltage of the virtual data lines connected to the virtual pixel units with the specific structure which are horizontally distributed corresponding to the lightened row, so that the pixel units capable of monitoring the actual voltage (the virtual pixel units with the specific structure) are added and detected to determine the optimal common electrode voltage and the optimal data signal input time and level value in any row in the display area on the premise of not changing the boundary of the liquid crystal panel The optimal common electrode voltage of the pixel unit and the optimal data signal input time and level value reduce the risks of the problems of picture flicker, image retention, uneven display and the like.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (9)
1. A liquid crystal panel comprises a display area for displaying images and virtual pixel areas arranged on the periphery of the display area, and is characterized in that actual pixel units of the display area are distributed in a row-column matrix arrangement manner, at least one virtual pixel unit belonging to the virtual pixel area is correspondingly distributed on at least one of two sides of each row of actual pixel units arranged along the horizontal row direction, and a corresponding virtual data line is uniformly distributed on one side of each virtual pixel unit far away from the display area;
each virtual pixel unit corresponding to all rows to be tested of the actual pixel units in the display area is set to be a specific structure virtual pixel unit, and a main pixel electrode and a sub-pixel electrode in each specific structure virtual pixel unit are simultaneously connected to a data line of a certain column of actual pixel units in the display area and are also simultaneously connected to a corresponding virtual data line, so that after a certain row to be tested of the actual pixel units in the display area is lightened, the optimal common electrode voltage and the optimal data signal input time and level value of the actual pixel units of the lightened row are determined by monitoring the voltage of virtual data lines connected to the horizontally distributed specific structure virtual pixel units corresponding to the actual pixel units of the lightened row.
2. The liquid crystal panel of claim 1, wherein there is one virtual pixel unit with a specific structure corresponding to each row of actual pixel units to be tested in the display area, and the virtual pixel units with a specific structure corresponding to each row of actual pixel units to be tested in the display area are located on one side of the display area at the same time and are connected to a corresponding virtual data line at regular intervals.
3. The liquid crystal panel according to claim 1, wherein one virtual pixel unit with a specific structure is disposed in the display region corresponding to each row of actual pixel units to be tested, and the virtual pixel units with the specific structure are disposed in the display region at two sides of the display region in a staggered manner corresponding to all rows of actual pixel units to be tested; the virtual pixel units with the specific structures on one side of the display area are simultaneously connected with one corresponding virtual data line, and the virtual pixel units with the specific structures on the other side of the display area are simultaneously connected with the other corresponding virtual data line.
4. The liquid crystal panel according to claim 2 or 3, wherein a preset common electrode array plate corresponds to each of the specific-structure dummy pixel units, and a first gate metal and a second gate metal connected to their corresponding dummy data lines correspond to each of the specific-structure dummy pixel units; wherein,
one end of a main pixel electrode and one end of a sub-pixel electrode in each virtual pixel unit with a specific structure are simultaneously connected with a data line of a corresponding column of actual pixel units in the display area;
the other end of the main pixel electrode in each virtual pixel unit with the specific structure and a corresponding preset public electrode array plate form a first through hole, and then are respectively connected with one end, far away from the virtual data line, of the corresponding first grid metal through a conductive metal oxide extending into the corresponding first through hole;
and the other end of the sub-pixel electrode in each virtual pixel unit with the specific structure is respectively connected with one end, far away from the virtual data line, of the corresponding second grid metal through the conductive metal oxide extending into the corresponding second through hole after the second through hole is formed by the sub-pixel electrode and the corresponding preset public electrode array plate.
5. The liquid crystal panel according to claim 4, wherein one end of the main pixel electrode and one end of the sub-pixel electrode in each of the specific-structure dummy pixel cells are simultaneously connected to the data lines of a corresponding column of the real pixel cells in the display area through three common thin film transistors disposed on a corresponding pre-set common electrode array plate thereof.
6. The liquid crystal panel of claim 5, wherein the corresponding first gate metal and second gate metal in each of the structurally specific dummy pixel cells are both fused together with their corresponding dummy data lines by laser light at the same time.
7. The liquid crystal panel according to claim 6, wherein the conductive metal oxide is indium tin oxide.
8. The liquid crystal panel according to claim 7, wherein all of the dummy pixel units except for each of the specific-structure pixel units in the dummy pixel region are provided with a disconnection from any of the dummy data lines connecting the specific-structure pixel units.
9. A display device comprising the liquid crystal panel according to any one of claims 1 to 8.
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| CN109828397A (en) * | 2019-04-09 | 2019-05-31 | 惠科股份有限公司 | Pixel circuit structure |
| CN111025697B (en) * | 2019-12-16 | 2021-06-01 | 武汉华星光电技术有限公司 | Liquid crystal display panel and display device |
| CN111429857A (en) * | 2020-04-10 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Pixel driving circuit of display panel |
| CN111415610B (en) * | 2020-04-26 | 2021-07-23 | Tcl华星光电技术有限公司 | Voltage regulation method of virtual pixel, display panel and storage medium |
| CN111477186B (en) * | 2020-05-07 | 2021-03-16 | Tcl华星光电技术有限公司 | Time schedule controller, display panel and driving method thereof |
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| JP2012173489A (en) * | 2011-02-21 | 2012-09-10 | Seiko Epson Corp | Electro-optical device, drive method for the electro-optical device, and electronic equipment |
| CN103915475A (en) * | 2012-12-28 | 2014-07-09 | 乐金显示有限公司 | Organic light emitting display device |
| CN105204213A (en) * | 2015-11-06 | 2015-12-30 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
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Address after: No.9-2 Tangming Avenue, Guangming New District, Shenzhen, Guangdong 518000 Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: No.9-2 Tangming Avenue, Guangming New District, Shenzhen, Guangdong 518000 Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |