CN107861906A - A kind of FPGA and arm processor high-speed data interactive system and method - Google Patents
A kind of FPGA and arm processor high-speed data interactive system and method Download PDFInfo
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- CN107861906A CN107861906A CN201710878173.7A CN201710878173A CN107861906A CN 107861906 A CN107861906 A CN 107861906A CN 201710878173 A CN201710878173 A CN 201710878173A CN 107861906 A CN107861906 A CN 107861906A
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- fpga
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a kind of FPGA and arm processor high-speed data interactive system and method, the system includes FPGA, arm processor and internal communication bus, connected between FPGA and arm processor by internal communication bus；The internal communication bus includes AXI_HP buses, AXI_GP buses and AXI_ACP buses, and AXI_HP buses are used to provide the high band wide data path that FPGA accesses memory module in arm processor；AXI_GP buses are used to provide the universal data interface between FPGA and arm processor, make FPGA and arm processor peripheral hardware each other；AXI_ACP buses are used for the caching Cache that arm processor is directly accessed for FPGA；Methods described includes establishing FPGA and arm processor high-speed data channel by internal communication bus；High band wide data between progress FPGA and arm processor interacts, conventional data interaction and instruction accelerator data interact.The invention provides a kind of FPGA and arm processor high-speed data interactive system and method, completes the data interaction between FPGA and arm processor by internal communication bus, improves reliability and message transmission rate.
Description
Technical field
The present invention relates to the data interaction of FPGA and arm processor, more particularly to a kind of FPGA and the height of arm processor
Fast data interaction system and method.
Background technology
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL, GAL,
The product further developed on the basis of the programming devices such as CPLD, as a kind of half in application specific integrated circuit (ASIC) field
Custom circuit and occur, both solved the deficiency of custom circuit, it is limited to overcome original programming device gate circuit number again
Shortcoming；ARM（Advanced RISC Machines）One 32 bit reduced instruction set computer (RISC) processor architecture, ARM processing
Device is widely used in many Embedded System Designs, and there is arm processor command length to fix, and execution efficiency is high, low cost
Etc. advantage.
In actual application, many times need to be communicated FPGA with arm processor, to realize to data
Processing and upload, but it is all to use SPI/ABS buses that traditional FPGA communicates with ARM, transmission rate can only achieve tens more slowly
To hundreds of million, it is designed using independent component, cost is higher, and occurs data/address bus arbitration in data transmission procedure at any time
Problem, cause the loss and mistake of data, it is necessary to which scrambled code function, otherwise get muddled phenomenon.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of FPGA and the high-speed data of arm processor
Interactive system and method, the data interaction between FPGA and arm processor is completed by internal communication bus, improve data friendship
Mutual reliability and message transmission rate.
The purpose of the present invention is achieved through the following technical solutions：A kind of FPGA and arm processor high-speed data
Interactive system, including FPGA, arm processor and internal communication bus, pass through intercommunication between the FPGA and arm processor
Bus connects；
The internal communication bus includes AXI_HP buses, AXI_GP buses and AXI_ACP buses, and the AXI_HP buses are used for
The high band wide data path that FPGA accesses memory module in arm processor is provided；The AXI_GP buses be used for provide FPGA with
Universal data interface between arm processor, make FPGA and arm processor peripheral hardware each other；The AXI_ACP buses are used to supply
FPGA directly accesses the caching Cache of arm processor.The AXI_HP buses include 4 AXI_HP interfaces, and each AXI_HP connects
Mouth includes two fifo buffers, a read buffer and a write buffer；The AXI_GP buses include two masters
Interface, two from interface；The AXI_ACP buses include 5 independent high-speed channels.The AXI_HP interfaces are relied in FPGA
The data completed between FPGA and arm processor of dma controller carry.
The data interactive method of described a kind of FPGA and arm processor high-speed data interactive system, including following step
Suddenly：
S1. FPGA and arm processor high-speed data channel are established by internal communication bus；
S2. using the high-speed data channel established, the data interaction between FPGA and arm processor is carried out, including：High bandwidth number
According to interaction, conventional data interaction and instruction accelerator data interaction.
Wherein, the high band wide data between the FPGA and arm processor is interacted including following sub-step：FPGA passes through
Memory module in AXI_HP bus access arm processors, the memory module include the DDR and OCM of arm processor；Rely on
The data of described dma controller are carried, and FPGA directly carries out digital independent to the memory module of arm processor or data are write
Enter, the high speed for completing high band wide data between FPGA and arm processor interacts.
Wherein, the conventional data between the FPGA and arm processor is interacted including following sub-step：It is total by AXI_GP
Line, make FPGA and arm processor peripheral hardware each other；Arm processor is accessed by FPGA, or FPGA is accessed by arm processor,
The control information of low speed and the transmission of low volume data are completed between FPGA and arm processor.
Wherein, the instruction accelerator data between the FPGA and arm processor is interacted including following sub-step：FPGA leads to
The caching Cache of AXI_ACP bus access arm processors is crossed, obtains the data in caching Cache；FPGA is in caching Cache
Data carry out logic accelerate computing, and the very first time by logic accelerate computing result returned to by AXI_ACP buses
Arm processor.
The beneficial effects of the invention are as follows：The present invention completes the number between FPGA and arm processor by internal communication bus
According to interaction, merging for FPGA and arm processor is realized, improves the reliability and message transmission rate of data interaction.
Brief description of the drawings
Fig. 1 is the system principle diagram of the present invention；
Fig. 2 is flow chart of the method for the present invention.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in figure 1, the high-speed data interactive system of a kind of FPGA and arm processor, including FPGA, arm processor and
Internal communication bus, connected between the FPGA and arm processor by internal communication bus；
The internal communication bus includes AXI_HP buses, AXI_GP buses and AXI_ACP buses, and the AXI_HP buses are used for
The high band wide data path that FPGA accesses memory module in arm processor is provided；The AXI_GP buses be used for provide FPGA with
Universal data interface between arm processor, make FPGA and arm processor peripheral hardware each other；The AXI_ACP buses are used to supply
FPGA directly accesses the caching Cache of arm processor.The AXI_HP buses include 4 AXI_HP interfaces, and each AXI_HP connects
Mouth includes two fifo buffers, a read buffer and a write buffer；The AXI_GP buses include two masters
Interface, two from interface；The AXI_ACP buses include 5 independent high-speed channels.The AXI_HP interfaces are relied in FPGA
The data completed between FPGA and arm processor of dma controller carry.
In embodiments herein, described internal communication bus can be realized using XC7Z020-CLG484, make
Obtain the advantage of the invention for having low cost, low in energy consumption, small volume, risk low；
As shown in Fig. 2 the data interactive method of described a kind of FPGA and arm processor high-speed data interactive system, including
Following steps：
S1. FPGA and arm processor high-speed data channel are established by internal communication bus；
S2. using the high-speed data channel established, the data interaction between FPGA and arm processor is carried out, including：High bandwidth number
According to interaction, conventional data interaction and instruction accelerator data interaction.
High band wide data between the FPGA and arm processor is interacted including following sub-step：FPGA passes through AXI_HP
Memory module in bus access arm processor, the memory module include the DDR and OCM of arm processor；Described in relying on
The data of dma controller are carried, and FPGA directly carries out digital independent to the memory module of arm processor or data write, and completes
The high speed alternating transmission of high band wide data between FPGA and arm processor.
Conventional data between the FPGA and arm processor is interacted including following sub-step：By AXI_GP buses, make
FPGA and arm processor peripheral hardware each other；Arm processor is accessed by FPGA, or FPGA is accessed by arm processor, in FPGA and
The control information of low speed and the transmission of low volume data are completed between arm processor.
Instruction accelerator data between the FPGA and arm processor is interacted including following sub-step：FPGA passes through
The caching Cache of AXI_ACP bus access arm processors, obtain the data in caching Cache；FPGA is in caching Cache
Data carry out logic and accelerate computing, and accelerate the result of computing to return to ARM by AXI_ACP buses logic in the very first time
Processor.
In data exchange process, the high speed that high band wide data can either be completed between FPGA and arm processor interacts；And can
Enough so that FPGA and arm processor peripheral hardware each other, complete the control information of low speed and the transmission of low volume data；It can also lead to simultaneously
Cross the interaction of instruction accelerator data so that the data that FPGA is cached to arm processor in Cache carry out logic and accelerate computing, real
The acceleration of existing arm processor；So complete FPGA with arm processor merging on the whole, improve the reliable of data interaction
Property and message transmission rate.Present invention could apply under a variety of scenes, for example, in certain embodiments, the present invention
It can be used for the collection and processing of high speed spectrum monitoring data；System is interacted with the high-speed data of arm processor by above-mentioned FPGA
High speed spectrum monitoring data are acquired and handled by system and method, then upload to the prison that PC realizes frequency spectrum by Ethernet
Survey and show, and then ensure that spectrum monitoring and the effect of display.In further embodiments, it is can also be applied to video
The acquisition process of image information, because internal communication bus completes merging for FPGA and arm processor, therefore it can significantly improve
The treatment effeciency of message transmission rate and video image.
Claims (7)
1. a kind of FPGA and arm processor high-speed data interactive system, it is characterised in that：Including FPGA, arm processor and interior
Portion's communication bus, connected between the FPGA and arm processor by internal communication bus；
The internal communication bus includes AXI_HP buses, AXI_GP buses and AXI_ACP buses, and the AXI_HP buses are used for
The high band wide data path that FPGA accesses memory module in arm processor is provided；The AXI_GP buses be used for provide FPGA with
Universal data interface between arm processor, make FPGA and arm processor peripheral hardware each other；The AXI_ACP buses are used to supply
FPGA directly accesses the caching Cache of arm processor.
2. a kind of FPGA according to claim 1 and arm processor high-speed data interactive system, it is characterised in that：Institute
Stating AXI_HP buses includes 4 AXI_HP interfaces, and each AXI_HP interfaces include two fifo buffers, and one is read buffering
Device and a write buffer；The AXI_GP buses include two main interfaces, and two from interface；The AXI_ACP buses include 5
Individual independent high-speed channel.
3. a kind of FPGA according to claim 2 and arm processor high-speed data interactive system, it is characterised in that：Institute
The data stated between dma controller completion FPGA and arm processor that AXI_HP interfaces are relied in FPGA are carried.
4. the data interaction side of the high-speed data interactive system of a kind of FPGA and arm processor according to claim 1 ~ 3
Method, it is characterised in that：Comprise the following steps：
S1. FPGA and arm processor high-speed data channel are established by internal communication bus；
S2. using the high-speed data channel established, the data interaction between FPGA and arm processor is carried out, including：High bandwidth number
According to interaction, conventional data interaction and instruction accelerator data interaction.
5. the data interactive method of the high-speed data interactive system of a kind of FPGA according to claim 4 and arm processor,
It is characterized in that：High band wide data between the FPGA and arm processor is interacted including following sub-step：
FPGA includes the DDR of arm processor by memory module in AXI_HP bus access arm processors, the memory module
And OCM；
The data for relying on described dma controller are carried, and FPGA directly carries out digital independent to the memory module of arm processor
Or data write-in, the high speed for completing high band wide data between FPGA and arm processor interact.
6. the data interactive method of the high-speed data interactive system of a kind of FPGA according to claim 4 and arm processor,
It is characterized in that：Conventional data between the FPGA and arm processor is interacted including following sub-step：
By AXI_GP buses, make FPGA and arm processor peripheral hardware each other；
Arm processor is accessed by FPGA, or FPGA is accessed by arm processor, low speed is completed between FPGA and arm processor
Control information and low volume data transmission.
7. the data interactive method of the high-speed data interactive system of a kind of FPGA according to claim 4 and arm processor,
It is characterized in that：Instruction accelerator data between the FPGA and arm processor interact including：
FPGA obtains the data in caching Cache by the caching Cache of AXI_ACP bus access arm processors；
FPGA to caching Cache in data carry out logic accelerate computing, and the very first time by logic accelerate computing result
Arm processor is returned to by AXI_ACP buses.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710878173.7A CN107861906A (en) | 2017-09-26 | 2017-09-26 | A kind of FPGA and arm processor high-speed data interactive system and method |
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| CN201710878173.7A CN107861906A (en) | 2017-09-26 | 2017-09-26 | A kind of FPGA and arm processor high-speed data interactive system and method |
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Cited By (5)
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|---|---|---|---|---|
| CN108873667A (en) * | 2018-07-13 | 2018-11-23 | 昆明理工大学 | A kind of time measurement system and its method based under linux system |
| CN109542836A (en) * | 2018-11-05 | 2019-03-29 | 西安智多晶微电子有限公司 | A kind of SOC chip and embedded system of integrated dual processor |
| CN109739695A (en) * | 2018-12-13 | 2019-05-10 | 南京航空航天大学 | ARM and FPGA dissimilar redundancy communication means in unmanned aerial vehicle (UAV) control device |
| CN111258936A (en) * | 2018-12-03 | 2020-06-09 | 郑州信大捷安信息技术股份有限公司 | DMA data transmission system and data transmission method |
| CN113326670A (en) * | 2021-05-31 | 2021-08-31 | 上海阵量智能科技有限公司 | Prototype verification system, method, processing unit and equipment |
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Cited By (7)
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| CN108873667A (en) * | 2018-07-13 | 2018-11-23 | 昆明理工大学 | A kind of time measurement system and its method based under linux system |
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| CN113326670B (en) * | 2021-05-31 | 2024-06-07 | 上海阵量智能科技有限公司 | Prototype verification system, method, processing unit and device |
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Application publication date: 20180330 |
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