CN107861047B - Detection system and detection method for safety test mode - Google Patents
Detection system and detection method for safety test mode Download PDFInfo
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- CN107861047B CN107861047B CN201711058364.5A CN201711058364A CN107861047B CN 107861047 B CN107861047 B CN 107861047B CN 201711058364 A CN201711058364 A CN 201711058364A CN 107861047 B CN107861047 B CN 107861047B
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- 238000001514 detection method Methods 0.000 title claims abstract description 59
- 238000011076 safety test Methods 0.000 title claims abstract description 28
- 238000012360 testing method Methods 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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Abstract
The invention discloses a detection system and a detection method of a safety test mode, wherein the detection system is used for preventing a test circuit of a chip from entering the safety test mode again after being disabled, and the detection system of the safety test mode comprises: the device comprises a sequential logic control module, a detection circuit module and a trigger module. The trigger module is used for generating a high-level or low-level trigger signal according to the on-off state. The sequential logic control module outputs a high-level test mode signal according to the low-level trigger signal, so that the chip can enter a safe test mode; or, the sequential logic control module outputs a low-level test mode signal according to a high-level trigger signal, so that the detection circuit module outputs a self-destruction signal to enable the chip to carry out self-destruction operation. Therefore, the detection system of the safety test mode provided by the invention has the advantages that the protection effect on sensitive information of the chip is improved by multiple guarantees, the realization requirements of most processes are met, and the detection system can be widely applied to various safety chips.
Description
Technical Field
The present invention relates to the field of information security of integrated circuits, and in particular, to a system and a method for detecting a security test mode applied to a security chip.
Background
Some manufacturing defects exist in the chip production process, chip testing is needed to reflect the real situation of the chip, and the problem chip is screened out. The security chip also usually has a test circuit to ensure that the chip product delivered to the user can operate correctly and reliably, so the test circuit is an essential component of the security chip. In order to improve the testing efficiency and reduce the design complexity of the testing circuit, the testing circuit can generally access all resources in the chip, and the security level of the testing mode is very high. In order to effectively resist an attacker from using a test mode, stealing key data of users in a secure chip, tampering a chip program and the like, a test circuit needs to be reliably and irreversibly abolished after the chip is tested.
In the prior art, a certain control signal or a clock and a reset signal are usually placed in a scribing slot as a chip Fuse (Fuse), and after the security chip is tested, the chip is broken by a scribing mode, and then the chip can not enter a test mode.
With the rapid development of the invasive attack technology, the ability of an attacker to reconnect the broken Fuse signal in the scribing slot by using technical means such as FIB and the like is greatly enhanced, so that the function of the test mode circuit is recovered, and sensitive information and important data in the security chip are obtained.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a detection system and a detection method of a safety test mode, which can improve the protection effect on chip sensitive information by multiple guarantees, meet the realization requirements of most processes and can be widely applied to various safety chips.
To achieve the above object, according to an aspect of the present invention, there is provided a system for detecting a security test mode to prevent a test circuit of a chip from being disabled and then entering the security test mode again, the system for detecting the security test mode including: the device comprises a sequential logic control module, a detection circuit module and a trigger module. The sequential logic control module is used for outputting a test mode signal; the detection circuit module detects the circuit state of the detection system, and can output a self-destruction signal according to the circuit state; the trigger module is electrically connected with the sequential logic control module and is used for generating a high-level or low-level trigger signal according to the on-off state; the sequential logic control module outputs a high-level test mode signal according to a low-level trigger signal, so that the chip can enter a safe test mode; or, the sequential logic control module outputs a low-level test mode signal according to a high-level trigger signal, so that the detection circuit module outputs a self-destruction signal to enable the chip to carry out self-destruction operation.
Preferably, in the above technical solution, the triggering module includes: the first fuse is electrically connected with the sequential logic control module and used for generating a first trigger signal according to the cut state; if the first fuse wire is not broken, the first trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode; if the first fuse wire is broken, the first trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal at a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Preferably, in the above technical solution, the detection system of the safety test mode further includes: scribing a groove; a part of the first fuse is arranged in the scribing groove and is scribed in the scribing groove.
Preferably, in the above technical solution, the triggering module further includes: a second fuse with one end electrically connected to the ground and the other end connected with the sequential logic control module through the scribing slot, wherein the second fuse is used for generating a second trigger signal according to the scribed state; if the second fuse wire is not broken, the second trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode; if the second fuse is broken, the second trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal at a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Preferably, in the above technical solution, the trigger module further includes a third fuse electrically connected to the detection circuit module, a portion of the third fuse is disposed in the scribe line, a portion of the third fuse is in a disconnected state, and the third fuse is configured to generate a third trigger signal according to the connected state; if the first fuse or/and the second fuse is/are connected with the third fuse, the third trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Preferably, in the above technical solution, the first fuse has a first resistor, and when a part of the first fuse in the scribe line is scribed, the first fuse pulls up the first resistor to a high level and outputs the first trigger signal to the sequential logic control module as the high level; and/or the second fuse has the second resistance, when a part of the second fuse in the scribing slot is scribed, the second fuse pulls up the second resistance to be set as high level and outputs the second trigger signal as high level to the sequential logic control module; and/or the third fuse has a third resistor and a fourth resistor, and the third fuse is a voltage division signal of the third resistor and the fourth resistor.
Preferably, in the above technical solution, the detection circuit module includes: a reference source unit and a comparator. The reference source unit is used for providing a reference signal; the comparator is used for comparing the voltage division signal with the reference signal, and the comparator can output a self-destruction signal.
According to another aspect of the present invention, there is provided a method for detecting a security test mode, comprising: acquiring the state of at least one first fuse wire electrically connected with the sequential logic control module; generating a first trigger signal according to a state that the first fuse is cut; if the first fuse wire is not broken, the first trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode; if the first fuse wire is broken, the first trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal at a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Compared with the prior art, the invention has the following beneficial effects: the detection system and the detection method of the safety test mode not only can improve the difficulty of the reconnection of fuse signals, but also can improve the protection effect of sensitive information of the chip by adding the detection circuit module for the reconnection attack of the fuse and starting the self-destruction operation of the chip by detecting that the fuse is attacked.
Drawings
Fig. 1 is a schematic diagram of a detection system for a safety test mode according to the present invention.
Fig. 2 is a schematic structural diagram of a detection circuit module of the detection system in the safety test mode according to the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
As shown in fig. 1 to 2, a system for detecting a security test mode according to an embodiment of the present invention is used to prevent a test circuit of a chip from being disabled and then entering the security test mode again, and the system for detecting a security test mode includes: the device comprises a sequential logic control module, a detection circuit module, a scribing groove and a trigger module. The sequential logic control module is used for outputting a test mode signal; the detection circuit module is used for detecting the circuit state of the detection system and can output a self-destruction signal according to the circuit state; the trigger module is electrically connected with the sequential logic control module and is used for generating a high-level or low-level trigger signal according to the on-off state; the sequential logic control module outputs a high-level test mode signal according to a low-level trigger signal, so that the chip can enter a safe test mode; or, the sequential logic control module outputs a low-level test mode signal according to a high-level trigger signal, so that the detection circuit module outputs a self-destruction signal to enable the chip to carry out self-destruction operation.
Preferably, the triggering module comprises: the first fuse is electrically connected with the sequential logic control module and used for generating a first trigger signal according to the cut state; if the first fuse wire is not broken, the first trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode; if the first fuse wire is broken, the first trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal at a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Preferably, the detection system of the safety test mode further comprises: scribing a groove; a part of the first fuse is arranged in the scribing groove and is scribed in the scribing groove.
Preferably, the trigger module further comprises: a second fuse with one end electrically connected to the ground and the other end connected with the sequential logic control module through the scribing slot, wherein the second fuse is used for generating a second trigger signal according to the scribed state; if the second fuse wire is not broken, the second trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode; if the second fuse is broken, the second trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal at a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Preferably, the trigger module further includes a third fuse electrically connected to the detection circuit module, a portion of the third fuse is disposed in the scribe line, a portion of the third fuse is in a disconnected state, and the third fuse is configured to generate a third trigger signal according to the connected state; if the first fuse or/and the second fuse is/are connected with the third fuse, the third trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Preferably, the first fuse has a first resistor (resistor R1), when a part of the first fuse in the scribe line is cut, the first fuse pulls up the first resistor to a high level and outputs a first trigger signal to the sequential logic control module as the high level, and the sequential logic control module outputs a test mode signal as the low level, so that the chip cannot enter the safe test mode; and/or the second fuse has the second resistance (resistance R2), when a part of the second fuse in the scribing slot is cut, the second fuse pulls up the second resistance to be set to high level, and outputs the second trigger signal to be high level to the sequential logic control module, the sequential logic control module outputs the test mode signal to be low level, thereby the chip can not enter the safe test mode; and/or the third fuse has a third resistor (R3) and a fourth resistor (R4), and the third fuse is a voltage division signal of the third resistor and the fourth resistor.
Preferably, the detection circuit module comprises: a reference source unit and a comparator. The reference source unit is used for providing a reference signal; the comparator is used for comparing the voltage division signal with the reference signal, and the comparator can output a self-destruction signal.
According to another embodiment of the present invention, a method for detecting a security test mode includes: acquiring the state of at least one first fuse wire electrically connected with the sequential logic control module; generating a first trigger signal according to a state that the first fuse is cut; if the first fuse wire is not broken, the first trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode; if the first fuse wire is broken, the first trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal at a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
Preferably, the method for detecting the safety test mode further comprises: acquiring the state of the second fuse wire which is electrically connected with the sequential logic control module and is cut off; generating a second trigger signal according to a state that the second fuse is cut; if the second fuse wire is not broken, the second trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode; if the second fuse is broken, the second trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal at a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation. Acquiring the connected state of a third fuse electrically connected with the detection circuit module; generating a third trigger signal according to a state that the third fuse is connected; if the first fuse or/and the second fuse is/are connected with the third fuse, the third trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
In practical application, only when the first fuse and the second fuse are normally connected and the third fuse has no connection relation with the first fuse and the second fuse, the output test mode signal is high-level and effective, namely the chip enters a safety test mode. If only one of the first fuse and the second fuse is broken, or if only the third fuse is detected to be connected with the first fuse or/and the second fuse, the test mode signal is output to be low level, the test mode cannot be entered, and the self-destruction signal is output.
As shown in fig. 2, the third fuse is a voltage division signal of a third resistor (resistor R3) and a fourth resistor (resistor R4), and the voltage division signal is compared with a reference signal provided by a reference source by a comparator to output a self-destruction signal. When the third fuse is not connected with the first fuse and the second fuse, namely the third fuse is only the voltage division signal of the third resistor and the fourth resistor, the reference signal level is higher than that of the third fuse, and the output self-destruction signal is low level. When the third fuse is connected with the first fuse, namely the third fuse is connected with the first resistor in parallel and then is subjected to voltage division with the fourth resistor, the reference signal level is lower than that of the third fuse at the moment, and the output self-destruction signal is high level (self-destruction operation is started). Similarly, when the third fuse is connected to the second fuse, or the third fuse is connected to the second fuse and the first fuse at the same time, that is, the third fuse is formed by connecting the third resistor and the second resistor in parallel, or connecting the third resistor, the second resistor and the first resistor in parallel and then dividing the voltage with the fourth resistor, and the reference signal level is lower than that of the third fuse at this time, and the output self-destruction signal is at a high level. When the self-destruction signal is set to be high level, the chip is certainly attacked in an invasive manner at the moment, the chip is started to carry out self-destruction operation, the nonvolatile memory is erased in a whole chip mode, then the chip is reset in the whole chip mode, and therefore sensitive data of the chip are prevented from being leaked.
In summary, the detection system and the detection method of the security test mode of the invention not only can improve the difficulty of the reconnection of the fuse signal, but also can add the detection circuit module for the reconnection attack of the fuse, and can multiply ensure and improve the protection effect of the chip sensitive information by detecting that the fuse is attacked to start the self-destruction operation of the chip.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (9)
1. A system for detecting a security test mode, for preventing a test circuit of a chip from entering the security test mode again after being disabled, the system comprising:
a sequential logic control module for outputting a test mode signal;
the detection circuit module is used for detecting the circuit state of the detection system and can output a self-destruction signal according to the circuit state; and
the trigger module is electrically connected with the sequential logic control module and used for generating a high-level or low-level trigger signal according to the on-off state, and the trigger module comprises a first fuse wire which is electrically connected with the sequential logic control module and used for generating a first trigger signal according to the cut-off state;
if the first fuse wire is not broken, the first trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs the test mode signal as a high level, so that the chip can enter a safety test mode;
if the first fuse is broken, the first trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs the self-destruction signal to enable the chip to perform self-destruction operation.
2. The system for detecting a safety test mode according to claim 1, further comprising:
scribing a groove;
and a part of the first fuse wire is arranged in the scribing groove and is scribed in the scribing groove.
3. The system for detecting a security test mode of claim 2, wherein the trigger module further comprises:
a second fuse, one end of which is electrically connected to the ground end and the other end of which is connected with the sequential logic control module through the scribing slot, wherein the second fuse is used for generating a second trigger signal according to the scribed state;
if the second fuse is not broken, the second trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs the test mode signal as a high level, so that the chip can enter a safety test mode;
if the second fuse is broken, the second trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs the self-destruction signal to enable the chip to perform self-destruction operation.
4. The system for detecting a security test mode of claim 3, wherein the trigger module further comprises:
a third fuse electrically connected to the detection circuit module, a portion of the third fuse being disposed in the scribe line, the portion of the third fuse being in a disconnected state, and the third fuse being configured to generate a third trigger signal according to the connected state;
if the first fuse or/and the second fuse is/are connected with the third fuse, the third trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs the self-destruction signal to enable the chip to perform self-destruction operation.
5. The system for detecting a safety test mode according to claim 4,
the first fuse is provided with a first resistor, and when the part of the first fuse in the scribing slot is scribed, the first fuse pulls the first resistor to be at a high level and outputs the first trigger signal to be at the high level to the sequential logic control module; and/or
The second fuse is provided with a second resistor, and when the part of the second fuse in the scribing slot is scribed, the second fuse pulls the second resistor to be set to be a high level and outputs the second trigger signal to be the high level to the sequential logic control module; and/or
The third fuse is provided with a third resistor and a fourth resistor, and the third fuse is a voltage division signal of the third resistor and the fourth resistor.
6. The system for detecting the safety test mode according to claim 5, wherein the detection circuit module comprises:
a reference source unit to provide a reference signal; and
a comparator to compare the divided voltage signal with the reference signal, and the comparator is capable of outputting the self-destruction signal.
7. A method for detecting a security test mode, comprising:
acquiring the state of at least one first fuse wire electrically connected with the sequential logic control module;
generating a first trigger signal according to the state that the first fuse is cut;
if the first fuse wire is not broken, the first trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode;
if the first fuse wire is broken, the first trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
8. The method for detecting a security test mode according to claim 7, further comprising:
acquiring the state of the second fuse wire which is electrically connected with the sequential logic control module and is cut off;
generating a second trigger signal according to the state that the second fuse is cut;
if the second fuse wire is not broken, the second trigger signal transmitted to the sequential logic control module is at a low level, and the sequential logic control module outputs a test mode signal as a high level, so that the chip can enter a safety test mode;
if the second fuse is broken, the second trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs a self-destruction signal to enable the chip to perform self-destruction operation.
9. The method for detecting a security test mode according to claim 8, further comprising:
acquiring the connected state of a third fuse electrically connected with the detection circuit module;
generating a third trigger signal according to a state that the third fuse is connected;
if the first fuse or/and the second fuse is/are connected with the third fuse, the third trigger signal transmitted to the sequential logic control module is at a high level, and the sequential logic control module outputs the test mode signal as a low level, so that the detection circuit module outputs the self-destruction signal to enable the chip to perform self-destruction operation.
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| CN110261717B (en) * | 2019-07-15 | 2022-01-28 | 立讯精密工业（滁州）有限公司 | Connector assembly test circuit and test method thereof |
| CN110399691A (en) * | 2019-07-31 | 2019-11-01 | 中国工程物理研究院电子工程研究所 | A kind of the all-electronin fuze safety Logic control module and its software timing design method of high security |
| CN110648964A (en) * | 2019-10-30 | 2020-01-03 | 华虹半导体(无锡)有限公司 | Method for repairing fuse circuit of chip |
| CN110995233B (en) * | 2019-11-11 | 2023-10-13 | 北京中电华大电子设计有限责任公司 | Method and circuit for high-safety calibration and screening test |
| CN112749419B (en) * | 2020-12-31 | 2023-11-21 | 广州万协通信息技术有限公司 | Protection device and method for safety chip test mode |
| CN117785590B (en) * | 2024-02-27 | 2024-05-28 | 深圳市纽创信安科技开发有限公司 | Chip and chip data protection method |
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| JP2000172573A (en) * | 1998-12-10 | 2000-06-23 | Toshiba Corp | Digital integrated circuit |
| JP2002214298A (en) * | 2001-01-17 | 2002-07-31 | Seiko Epson Corp | Semiconductor integrated circuit device and its manufacturing method |
| US6766468B2 (en) * | 2001-07-11 | 2004-07-20 | International Business Machines Corporation | Memory BIST and repair |
| CN103530575A (en) * | 2012-07-04 | 2014-01-22 | 北京中电华大电子设计有限责任公司 | Protection method for chip testing mode |
| CN103227167B (en) * | 2013-04-08 | 2015-07-22 | 北京昆腾微电子有限公司 | Chip and test mode protection circuit and method of chip |
| CN104678284B (en) * | 2013-12-03 | 2017-11-14 | 北京中电华大电子设计有限责任公司 | A kind of novel test control circuit and method for improving chip robustness |
| JP2015225990A (en) * | 2014-05-29 | 2015-12-14 | パナソニックＩｐマネジメント株式会社 | Semiconductor device and evaluation method of the same |
| CN104502830A (en) * | 2014-12-18 | 2015-04-08 | 重庆智锐德科技有限公司 | Chip testing device |
| CN106326781B (en) * | 2016-08-22 | 2019-04-19 | 大唐微电子技术有限公司 | A kind of method and apparatus for protecting chip test mode |
| CN206353192U (en) * | 2016-12-01 | 2017-07-25 | 北京同方微电子有限公司 | A kind of safety circuit for chip testing |
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