CN107634101A - Semiconductor field effect transistor and its manufacture method with three-stage oxygen buried layer - Google Patents
Semiconductor field effect transistor and its manufacture method with three-stage oxygen buried layer Download PDFInfo
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- CN107634101A CN107634101A CN201710861809.7A CN201710861809A CN107634101A CN 107634101 A CN107634101 A CN 107634101A CN 201710861809 A CN201710861809 A CN 201710861809A CN 107634101 A CN107634101 A CN 107634101A
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- 229910052760 oxygen Inorganic materials 0.000 title claims abstract description 40
- 239000001301 oxygen Substances 0.000 title claims abstract description 40
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000005669 field effect Effects 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 34
- 239000010703 silicon Substances 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 33
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000000605 extraction Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 241000321453 Paranthias colonus Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
The invention discloses the semiconductor field effect transistor with three-stage oxygen buried layer and its manufacture method, the oxygen buried layer of the transistor is three stage structure, BOX and BOX at source and drain both ends below body is separated, while active area and substrate are isolated by this three sections of BOX again；Compared with traditional SOI technique, BOX at body of the present invention from substrate bottom closer to；P+ layers are added in source, leakage both ends bottom simultaneously, so that source, leakage both ends isolate with BOX layer.Based on said structure, even if the positive charge accumulated in BOX reaches to a certain degree, because source, leakage both ends are isolated, leak channel does not become yet, so as to effectively prevent backgate electric leakage；Source, the P+ for leaking both ends not only effectively inhibit the floater effect of PD SOI device, and also reduce the body contact resistance of device as body extraction.
Description
Technical field
The invention belongs to semiconductor devices research field, relates generally to a kind of semiconductcor field effect with three-stage oxygen buried layer
Answer transistor and its manufacture method.
Background technology
Silicon on insulator（SOI, Silicon on Insulator) it is a kind of treated special silicon chip, it is tied
Structure is mainly characterized by the buried insulating layer between substrate layer and active layer（Usually SiO2）Come separate active layer and substrate it
Between electrical connection.This design feature for silicon-on-insulator device bring ghost effect is small, speed is fast, it is low in energy consumption and collection
Into spend it is high the advantages of.Because SOI is a kind of Fully dielectric isolation technology, it can reduce the parasitic transistor between device.Therefore,
SOI MOSFET (MOS memory) are a kind of critically important devices, but because the backgate of SOI device is imitated
Should, the phenomenon of threshold voltage shift and leakage current increase occurs in SOI device.
As shown in figure 1, in traditional SOI MOSFET structure, work as oxygen buried layer（BOX, buried oxide）The positive electricity of middle accumulation
When lotus reaches to a certain degree so as to produce larger voltage, inversion channel can be formed in oxygen buried layer and body contact position.Due to
Source, leakage both ends and oxygen buried layer contact, can thus form leak channel, cause the unlatching of device, so as to influence the performance of circuit.
In current existing technology, can solve SOI MOSFET's by representative of the BUSFET of Sandia National Laboratories
Leaky.But as shown in Fig. 2 BUSFET unsymmetric structure brings inconvenience to circuit design.
The content of the invention
The present invention is in order to solve the above technical problems, provide a kind of semiconductor field effect transistor with three-stage oxygen buried layer
Pipe and its manufacture method, the transistor arrangement is symmetrical, can effectively solve the three-part SOI field effect transistors of backgate electric leakage
Pipe and its manufacture method.Symmetrical configuration, the three-part SOI field-effect transistors of backgate leakproof not only reduce circuit
Power consumption, and very big convenience is brought to circuit design.
Technical scheme is as follows：
Semiconductor field effect transistor with three-stage oxygen buried layer, it is characterised in that：It is the silicon as supporting layer including bottom
Bottom（1）And oxygen buried layer（2）；The silicon bottom（1）Upper surface among have a groove, in groove growth have one section of oxygen buried layer
（2）, the silicon bottom in groove both sides（1）Upper surface also respectively growth have oxygen buried layer（2）, three sections of oxygen buried layers altogether（2）；It is located at
Oxygen buried layer in groove（2）Upper is silicon top layer, positioned at silicon bottom（1）The another two sections of oxygen buried layers in upper surface（2）Above growth have P
+ layer（3）, P+ layers（3）Upper end is respectively source electrode（4）And drain electrode（5）.
The preparation method of above-mentioned transistor arrangement is as follows：
（a）Prepare the wafer of an ordinary silicon, the silicon on upper strata is etched away using photoetching technique；
（b）Utilize mask plate, the centre position of silicon chip（Lower section at following body）Etch a groove；
（c）In step（b）Layer of oxide layer is grown in the structure of gained so that is given birth to respectively with silicon chip upper surface in the groove of silicon chip
With oxide layer, the oxide layer is as oxygen buried layer（BOX layer, Buried Oxide）；
（d）Then epitaxial growth is carried out in oxide layer, by controlling growth time Si pieces is become a new wafer；
（e）In step（d）On the basis of resulting structures, ion implanting is carried out；
The ion implanting is divided into twice：For the first time, the ion energy of injection is high, time length, so that P+ is formed on source and drain bottom
Area；Secondary ion implanting is injected for normal source-drain area, so as to form source-drain area.The ion that injects twice is identical, with
Do not introduce premised on other impurities ion.The ion concentration of injection is greater than 1 ~ 2 number of active area ion concentration for the first time simultaneously
Magnitude, so as to form P+ regions.
（f）Finally, in step（e）Grid oxygen is grown on the basis of resulting structures and makes grid, so as to form three-
The structure of part SOI field-effect transistors.
Effective effect of the present invention is as follows：
For the present invention compared with traditional SOI device architecture, the oxygen buried layer of formation uses three stage structure, the BOX wherein below body
It is separated with BOX at source and drain both ends, while active area and substrate are isolated by this three sections of BOX again.Compared with traditional SOI technique,
BOX at body of the present invention will be more recently from a distance from substrate bottom.P+ layers are added at source and drain both ends simultaneously, so that source
Leakage both ends isolate with BOX.Based on said structure, even if the positive charge accumulated in BOX reaches to a certain degree, due to source and drain both ends quilt
Isolation, leak channel do not become yet, so as to effectively prevent backgate electric leakage.The P+ at source and drain both ends is drawn as body, is not only had
Effect inhibits the floater effect of PD SOI device, and also reduces the body contact resistance of device.Tied with BUSFET
Structure is compared, because the present invention has obvious symmetry in structure.This symmetrical structure brings very big to circuit design
It is convenient.Also without new parasitic transistor is introduced, the performance of the transistor greatly improves the present invention simultaneously.In addition, the present invention from
The angle of technique elaborates how to manufacture three-part SOI transistors.
Brief description of the drawings
Fig. 1 is the structural representation of traditional SOI MOSFET elements.
Fig. 2 is the SOI MOSFET element structural representations of existing BUSFET unsymmetric structures.
Fig. 3 is the structural representation of the present invention.
Fig. 4 is the structural representation of common SOI wafer in the present invention.
Fig. 5 is the structural representation that groove is etched in Fig. 4 structure.
Fig. 6 is the structural representation to growing three sections of oxide layers in Fig. 5 structure.
Fig. 7 is the rear structural representation for forming new wafer on Fig. 6 architecture basics.
Fig. 8 is the structural representation of three-part SOI field-effect transistors after being formed on Fig. 7 architecture basics.
In above-mentioned accompanying drawing, reference is：1- silicon bottoms, 2- oxygen buried layers, 3- P+ layers, 4- source electrodes, 5- drain electrodes.
Embodiment
In order that present disclosure is more clear and understandable, present disclosure is retouched in detail below in conjunction with the accompanying drawings
State.
As shown in figure 3, the semiconductor field effect transistor with three-stage oxygen buried layer, including bottom are as supporting layer
Silicon bottom 1 and oxygen buried layer 2；There is a groove among the upper surface of the silicon bottom 1, being grown in groove has one section of oxygen buried layer 2,
Also growth has oxygen buried layer 2 respectively for the upper surface of the silicon bottom 1 of groove both sides, altogether three sections of oxygen buried layers 2；Oxygen is buried in groove
It is silicon top layer on layer 2, positioned at silicon bottom（1）The another two sections of oxygen buried layers 2 in upper surface above growth have P+ layers（5）, the upper end of P+ layers 3
Respectively source electrode 4 and drain electrode 5.
The preparation method of above-mentioned transistor arrangement is as follows：
（a）As shown in figure 4, preparing the wafer of an ordinary silicon, the silicon on upper strata is etched away using photoetching technique；
（b）As shown in figure 5, utilize mask plate, the centre position of silicon chip（Lower section at following body）Etch a groove；
（c）As shown in fig. 6, in step（b）Layer of oxide layer is grown in the structure of gained so that in the groove of silicon chip and on silicon chip
Surface grows respectively oxide layer, and the oxide layer is as oxygen buried layer 2（BOX layer, Buried Oxide）；
（d）As shown in fig. 7, epitaxial growth is then carried out on oxygen buried layer 2, by controlling growth time Si pieces is become one newly
Wafer；
（e）As shown in figure 8, in step（d）On the basis of resulting structures, ion implanting is carried out；
The ion implanting is divided into twice：For the first time, the ion energy of injection is high, time length, so that P+ is formed on source and drain bottom
Area；Secondary ion implanting is injected for normal source-drain area, so as to form source-drain area.The ion that injects twice is identical, with
Do not introduce premised on other impurities ion.The ion concentration of injection is greater than 1 ~ 2 number of active area ion concentration for the first time simultaneously
Magnitude, so as to form P+ regions.
（f）Finally, in step（e）Grid oxygen is grown on the basis of resulting structures and makes grid, so as to be formed as shown in Figure 3
Three-part SOI field-effect transistors structure.
The present invention is got up active area and substrate isolation by three-stage oxygen buried layer.Heavy doping shape is done in source-drain area bottom
Adult connects.The structure forms body connection for N-type SOI transistor using p-type heavy doping；Used for p-type SOI transistor
N-type heavy doping forms body connection.P+ layers and the BOX at source and drain both ends have blocked the formation of leak channel, while P+ layers draw as body
Go out to effectively reduce the floater effect of PD SOI device.The present invention successfully solve traditional SOI device backgate electric leakage and
The asymmetry problem of BUSFET devices.
It should be noted that the present invention has carried out the elaboration explanation of correlation by taking three-part SOI NMOS as an example, should
Invention is equally applicable to three-part SOI PMOS making.
Claims (5)
1. the semiconductor field effect transistor with three-stage oxygen buried layer, it is characterised in that：It is as supporting layer including bottom
Silicon bottom（1）And oxygen buried layer（2）；The silicon bottom（1）Upper surface among have a groove, in groove growth there is one section to bury oxygen
Layer（2）, the silicon bottom in groove both sides（1）Upper surface also respectively growth have oxygen buried layer（2）, three sections of oxygen buried layers altogether（2）；Position
In the oxygen buried layer in groove（2）Upper is silicon top layer, positioned at silicon bottom（1）The another two sections of oxygen buried layers in upper surface（2）Above grow
There are P+ layers（3）, P+ layers（3）Upper end is respectively source electrode（4）And drain electrode（5）.
2. the method for transistor described in manufacturing claims 1, it is characterised in that step is as follows：
（a）Prepare the wafer of an ordinary silicon, the silicon on upper strata is etched away using photoetching technique；
（b）Using mask plate, the centre position of silicon chip etches a groove；
（c）In step（b）Layer of oxide layer is grown in the structure of gained so that is given birth to respectively with silicon chip upper surface in the groove of silicon chip
With oxide layer, the oxide layer is as oxygen buried layer；
（d）Then epitaxial growth is carried out in oxide layer, by controlling growth time Si pieces is become a new wafer；
（e）In step（d）On the basis of resulting structures, ion implanting is carried out, sequentially forms P+ areas and source-drain area；
（f）Finally, in step（e）Grid oxygen is grown on the basis of resulting structures and makes grid, so as to form three-part
SOI field-effect transistors.
3. manufacture method according to claim 2, it is characterised in that：The ion implanting is divided into twice：Inject for the first time
Source and drain bottom is set to form P+ areas, secondary ion implanting is injected for source-drain area, so as to form source-drain area；The first time injection
Ion energy than second of injection is high, time length.
4. manufacture method according to claim 3, it is characterised in that：The ion that injects twice is identical.
5. the manufacture method according to claim 3 or 4, it is characterised in that：The ion concentration of the first time injection is more than
1 ~ 2 order of magnitude of active area ion concentration, so as to form P+ regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710861809.7A CN107634101A (en) | 2017-09-21 | 2017-09-21 | Semiconductor field effect transistor and its manufacture method with three-stage oxygen buried layer |
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| CN201710861809.7A CN107634101A (en) | 2017-09-21 | 2017-09-21 | Semiconductor field effect transistor and its manufacture method with three-stage oxygen buried layer |
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Citations (10)
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|---|---|---|---|---|
| WO1993020587A1 (en) * | 1992-03-30 | 1993-10-14 | Honeywell Inc. | Mos structure for reducing snapback |
| JPH0974189A (en) * | 1995-09-06 | 1997-03-18 | Sharp Corp | Manufacture of semiconductor device |
| JP2001015751A (en) * | 1999-07-02 | 2001-01-19 | Telecommunication Advancement Organization Of Japan | Field effect transistor |
| CN1431717A (en) * | 2003-02-14 | 2003-07-23 | 中国科学院上海微系统与信息技术研究所 | Structure for lowering series resistor between source and drain in silicon transistors on insulator as well as implement method |
| CN1516903A (en) * | 2001-06-06 | 2004-07-28 | �Ҵ���˾ | SOI device with reduced junction capacitance |
| CN1623226A (en) * | 2002-03-28 | 2005-06-01 | 先进微装置公司 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same |
| US20090242936A1 (en) * | 2008-03-28 | 2009-10-01 | International Business Machines Corporation | Strained ultra-thin soi transistor formed by replacement gate |
| CN102208448A (en) * | 2011-05-24 | 2011-10-05 | 西安电子科技大学 | Polycrystalline Si1-xGex/metal parallel covering double-gate strained SiGe-on-insulator (SSGOI) n metal oxide semiconductor field effect transistor (MOSFET) device structure |
| CN103094177A (en) * | 2011-11-08 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Silicon on insulator (SOI), metal oxide semiconductor (MOS) part based on SOI and manufacturing method thereof |
| CN207425863U (en) * | 2017-09-21 | 2018-05-29 | 中国工程物理研究院电子工程研究所 | Semiconductor field effect transistor with three-stage oxygen buried layer |
-
2017
- 2017-09-21 CN CN201710861809.7A patent/CN107634101A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993020587A1 (en) * | 1992-03-30 | 1993-10-14 | Honeywell Inc. | Mos structure for reducing snapback |
| JPH0974189A (en) * | 1995-09-06 | 1997-03-18 | Sharp Corp | Manufacture of semiconductor device |
| JP2001015751A (en) * | 1999-07-02 | 2001-01-19 | Telecommunication Advancement Organization Of Japan | Field effect transistor |
| CN1516903A (en) * | 2001-06-06 | 2004-07-28 | �Ҵ���˾ | SOI device with reduced junction capacitance |
| CN1623226A (en) * | 2002-03-28 | 2005-06-01 | 先进微装置公司 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same |
| CN1431717A (en) * | 2003-02-14 | 2003-07-23 | 中国科学院上海微系统与信息技术研究所 | Structure for lowering series resistor between source and drain in silicon transistors on insulator as well as implement method |
| US20090242936A1 (en) * | 2008-03-28 | 2009-10-01 | International Business Machines Corporation | Strained ultra-thin soi transistor formed by replacement gate |
| CN102208448A (en) * | 2011-05-24 | 2011-10-05 | 西安电子科技大学 | Polycrystalline Si1-xGex/metal parallel covering double-gate strained SiGe-on-insulator (SSGOI) n metal oxide semiconductor field effect transistor (MOSFET) device structure |
| CN103094177A (en) * | 2011-11-08 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Silicon on insulator (SOI), metal oxide semiconductor (MOS) part based on SOI and manufacturing method thereof |
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Non-Patent Citations (1)
| Title |
|---|
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