CN107425064A - Bilateral wall VDMOS device and preparation method thereof - Google Patents
Bilateral wall VDMOS device and preparation method thereof Download PDFInfo
- Publication number
- CN107425064A CN107425064A CN201610346477.4A CN201610346477A CN107425064A CN 107425064 A CN107425064 A CN 107425064A CN 201610346477 A CN201610346477 A CN 201610346477A CN 107425064 A CN107425064 A CN 107425064A
- Authority
- CN
- China
- Prior art keywords
- layer
- wall
- dielectrically separated
- grid
- gate insulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002146 bilateral effect Effects 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000012774 insulation material Substances 0.000 claims abstract description 43
- 238000009413 insulation Methods 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000001312 dry etching Methods 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 60
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000002210 silicon-based material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a kind of bilateral wall VDMOS device and preparation method thereof, this method includes：N epitaxial layers are formed on N+ substrates；The first gate insulation layer, grid layer and the second gate insulation layer are sequentially formed on N epitaxial layers；P ions and N+ ions are injected in source region on N epitaxial layers；Form the covering grid layer side wall is dielectrically separated from wall；Insulation material layer is formed foring to be dielectrically separated from the structure of wall；Wherein, the insulation material layer formed from described to be dielectrically separated from walling matter different；Dry etching is carried out to the N epitaxial layers for exposing source region to the insulation material layer of formation；Wherein, the gas employed in dry etching is not suitable for being dielectrically separated from wall described in etching；Metal level is formed on structure after etching.It in the present invention, due to being dielectrically separated from the buffer action of wall, can be good at avoiding the side wall of grid layer to expose, can effectively reduce the risk that the source electrode of subsequent process formation directly contacts with grid.
Description
Technical field
Technical field of semiconductors of the present invention, more particularly to a kind of bilateral wall VDMOS device and its system
Make method.
Background technology
Vertical double diffused metal-oxide semi conductor transistor (VDMOS) has bipolar transistor concurrently
Pipe and the advantages of common MOS device, no matter switch application or linear applications, VDMOS
All it is preferable power device.VDMOS is mainly used in electric machine speed regulation, inverter, uninterrupted
Power supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc..VDMOS points
For enhanced VDMOS and depletion type VDMOS.
With the development of semiconductor design arts and field of semiconductor technology, current VDMOS
Device towards low cost, develop by high-performance field, how under the premise of high-performance is ensured,
Cost squeeze as far as possible, turn into the major subjects of each Chevron Research Company (CRC) and foundries.Device
Production cost be typically to be adjusted according to photoetching number, therefore, with the development of technology field,
The photoetching number during device production is reduced as far as possible, turns into current mainstream scheme.
Referring to Fig. 1, a kind of current signal of the preparation method of bilateral wall VDMOS device is shown
Figure, this method include：
1, form N+ types substrate on the base 1 first and form N- epitaxial layer；Afterwards by
The first grid insulation material layer 2 and polysilicon material layer 3 of traditional handicraft growth of device, obtain Fig. 1
Shown structure.Usual first grid insulation material layer 2 can be given birth to by the way of thermal oxide is used
Length, also known as grid oxygen.
2, do the oxidation of the polycrystalline silicon material at the top of polysilicon material layer 3, oxidized polycrystalline
Silicon materials 3 form second gate insulation material layer 4, and obtained structure is referring to Fig. 2.
3, photoresist 5 is coated on second gate insulation material layer 4 and is patterned, reserved bit
Structure as shown in Figure 3 is obtained in the photoresist 5 of area of grid；
4th, with photoresist 5 be mask to first grid insulation material layer 2, the and of polysilicon material layer 3
Second gate insulation material layer 4 is once etched, and only retains the first gate insulation in area of grid
Material layer 2 as the first gate insulation layer (for convenience of explanation, also be indicated as 2), retain grid
Polysilicon material layer 3 in region as grid layer (for convenience of explanation, also be indicated as 3) and
The second gate insulation material layer 4 retained in area of grid is used as the second gate insulation layer (for convenience
Illustrate, also be indicated as 4), remove photoresist to obtain the structure shown in Fig. 4 afterwards.
5, complete the P- bodies area autoregistration injection of device and drive in, N+ source regions autoregistration injection,
Obtain structure as shown in Figure 5.
6, LPTEOS spacer deposits are done, using LPCVD modes, deposit one layer of TEOS
(SiO2, it is expressed as 6), obtaining structure as shown in Figure 6 in figure.
7, LPTEOS etchings are done, full wafer is etched, and the TEOS6 of polycrystalline side wall can be protected after etching
Stay, obtain structure as shown in Figure 7.
8, autoregistration silicon hole etching is done, and complete metal 7 and connect, obtain the structure shown in Fig. 8.
Wherein, in the 7th step, to ensure that the TEOS of area surface is etched totally,
A certain amount of over etch (cross and carve) must be then added, now due to the exhausted etch rate of layer 5 of second gate
(TEOS can be faster) inconsistent with TEOS etch rates, therefore positioned at the side wall of grid layer 3
TEOS can be etched away faster, and the worst situation can become as shown in Figure 9.Now grid layer
3 grids formed have leaked outside cruelly, after follow-up filling metal, will directly result in device gate
Pole and source short, component failure.
The content of the invention
It is an object of the present invention to provide a kind of bilateral wall VDMOS device and its making side
Method, to reduce the risk of grid and source short therein.
In a first aspect, the invention provides a kind of preparation method of bilateral wall VDMOS device,
Including：
N- epitaxial layers are formed on N+ substrates；
The first gate insulation layer, grid layer and the second gate insulation layer are sequentially formed on N- epitaxial layers；
Wherein, the first gate insulation layer, grid layer and the second gate insulation layer are stacked, and figure is identical；
P- ions and N+ ions are injected in source region on N- epitaxial layers；
Form the covering grid layer side wall is dielectrically separated from wall；
Insulation material layer is formed foring to be dielectrically separated from the structure of wall；Wherein, formed
Insulation material layer from described to be dielectrically separated from walling matter different；
Dry etching is carried out to the N- epitaxial layers for exposing source region to the insulation material layer of formation；Its
In, the gas employed in dry etching is not suitable for being dielectrically separated from wall described in etching；
Metal level is formed on structure after etching.
Further, it is described sequentially formed on N- epitaxial layers the first gate insulation layer, grid layer and
Second gate insulation layer, is specifically included：
First grid insulation material layer and polysilicon material layer are sequentially formed on N- epitaxial layers；
The polycrystalline silicon material at the top of the polysilicon material layer is aoxidized, obtained by aoxidizing
Second gate insulation material layer that rear polycrystalline silicon material is formed and by not oxidized polycrystalline silicon material
The gate material layers of composition；
To the first grid insulation material layer, the second gate insulation material layer and the grid material
The bed of material is patterned；Obtain by remaining gate insulation layer material in the first grid insulation material layer
Material forms the first gate insulation layer；The second gate insulation being made up of remaining second gate insulation material layer
Layer and the grid layer being made up of remaining gate material layers.
Further, the thickness of the polysilicon material layer formed is 3000 angstroms -10000 angstroms.
Further, the thickness of the polysilicon material layer formed is 6000 angstroms；
The polycrystalline silicon material at the top to the polysilicon material layer, which carries out oxidation, to be included：It is right
3000 angstroms of the polycrystalline silicon material at the top of polysilicon material layer is aoxidized.
Further, the wall that is dielectrically separated from for forming the covering grid layer side wall includes：
Formed on the structure for completing P- ions and N+ ion implantings and be dielectrically separated from the walling bed of material；
It is described that to be dielectrically separated from the walling bed of material different from the material of second gate insulation layer；
The walling bed of material progress dry etching that is dielectrically separated from is obtained being dielectrically separated from wall；Wherein,
Etching gas employed in dry etching are unsuitable for etching the second gate insulation layer.
Further, the material for being dielectrically separated from wall is silicon nitride.
Further, the thickness for being dielectrically separated from wall is 300-800 angstroms.
Further, the insulation material layer that is formed on the structure of wall is dielectrically separated from foring
Material is silica.
Further, the insulation material layer that is formed on the structure of wall is dielectrically separated from foring
Thickness is 3000 angstroms -4000 angstroms.
Second aspect, made the invention provides a kind of method using described in any of the above-described
Bilateral wall VDMOS device.
In the preparation method of bilateral wall VDMOS device provided by the invention, grid layer is being formed
Afterwards, the side wall for being dielectrically separated from wall covering grid layer is initially formed, uses different materials again afterwards
Material forms another insulating barrier being dielectrically separated from outside wall；Dry etching is being carried out to another insulating barrier
When, performed etching using the gas that wall is dielectrically separated from described in unsuitable etching.So due to insulation
The buffer action of divider wall, it can be good at avoiding the side wall of grid layer to expose, can effectively drop
The risk that the source electrode that low subsequent process is formed directly contacts with grid.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below
Simply introduce, show by making one to the required accompanying drawing used in embodiment or description of the prior art
It is general for this area and easy insight, drawings in the following description are some embodiments of the present invention
, on the premise of not paying creative work, can also be attached according to these for logical technical staff
Figure obtains other accompanying drawings.
Fig. 1-8 is a kind of preparation method of the bilateral wall VDMOS device provided in the prior art
Flow chart；
Fig. 9 is to utilize structure of the preparation method in the prior art through being likely to occur after the 7th technique
Schematic diagram；
Figure 10-Figure 14 is in the preparation method using bilateral wall VDMOS device provided by the invention
Partial process view.
Embodiment
, below will knot to make the purpose, technical scheme and advantage of the embodiment of the present invention clearer
Close the embodiment of the present invention in accompanying drawing, the technical scheme in the embodiment of the present invention is carried out it is clear,
It is fully described by, it is clear that described embodiment is part of the embodiment of the present invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not having
The every other embodiment obtained under the premise of creative work is made, belongs to protection of the present invention
Scope.
In the preparation method of bilateral wall VDMOS device provided by the invention, in injection P- ions
After N+ ions, be initially formed covering grid layer side wall is dielectrically separated from wall, and the isolation
The insulation material layer being covered on the second gate insulation layer formed in the material and subsequent process of wall；
The insulation material layer is different from the material for being dielectrically separated from wall, and subsequently the insulation material layer is being carried out
During etching, the etching gas for being dielectrically separated from wall from unsuitable etching perform etching.Thus can
It is enough avoid being dielectrically separated from wall well be etched, can so as to avoid the side wall of grid layer from exposing
Effectively reduce the risk that the source electrode that subsequent process is formed directly contacts with grid.
Accompanying drawings below is described in detail.The method that one embodiment of the invention provides includes：
1, form N+ types substrate on the base 1 first and form N- epitaxial layer；Afterwards by
The first grid insulation material layer 2 and polysilicon material layer 3 of traditional handicraft growth of device, obtain Fig. 1
Shown structure.Usual first grid insulation material layer 2 can be given birth to by the way of thermal oxide is used
Length, also known as grid oxygen.The thickness of polysilicon material layer 3 is usually 3000 angstroms -10000 angstroms, preferably
For 6000 angstroms.
2, do the oxidation of the polycrystalline silicon material at the top of polysilicon material layer 3, oxidized polycrystalline
Silicon materials 3 form second gate insulation material layer 4, and obtained structure is referring to Fig. 2.Preferably, it is more
3000 angstroms of the material at the top of crystal silicon material 3 is oxidized.
3, photoresist 5 is coated on second gate insulation material layer 4 and is patterned, reserved bit
Structure as shown in Figure 3 is obtained in the photoresist 5 of area of grid；
4th, with photoresist 5 be mask to first grid insulation material layer 2, the and of polysilicon material layer 3
Second gate insulation material layer 4 performs etching, and only retains the first gate insulation in area of grid
Layer 2, polysilicon material layer 3 and second gate insulation material layer 4, as the first gate insulation layer 2,
The gate insulation layer 4 of grid layer 3 and second, removes photoresist to obtain the structure shown in Fig. 4 afterwards.
5, complete the P- bodies area autoregistration injection of device and drive in, N+ source regions autoregistration injection,
Obtain structure as shown in Figure 5.
6th, formed on the structure for completing P- ions and N+ ion implantings and be dielectrically separated from walling material
Layer 8；The structure obtained after this step may refer to Figure 10；
In this step, it can be used as by LPCVD mode deposited silicon nitrides and be dielectrically separated from walling material
Layer 8；Its thickness can be between 300-800 angstroms.
7th, do silicon nitride material 8 to etch, etch away the first gate insulation layer 2, the and of grid layer 3
Silicon nitride material outside the silicon nitride covered in the side wall of second gate insulation layer 4, formed exhausted
Edge divider wall 8, the structure obtained after this step may be referred to Figure 11；
Because the second gate insulation layer 4 of the upper surface of grid 3 is the oxygen that is obtained by polysilicon oxidation
SiClx layer；It can use and be suitable to perform etching silicon nitride material and be unsuitable for entering silicon oxide layer
The gas of row etching carries out dry etching to silicon nitride material and obtains silicon nitride spacer 8, such quarter
Erosion process can be good at avoiding the second gate insulation layer 4 from being damaged.
8th, LPTEOS spacer deposits are done, using LPCVD modes, deposit one layer of TEOS
(SiO2, it is expressed as 6), obtaining structure as shown in figure 12 in figure.
9th, LPTEOS etchings are done, full wafer is etched, and the TEOS6 of polycrystalline side wall can be protected after etching
Stay, obtain structure as shown in fig. 13 that.
10th, autoregistration silicon hole etching is done, and completes metal 7 and connects, obtains the knot shown in Figure 14
Structure.
So far, the making of bilateral wall VDMOS device is completed, due to being dielectrically separated from wall 8
Buffer action, the side wall of grid layer 3 can be avoided to expose, can effectively reduce subsequent process shape
Into the risk that is directly contacted with grid layer 3 of metal source.
Second aspect, present invention also offers a kind of bilateral wall VDMOS device, the VDMOS
Device is the VDMOS made by the preparation method using above-mentioned bilateral wall VDMOS device
Device.
Understandable to be, what is shown in above-mentioned each accompanying drawing is dielectrically separated from wall and can also pass through
Other modes are made, and grid layer side wall is covered and selected material can reach
So that subsequently to formed thereon insulation material layer etching during this be dielectrically separated from wall will not be light
In the case of being easily etched, corresponding technical scheme should fall into protection scope of the present invention.
It should be noted that the present invention will be described rather than the present invention is carried out for above-described embodiment
Limitation, and those skilled in the art without departing from the scope of the appended claims may be used
Design alternative embodiment.In the claims, should not be by any reference between bracket
Symbol construction is into limitations on claims.Word "comprising", which does not exclude the presence of, is not listed in right
Element or step in it is required that.Word "a" or "an" before element is not excluded for
Multiple such elements be present.The present invention can be by means of including the hardware of some different elements
And realized by means of properly programmed computer.If listing the unit right of equipment for drying
In it is required that, several in these devices can be embodied by same hardware branch.
The use of word first, second, and third does not indicate that any order.Can be by these words
It is construed to title.
Claims (10)
- A kind of 1. preparation method of bilateral wall VDMOS device, it is characterised in that including：N- epitaxial layers are formed on N+ substrates；The first gate insulation layer, grid layer and the second gate insulation layer are sequentially formed on N- epitaxial layers； Wherein, the first gate insulation layer, grid layer and the second gate insulation layer are stacked, and figure is identical；P- ions and N+ ions are injected in source region on N- epitaxial layers；Form the covering grid layer side wall is dielectrically separated from wall；Insulation material layer is formed foring to be dielectrically separated from the structure of wall；Wherein, formed Insulation material layer from described to be dielectrically separated from walling matter different；Dry etching is carried out to the N- epitaxial layers for exposing source region to the insulation material layer of formation；Its In, the gas employed in dry etching is not suitable for being dielectrically separated from wall described in etching；Metal level is formed on structure after etching.
- 2. according to the method for claim 1, it is characterised in that described on N- epitaxial layers The first gate insulation layer, grid layer and the second gate insulation layer are sequentially formed, is specifically included：First grid insulation material layer and polysilicon material layer are sequentially formed on N- epitaxial layers；The polycrystalline silicon material at the top of the polysilicon material layer is aoxidized, obtained by aoxidizing Second gate insulation material layer that rear polycrystalline silicon material is formed and by not oxidized polycrystalline silicon material The gate material layers of composition；To the first grid insulation material layer, the second gate insulation material layer and the grid material The bed of material is patterned；Obtain by remaining gate insulation layer material in the first grid insulation material layer Material forms the first gate insulation layer；The second gate insulation being made up of remaining second gate insulation material layer Layer and the grid layer being made up of remaining gate material layers.
- 3. according to the method for claim 2, it is characterised in that the polysilicon material formed The thickness of the bed of material is 3000 angstroms -10000 angstroms.
- 4. according to the method for claim 3, it is characterised in that the polysilicon material formed The thickness of the bed of material is 6000 angstroms；The polycrystalline silicon material at the top to the polysilicon material layer, which carries out oxidation, to be included：It is right 3000 angstroms of the polycrystalline silicon material at the top of polysilicon material layer is aoxidized.
- 5. according to the method for claim 1, it is characterised in that described to be formed described in covering The wall that is dielectrically separated from of grid layer side wall includes：Formed on the structure for completing P- ions and N+ ion implantings and be dielectrically separated from the walling bed of material； It is described that to be dielectrically separated from the walling bed of material different from the material of second gate insulation layer；The walling bed of material progress dry etching that is dielectrically separated from is obtained being dielectrically separated from wall；Wherein, Etching gas employed in dry etching are unsuitable for etching the second gate insulation layer.
- 6. according to the method for claim 1, it is characterised in that the wall of being dielectrically separated from Material is silicon nitride.
- 7. the method according to claim 1 or 6, it is characterised in that described to be dielectrically separated from The thickness of wall is 300-800 angstroms.
- 8. according to the method for claim 1, it is characterised in that be dielectrically separated from foring The material of the insulation material layer formed on the structure of wall is silica.
- 9. according to the method for claim 8, it is characterised in that be dielectrically separated from foring The thickness of the insulation material layer formed on the structure of wall is 3000 angstroms -4000 angstroms.
- A kind of 10. bilateral wall that method using as described in claim any one of 1-9 makes VDMOS device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610346477.4A CN107425064A (en) | 2016-05-23 | 2016-05-23 | Bilateral wall VDMOS device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610346477.4A CN107425064A (en) | 2016-05-23 | 2016-05-23 | Bilateral wall VDMOS device and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107425064A true CN107425064A (en) | 2017-12-01 |
Family
ID=60422271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610346477.4A Pending CN107425064A (en) | 2016-05-23 | 2016-05-23 | Bilateral wall VDMOS device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107425064A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5462896A (en) * | 1991-06-24 | 1995-10-31 | Nippondenso Co., Ltd. | Method of forming a sidewall on a semiconductor element |
| US20060131646A1 (en) * | 2004-12-20 | 2006-06-22 | Silicon-Based Technology Corp. | Scalable planar DMOS transistor structure and its fabricating methods |
| CN204424260U (en) * | 2015-01-30 | 2015-06-24 | 苏州同冠微电子有限公司 | Anti-creeping power device |
-
2016
- 2016-05-23 CN CN201610346477.4A patent/CN107425064A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5462896A (en) * | 1991-06-24 | 1995-10-31 | Nippondenso Co., Ltd. | Method of forming a sidewall on a semiconductor element |
| US20060131646A1 (en) * | 2004-12-20 | 2006-06-22 | Silicon-Based Technology Corp. | Scalable planar DMOS transistor structure and its fabricating methods |
| CN204424260U (en) * | 2015-01-30 | 2015-06-24 | 苏州同冠微电子有限公司 | Anti-creeping power device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5091487B2 (en) | Manufacturing method of semiconductor device | |
| TWI518755B (en) | An integrated circuit structure (ic) and method of making the same | |
| TW202105729A (en) | Shield gate mosfet and method for fabricating the same | |
| CN106653831A (en) | High density low voltage trench power MOS device and method of manufacturing same | |
| CN106129063B (en) | Thin-film transistor array base-plate and its manufacturing method | |
| CN102945832B (en) | The forming method of flush memory device | |
| CN105070663B (en) | Silicon carbide MOSFET channel self-alignment process implementation method | |
| CN106952865A (en) | Semiconductor structure and forming method thereof | |
| JP2008016808A (en) | Method of manufacturing flash memory device | |
| CN105990332A (en) | Thin film transistor substrate and display panel thereof | |
| CN102881693B (en) | Storage device and manufacturing method thereof | |
| CN107425064A (en) | Bilateral wall VDMOS device and preparation method thereof | |
| CN105448981A (en) | VDMOS device, drain electrode structure thereof, and manufacturing method | |
| CN110047848B (en) | Array substrate and preparation method thereof | |
| CN106033731A (en) | Semiconductor element and manufacture method for the same | |
| CN101211785B (en) | Method for manufacturing trench gate type MOSFET device | |
| CN107464836A (en) | The preparation method and top gate type thin film transistor of a kind of top gate type thin film transistor | |
| JP2013048161A (en) | Semiconductor device manufacturing method | |
| CN108962748A (en) | The forming method and its structure of IGBT device | |
| KR100804155B1 (en) | Method for manufacturing of semiconductor device | |
| KR100975974B1 (en) | Method for reducing bird's beak of floating gate in eeprom | |
| CN107359121A (en) | The preparation method and VDMOS power devices of VDMOS power devices | |
| KR100800131B1 (en) | Method for fabricating semiconductor device | |
| CN105161457B (en) | The preparation method of semiconductor substrate | |
| TW523882B (en) | Flash memory manufacturing method can increase coupling ratio |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171201 |