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CN107406335A - 陶瓷基板、层叠体和saw器件 - Google Patents

陶瓷基板、层叠体和saw器件 Download PDF

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Publication number
CN107406335A
CN107406335A CN201680001823.3A CN201680001823A CN107406335A CN 107406335 A CN107406335 A CN 107406335A CN 201680001823 A CN201680001823 A CN 201680001823A CN 107406335 A CN107406335 A CN 107406335A
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China
Prior art keywords
interarea
substrate
support
ceramic substrate
layered product
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Granted
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CN201680001823.3A
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CN107406335B (zh
Inventor
下司庆郎
下司庆一郎
中山茂
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/25—Constructional features of resonators using surface acoustic waves
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    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B18/00—Layered products essentially comprising ceramics, e.g. refractory products
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B3/02—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by features of form at particular places, e.g. in edge regions
    • B32B3/08—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by features of form at particular places, e.g. in edge regions characterised by added members at particular parts
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    • B32B3/26—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
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Abstract

陶瓷基板由多晶陶瓷形成并具有支撑主面。所述支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度。在所述支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。

Description

陶瓷基板、层叠体和SAW器件
技术领域
本发明涉及陶瓷基板、层叠体和SAW器件。更具体地，本发明涉及适合于支撑压电基板的陶瓷基板，包含所述压电基板和所述陶瓷基板的层叠体，和包含所述层叠体的SAW器件。
背景技术
SAW器件(声表面波器件)安装在通信设备如便携式电话中，以除去电信号中包含的噪音。SAW器件具有只提取输入电信号之中具有期望频率的电信号的功能。SAW器件具有在压电基板上形成有电极的结构。为了在工作时散热，将压电基板配置在由散热性质良好的材料制成的底部基板(ベース基板)上。
例如，可以将由单晶蓝宝石制成的基板用作底部基板。然而，如果将这样的由单晶蓝宝石制成的基板用作底部基板，则SAW器件的制造成本上升。为了解决这个问题，已经提出了具有下述结构的SAW器件：由多晶尖晶石制成的陶瓷基板被用作底部基板，并且压电基板和降低了表面粗糙度Ra(算术平均粗糙度)的陶瓷基板通过范德华力互相结合。由此，可以降低SAW器件的制造成本(例如，参考专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2011-66818号公报
发明内容
本公开的陶瓷基板由多晶陶瓷形成并具有支撑主面。支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度。在支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。
附图说明
[图1]图1为显示包含陶瓷基板和压电基板的层叠体的结构的截面示意图。
[图2]图2为示意性显示陶瓷基板、层叠体和SAW器件的制造方法的流程图。
[图3]图3为用于说明陶瓷基板、层叠体和SAW器件的制造方法的截面示意图。
[图4]图4为用于说明层叠体和SAW器件的制造方法的截面示意图。
[图5]图5为用于说明层叠体和SAW器件的制造方法的截面示意图。
[图6]图6为用于说明层叠体和SAW器件的制造方法的示意图。
[图7]图7为显示SAW器件的结构的示意图。
具体实施方式
[本公开要解决的技术问题]
为了进一步降低SAW器件的制造成本，需要进一步增大压电基板与陶瓷基板之间的结合强度。因此，本公开的目的是提供可以以足够的结合强度与压电基板结合的陶瓷基板、包含以足够的结合强度互相结合的压电基板和陶瓷基板的层叠体、和包含所述层叠体的SAW器件。
[本公开的效果]
根据上述陶瓷基板，可以提供可以以足够的结合强度与压电基板结合的陶瓷基板。
[本公开的实施方式的说明]
首先，将列举并说明本发明的实施方式。本申请的陶瓷基板由多晶陶瓷形成并具有支撑主面。所述支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度。在所述支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。
本发明人对当压电基板和具有降低了的算术平均粗糙度的表面的陶瓷基板(底部基板)通过范德华力互相结合时有时发生结合强度不足的原因进行了研究。结果，他们发现，即使充分降低以算术平均粗糙度表示的粗糙度，在存在大的凹凸的情况下，例如在边长为50μm的正方形区域内高度为1nm以上的凹凸的数目为5个以上的情况下或者在边长为50μm的正方形区域内高度为2nm以上的凹凸的数目为1个以上的情况下，也达不到足够的结合强度。也就是说，为了获得足够的结合强度，不仅需要充分降低以算术平均粗糙度表示的(以平均粗糙度表示的)粗糙度，而且需要减少在如上所述的某些罕见情况下存在的大的凹凸的数目。
在本申请的陶瓷基板中，所述支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度，因此以算术平均粗糙度表示的表面粗糙度被充分降低。此外，在本申请的陶瓷基板中，在支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。也就是说，在本申请的陶瓷基板中，以算术平均粗糙度表示的支撑主面的粗糙度被充分降低，此外在某些罕见情况下在支撑主面上存在的大的凹凸的数目也被减少。因此，根据本申请的陶瓷基板，可以提供可以以足够的结合强度与压电基板结合的陶瓷基板。
在上述陶瓷基板中，支撑主面可以具有以Sq表示的0.5nm以下的粗糙度。这更为确定地在陶瓷基板与压电基板之间提供足够的结合强度。
上述陶瓷基板可以由选自由如下材料构成的组中的至少一种材料制成的多晶陶瓷形成：尖晶石(MgAl2O4)、氧化铝(Al2O3)、氧化镁(MgO)、二氧化硅(SiO2)、富铝红柱石(3Al2O3·2SiO2)、堇青石(2MgO·2Al2O3·5SiO2)、氧化钙(CaO)、二氧化钛(TiO2)、氮化硅(Si3N4)、氮化铝(AlN)、和碳化硅(SiC)。这些材料适合于本申请的陶瓷基板。
本申请的层叠体包含上述陶瓷基板和配置在支撑主面上并由压电体形成的压电基板。所述陶瓷基板和所述压电基板通过范德华力互相结合。
在本申请的层叠体中，其中以算术平均粗糙度表示的支撑主面的粗糙度被充分降低且此外在某些罕见情况下在支撑主面上存在的大的凹凸的数目也被减少的陶瓷基板和压电基板通过范德华力互相结合。因此，根据本申请的层叠体，可以提供包含以足够的结合强度互相结合的压电基板和陶瓷基板的层叠体。
在上述层叠体中，陶瓷基板与压电基板之间的结合强度可以为0.5J/m2以上。这样，压电基板和陶瓷基板更为确定地互相结合。如果压电基板与陶瓷基板之间的结合强度小于0.5J/m2，则例如在SAW器件的制造中所进行的电极形成步骤或芯片形成步骤中可能发生基板的剥离和裂纹(欠け)。为了使压电基板和陶瓷基板更为确定地互相结合，优选陶瓷基板与压电基板之间的结合强度为1.0J/m2以上，更优选为1.3J/m2以上，且进一步优选为1.5J/m2以上。
本申请的SAW器件包含上述本申请的层叠体和在压电基板的主面上形成的电极，所述主面位于所述陶瓷基板的相反侧。本申请的SAW器件包含本申请的层叠体，在本申请的层叠体中压电基板和由多晶陶瓷形成的陶瓷基板以足够的结合强度互相结合。因此，可以提供其中在制造成本被降低的同时、压电基板和陶瓷基板以足够的结合强度互相结合的SAW器件。
在此，粗糙度Sa、Sq和Sz分别是指符合ISO 25178的算术平均高度Sa、均方根高度Sq和最大高度Sz。这些表面粗糙度参数可以通过使用例如三维表面粗糙度测量仪进行测量。
[本发明的具体实施方式的详情]
接下来，将参照附图对本发明实施方式的陶瓷基板和层叠体进行说明。在这些图中，相同或相应的部分由相同的参考编号表示并省略对其的重复说明。
参照图1，本实施方式的层叠体1包含作为陶瓷基板的底部基板10和压电基板20。压电基板20由用例如钽酸锂(LiTaO3)或铌酸锂(LiNbO3)制成的压电体形成。底部基板10由用选自由尖晶石、氧化铝、氧化镁、二氧化硅、富铝红柱石、堇青石、氧化钙、二氧化钛、氮化硅、氮化铝和碳化硅构成的组中的至少一种制成的多晶陶瓷形成，并且优选由用前述材料中的一种制成的多晶陶瓷形成。
底部基板10具有支撑主面11。压电基板20具有露出主面21和位于露出主面21相反侧的结合主面22。压电基板20以使得结合主面22与支撑主面11接触的方式配置在底部基板10的支撑主面11上。底部基板10和压电基板20通过范德华力互相结合。
底部基板10的支撑主面11具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度。此外，在支撑主面11上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。
在层叠体1中，当支撑主面11具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度时，以算术平均粗糙度表示的表面粗糙度被充分降低。在层叠体1中，在支撑主面11上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。也就是说，在层叠体1中，以算术平均粗糙度表示的粗糙度被充分降低，此外在某些罕见情况下存在的大的凹凸的数目也被减少。因此，层叠体1为其中压电基板20和底部基板10以足够的结合强度互相结合的层叠体。
在本申请中，高度为1nm以上的凹凸是指从测定区域(边长为50μm的正方形区域)内算出的平均面(平均高度)到顶部(或底部)的距离为1nm以上的凹凸。同样地，高度为2nm以上的凹凸是指从测定区域(边长为50μm的正方形区域)内算出的平均面(平均高度)到顶部(或底部)的距离为2nm以上的凹凸。在支撑主面11上的多个测定区域(边长为50μm的正方形区域)内用显微镜等对凹凸的数目进行计数，将所述数目的平均值定义为平均凹凸数目。
为了更确定地在压电基板20与底部基板10之间获得足够的结合强度，优选将以Sa表示的支撑主面的粗糙度设定为2.0nm以下并且更优选为1.0nm以下。在支撑主面11上边长为50m的正方形区域内高度为1nm以上的凹凸的数目优选平均小于4个，更优选小于3个，且进一步优选小于2个。
优选支撑主面11具有以Sq表示的0.5nm以下的粗糙度。这更确定地在压电基板20与底部基板10之间获得足够的结合强度。
优选底部基板10与压电基板20之间的结合强度为0.5J/m2以上。由此，压电基板20和底部基板10更为确定地互相结合。
接下来，将对本实施方式的作为陶瓷基板的底部基板10、层叠体1、和包含所述层叠体1的SAW器件的制造方法进行说明。参照图2，在本实施方式的底部基板10、层叠体1和SAW器件的制造方法中，实施作为步骤(S10)的底部基板准备步骤。在步骤(S10)中，如在图3中所示，准备由用选自由尖晶石、氧化铝、氧化镁、二氧化硅、富铝红柱石、堇青石、氧化钙、二氧化钛、氮化硅、氮化铝和碳化硅构成的组中的至少一种材料制成的多晶陶瓷形成的底部基板10。例如，准备由用前述材料中的一种制成的多晶陶瓷形成的底部基板10。具体地，例如，当准备由多晶尖晶石形成的底部基板10时，通过混合氧化镁粉末和氧化铝粉末来准备原料粉末，并且通过对所述原料粉末进行成型制作成型体。所述成型体可以通过例如经由压制成型实施预成型，然后实施CIP(冷等静压制)来进行制作。随后，对所述成型体进行烧结处理。可以通过诸如真空烧结或HIP(热等静压制)的方法实施烧结处理。由此获得烧结体。然后将烧结体切割以获得具有期望形状(厚度)的底部基板10(参照图3)。
随后，实施作为步骤(S20)的第一研磨步骤。在步骤(S20)中，如图3中所示，在步骤(S10)中准备的底部基板10的支撑主面11上实施粗研磨。具体地，使用例如磨粒号为#800至#2000的GC(绿碳化硅)砂轮在支撑主面11上实施粗研磨。
随后，实施作为步骤(S30)的第二研磨步骤。在步骤(S30)中，在已经于步骤(S20)中实施过粗研磨的支撑主面11上实施通常研磨。具体地，使用例如磨粒的粒径为3μm至5μm的金刚石砂轮在支撑主面11上实施通常研磨。
随后，实施作为步骤(S40)的第三研磨步骤。在步骤(S40)中，在已经于步骤(S30)中实施过通常研磨的支撑主面11上实施精研磨。具体地，使用例如粒径为0.5μm至1.0μm的金刚石磨粒在支撑主面11上实施精研磨。这提供了具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度的支撑主面11。然而，因为金刚石磨粒的使用而在支撑主面11上形成划痕损伤。因此，在支撑主面11上，获得了以Sa表示的0.01nm以上且3.0nm以下的粗糙度，但存在由划痕损伤而造成的大的凹凸。
随后，实施作为步骤(S50)的第四研磨步骤。在步骤(S50)中，在已经于步骤(S40)中实施过精研磨的支撑主面11上实施划痕损伤去除研磨。具体地，例如以对支撑主面11进行轻微研磨的方式在支撑主面11上实施CMP(化学机械研磨)。支撑主面11被CMP研磨掉的厚度约为数百纳米。由此，可以在支撑主面11上维持以Sa表示的0.01nm以上且3.0nm以下的粗糙度。同时，可以将在支撑主面11上的边长为50μm的正方形区域内高度为1nm以上的凹凸的数目控制为平均小于5个，并且可以将在所述正方形区域内高度为2nm以上的凹凸的数目控制为平均小于1个。由此，完成了作为本实施方式的陶瓷基板的底部基板10。
随后，实施作为步骤(S60)的结合步骤。在步骤(S60)中，将已经于步骤(S20)至(S50)中对其支撑主面11实施过研磨的底部基板10和另行准备的压电基板20互相结合。具体地，如图3和图1中所示，准备由用例如钽酸锂或铌酸锂制成的压电体形成的压电基板20，并且以使得压电基板20的结合主面22与底部基板10的支撑主面11接触的方式将底部基板10和压电基板20互相结合。由此，底部基板10和压电基板20通过范德华力互相结合。由此，获得本实施方式的层叠体1。
在本实施方式中，以算术平均粗糙度表示的支撑主面11的粗糙度被充分降低，此外在某些罕见情况下在支撑主面11上存在的大的凹凸(划痕损伤)的数目也被减少。结果，根据层叠体1的制造方法，制造了其中压电基板20和底部基板10以足够的结合强度互相结合的层叠体1。
接下来，将对包含层叠体1的SAW器件的制造方法进行说明。参照图2，在步骤(S60)之后，实施作为步骤(S70)的减小厚度的步骤。在步骤(S70)中，如图1和图4中所示，在步骤(S60)中获得的层叠体1的压电基板20的厚度减小。具体地，例如对压电基板20的露出主面21进行磨削处理。由此，将压电基板20的厚度减小至适合于SAW器件的厚度。
随后，实施作为步骤(S80)的电极形成步骤。在步骤(S80)中，如图4至图6中所示，在压电基板20的露出主面21上形成梳齿型电极。图5为沿图6中的线V-V取的截面图。具体地，如图5和图6中所示，在已经于步骤(S70)中适当调节过厚度的压电基板20的露出主面21上形成由诸如Al的导体制成的导体膜。导体膜可以通过例如溅射法形成。然后在导体膜上涂布抗蚀剂以形成抗蚀膜。通过实施曝光和显影，在与输入侧电极30和输出侧电极40的期望形状对应的区域以外的区域中形成开口。例如，使用其中形成有开口的抗蚀膜作为掩模实施湿蚀刻，从而形成如图5和图6中所示的多对输入侧电极30和输出侧电极40。图5和图6显示了与一对输入侧电极30和输出侧电极40对应的区域。输入侧电极30和输出侧电极40中的梳齿型电极的电极间隔可以根据要输出的信号频率而适当决定。
随后，实施作为步骤(S90)的芯片形成步骤。在步骤(S90)中，将其上已经形成有多对输入侧电极30和输出侧电极40的层叠体1在厚度方向上切割成各自包含一对输入侧电极30和输出侧电极40的多个芯片。
然后，参照图6和图7，在步骤(S90)中制作的芯片上形成输入侧配线51和输出侧配线61从而完成第一实施方式的SAW器件100(SAW滤波器)。
参照图7，本实施方式的SAW器件100包含层叠体1、输入侧电极30和输出侧电极40、与输入侧电极30连接的输入侧配线51、和与输出侧电极40连接的输出侧配线61，所述层叠体1包含通过范德华力互相结合的底部基板10和压电基板20，所述输入侧电极30和输出侧电极40为以与压电基板20的露出主面21接触的方式形成的一对梳齿型电极。
输入侧电极30包含第一部分31和第二部分32。第一部分31包含直线状底部31A和以垂直于底部31A延伸方向的方向从底部31A突出的多个直线状突出部31B。第二部分32包含平行于底部31A延伸的直线状底部32A和以垂直于底部32A延伸方向的方向从底部32A突出并且进入相邻突出部31B之间的间隙中的多个直线状突出部32B。以预定的等间距间隔配置突出部31B和突出部32B。
输出侧电极40包含第一部分41和第二部分42。第一部分41包含直线状底部41A和以垂直于底部41A延伸方向的方向从底部41A突出的多个直线状突出部41B。第二部分42包含平行于底部41A延伸的直线状底部42A和以垂直于底部42A延伸方向的方向从底部42A突出并且进入相邻突出部41B之间的间隙中的多个直线状突出部42B。以预定的等间距间隔配置突出部41B和突出部42B。
当将作为输入信号的交流电压从输入侧配线51施加到输入侧电极30时，因为压电效应而在压电基板20的露出主面21(表面)上产生声表面波，并且所述声表面波传播到输出侧电极40。在此，输入侧电极30和输出侧电极40具有如图1中所示的梳齿形状，并且突出部31B和突出部32B被均匀隔开且突出部41B和突出部42B被均匀隔开。由此，在从输入侧电极30向输出侧电极40的方向上，在压电基板20的露出主面21上形成电极的区域以预定的周期(电极周期)存在。因此，当由输入信号产生的声表面波的波长与电极周期一致时该声表面波被最强激发，并且随着波长与电极周期之差增大而衰减。结果，只有波长接近电极周期的信号才通过输出侧电极40和输出侧配线61输出。
在上述工作中，压电基板20的温度上升。在本实施方式的SAW器件100中，以与由散热性质良好的材料制成的底部基板10接触的方式配置压电基板20。因此，SAW器件100具有高可靠性。此外，在本实施方式的SAW器件100中，压电基板20和底部基板10以足够的结合强度互相结合。因此，SAW器件100为高可靠性器件。
[实施例]
为了研究层叠体中底部基板的支撑主面的粗糙度以及在支撑主面上存在的凹凸的状态与结合强度之间的关系而进行了实验。通过以下方法进行了实验。
准备由多晶尖晶石形成的底部基板10，并通过与上述实施方式中同样的程序制作SAW器件(实施例A、B和C)。准备由多晶氧化铝形成的底部基板10和由多晶富铝红柱石形成的底部基板10，并以同样的方式制作SAW器件(实施例D和E)。为了比较，准备由多晶尖晶石形成的底部基板，并以除了省略步骤(S50)以外同样的方式制作SAW器件(比较例A至F)。准备由多晶氧化铝形成的底部基板，并以除了省略步骤(S50)以外同样的方式制作SAW器件(比较例G和H)。准备由多晶富铝红柱石形成的底部基板，并以除了省略步骤(S50)以外同样的方式制作SAW器件(比较例I和J)。与压电基板结合之前，测定底部基板的支撑主面的Sa(算术平均粗糙度)、Sq(均方根高度)和Sz(最大高度)。此外，确定在边长为50μm的正方形区域内高度为1nm以上且小于2nm的凹凸的数目、高度为2nm以上且小于3nm的凹凸的数目、和高度为3nm以上的凹凸的数目。确定在支撑主面的中央附近和外周附近的两个位置处的粗糙度和凹凸的数目。在结合后，确定结合状态并测定结合强度。通过裂纹张开法(クラックオープニング法)测定结合强度。表1显示了采用由多晶尖晶石形成的底部基板的实施例的实验结果。表2显示了采用由多晶尖晶石形成的底部基板的比较例的实验结果。表3显示了采用由多晶氧化铝形成的底部基板的实施例和比较例的实验结果。表4显示了采用由多晶富铝红柱石形成的底部基板的实施例和比较例的实验结果。在表1至4的最下列，当可以令人满意地实施电极形成步骤和芯片形成步骤时给出“良好”，而当在电极形成步骤和芯片形成步骤中在层叠体内发生剥离时给出“不良”。
[表1]
[表2]
[表3]
[表4]
参照表1，在实施例A至C中，获得了0.5J/m2以上的结合强度并且在整个主面上获得了良好的结合，所述实施例A至C中由多晶尖晶石形成的底部基板的支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度；在所述支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。参照表2，在比较例A至F中，底部基板的支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度，但结合强度低并且没有获得良好的结合状态。这可能是因为在比较例A至F中在边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均为5个以上，且在比较例A、D、E和F中在边长为50μm的正方形区域内高度为2nm以上的凹凸的数目平均为1个以上。
参照表3，在实施例D中，获得了0.5J/m2以上的结合强度并且在整个主面上获得了良好的结合，所述实施例D中由多晶氧化铝形成的底部基板的支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度；在所述支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。在比较例G和H中，底部基板的支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度，但结合强度低并且没有获得良好的结合状态。与上述由多晶尖晶石形成的底部基板的情况一样，这可能是因为在比较例G和H中在边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均为5个以上，且在比较例H中在边长为50μm的正方形区域内高度为2nm以上的凹凸的数目平均为1个以上。
参照表4，在实施例E中，获得了0.5J/m2以上的结合强度并且在整个主面上获得了良好的结合，所述实施例E中由多晶富铝红柱石形成的底部基板的支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度；在所述支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。在比较例I和J中，底部基板的支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度，但结合强度低并且没有获得良好的结合状态。与上述由多晶尖晶石形成的底部基板的情况一样，这可能是因为在比较例I和J中在边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均为5个以上，且在比较例J中在所述正方形区域内高度为2nm以上的凹凸的数目平均为1个以上。
从以上实验结果发现，根据本申请的层叠体，获得了包含以足够的结合强度互相结合的压电基板和底部基板的层叠体，本申请的层叠体中以算术平均粗糙度表示的支撑主面的粗糙度被充分降低且此外在某些罕见情况下在支撑主面上存在的大的凹凸的数目也被减少。
在此公开的实施方式和实施例在各个方面都仅仅是例示并且在任何角度上都应该被理解为是非限制性的。本发明的范围不是由上述说明而是由权利要求限定。本发明的范围旨在包括与权利要求书等价的含义和范围内的所有修改。
[标号说明]
1 层叠体
10 底部基板
100 SAW器件
11 支撑主面
20 压电基板
21 露出主面
22 结合主面
30 输入侧电极
31 第一部分
31A 底部
31B 突出部
32 第二部分
32A 底部
32B 突出部
40 输出侧电极
41 第一部分
41A 底部
41B 突出部
42 第二部分
42A 底部
42B 突出部
51 输入侧配线
61 输出侧配线

Claims (6)

1.一种陶瓷基板，其由多晶陶瓷形成并具有支撑主面，其中，
所述支撑主面具有以Sa表示的0.01nm以上且3.0nm以下的粗糙度，并且
在所述支撑主面上，边长为50μm的正方形区域内高度为1nm以上的凹凸的数目平均小于5个、并且在所述正方形区域内高度为2nm以上的凹凸的数目平均小于1个。
2.根据权利要求1所述的陶瓷基板，其中所述支撑主面具有以Sq表示的0.5nm以下的粗糙度。
3.根据权利要求1或2所述的陶瓷基板，其中，
所述多晶陶瓷由选自由下列材料构成的组中的至少一种材料制成：尖晶石、氧化铝、氧化镁、二氧化硅、富铝红柱石、堇青石、氧化钙、二氧化钛、氮化硅、氮化铝和碳化硅。
4.一种层叠体，其包含：
根据权利要求1至3中任一项所述的陶瓷基板；和
配置在所述支撑主面上并由压电体形成的压电基板，
其中所述陶瓷基板和所述压电基板通过范德华力互相结合。
5.根据权利要求4所述的层叠体，其中，
所述陶瓷基板与所述压电基板之间的结合强度为0.5J/m2以上。
6.一种SAW器件，其包含：
根据权利要求4或5所述的层叠体；和
在所述压电基板的主面上形成的电极，所述主面位于所述陶瓷基板的相反侧。
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