CN107360380B - Double-code-rate compression camera device and upper computer decoding device thereof - Google Patents
Double-code-rate compression camera device and upper computer decoding device thereof Download PDFInfo
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- 230000008521 reorganization Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
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- 238000010586 diagram Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
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- 101000911390 Homo sapiens Coagulation factor VIII Proteins 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/439—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using cascaded computational arrangements for performing a single operation, e.g. filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2628—Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
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- Engineering & Computer Science (AREA)
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Abstract
The invention provides a double-code-rate compression camera device and an upper computer decoding device thereof, which are stable in work, can acquire high-definition picture information on the premise of not increasing transmission bandwidth, and greatly improve the observation effect of loads on an aircraft on key targets. The double code rate compression camera device adopts a serial structure of FPGA and ARM; the IPIPEIF divides the received high-definition video into two paths, one path is sent to the image size adjusting module RZA to adjust the video size to a standard definition format, and then the standard definition video is sent to the compression core to carry out H.264 compression on the video data; the other path is sent to an image signal interface module ISIF and finally sent to a compression core for JPEG compression of picture data; dividing the JPEG-compressed picture data into a plurality of data blocks, and embedding one data block between two adjacent frames of video data; and sending serial data containing picture data and video data to the FPGA through the SPI.
Description
Technical field:
The invention belongs to image information technical field, it is related to a kind of double Compression photographic devices and its host computer decoding dress
It sets, more particularly to the improvement to Image Acquisition Compression Transmission Technology.
Background technique:
With the continuous development of China's aerospace cause, the demand of China's effective monitoring load on board the aircraft at present
Increasing simultaneously.Due to being limited by transmission bandwidth and compression algorithm, monitor camera device is mostly used on China's aircraft
720x576 resolution ratio is compressed video data according to no more than 500kbps compression bit rate, to observe key position work
Make state；Due to being limited in bandwidth, to be transmitted to the image that earth station unzips it display again after 500kbps Compression
It is ineffective, it is difficult to meet observation requirement.Therefore how how to meet observation in the case where not improving bandwidth to require to become winged
The problem of row device monitor camera device focuses on solving.
By inquiring the related literatures of other field, patent document CN 102387348A is " applied to intelligent transportation
Dual code stream high definition camera " discloses a kind of dual code stream compression set, which adds the parallel processing structure of DSP using ARM, proposes
HD video and high definition picture are compressed simultaneously.But data volume is larger after program compression, is unable to satisfy in aerospace field
The smaller requirement of bandwidth, while the program can not to compression video and the compression bit rate of picture, resolution ratio be adjusted, flexibility
Not enough, it is unable to satisfy actual requirement of engineering.Although structure is not sufficiently stable moreover, parallel processing speeds are fast, it is easy to appear number
According to the loss in acquisition compression process, error code is caused to occur.
Summary of the invention:
The present invention proposes that a kind of double Compression photographic devices and its host computer decoding apparatus, the operation is stable are not improving
Under the premise of transmission bandwidth, high definition pictorial information can be collected, greatly improves sight of the load to common-denominator target on aircraft
Survey effect.
Solution of the invention is as follows:
Double Compression photographic devices include video acquisition module and video compressing module, using the string of FPGA plus ARM
Row structure；The video acquisition module is based on FPGA, acquires vision signal and is converted to HD video, is sent into video compress mould
Block；The video compressing module includes image conduit interface module IPIPEIF, image size adjustment module RZA and picture signal
Interface module ISIF；The HD video received is divided into two-way by image conduit interface module IPIPEIF, is sent into image tube all the way
The image size adjustment module RZA of road IPIPE adjusts video size to SD format, then by SD video be sent into compression core into
H.264, row video data compresses；Another way is sent into picture signal interface module ISIF, and is ultimately delivered to compression core and carries out picture number
According to JPEG compression；Image data after JPEG compression is divided into multiple data blocks, is embedded in an institute between adjacent two frames video data
State data block；It will include that the serial data of image data and video data is sent to FPGA by SPI interface, FPGA presses 422
Interface rear end data integrator sends data, and is sent to ground data receiving device by antenna.
Based on above scheme, the present invention has also further made following optimization:
In the serial data, compressed video data and compressed image data are end to end respectively added with mark
Position.
The video compressing module uses TI DM368 type product.
The FPGA is communicated by GPIO interface with video compressing module.
The video acquisition module is to convert the video signal format of acquisition to BT.1120 HD video agreement, according to
1080P@25HZ video is sent into video compressing module by BT.1120 HD video agreement；Described image size adjustment module RZA is
Video size is adjusted to 720x576, then 720x576@25HZ video is sent into compression core progress video data and is H.264 compressed.
It is 1KB size by each data block that the image data after the JPEG compression is split out.
Corresponding to the host computer decoding apparatus of above-mentioned double Compression photographic devices, including data reorganization module and decoding mould
After data reorganization module receives the serial data of compression, according to zone bit information, image data is chosen from video data for block
It out and recombinates, the video compression data chosen and recombinated and picture compression data are decoded aobvious by decoder module respectively
Show.
The invention has the following advantages that
1) serial structure of ARM is added using FPGA, stable structure is not in asking of losing in data acquisition compression process
Topic, can guarantee system steady operation.
2) it is compressed while using SD video and high definition picture for input video, in the premise for not improving transmission bandwidth
Under, high definition pictorial information can be collected, the significant increase clarity of observed object.
3) by solving the problems, such as bandwidth deficiency, ensure that data uniform transmission, meet to by compressed picture deblocking
Transmission of video requirement.
4) HD video is acquired by DM368, and HD video can be cut randomly and be scaled using RZA module；
5) FPGA can be communicated by GPIO interface with DM368, the resolution ratio of real time modifying video and picture compression,
Code rate, frame frequency.
6) earth station of the present invention can be shown using soft decoding progress real-time decoding.
Detailed description of the invention
Fig. 1 is photographic device outline structural diagram.
Fig. 2 is overall structure diagram of the invention.
Fig. 3 is working principle (the i.e. video sampling and compressing transport stream of DM368 in Fig. 2 of double Compressions in the present invention
Journey).
Fig. 4 is the flow chart of video acquisition thread in double Compressions.
Fig. 5 is video pictures compression process figure in double Compressions.
Fig. 6 is compressed data output flow chart in double Compressions.
Fig. 7 is video resolution, code rate modification process figure.
Fig. 8 is thin-skinned decoding process figure.
Specific embodiment
By way of example and in conjunction with the accompanying drawings, the implementation that the present invention will be described in detail.
Double Compression photographic device contour structures as shown in Figure 1, it is internal to place two pieces of circuit boards, including power panel
With video compress plate.
As shown in Fig. 2, double Compression photographic devices include the devices such as CMOS, FPGA and DM368, for video
Acquisition and double Compressions, corresponding built-in function can be divided into video data receive capabilities, compression function and transfer function.
FPGA (video acquisition module) as video acquisition and with external interface communication chip, FPGA is by collected video
Data conversion is sent to TI DM368 at BT.1120 format；TI DM368 (video compressing module) as video input, compression,
The master chip of transmission can satisfy the requirement of the experimental situations such as temperature.
H.264, double Compression photographic devices are scaled to high definition 1080P video to be compressed to 720x576,
High definition picture compression is carried out by 1080P (1920x1080) resolution ratio simultaneously, compression algorithm uses JPEG, and picture presses every 125 frame pressure
Contract a frame.Since picture uses JPEG compression, compression efficiency is not high, and the data volume after data compression is larger, by video data and
Image data successively passes down and will lead to bandwidth and increase to 1Mbps or more suddenly, therefore the present invention splits into image data
Multiple small data blocks, addition transmitted after the every frame compressed data of video data, can guarantee in this way transmission bandwidth uniformly without
It can increase suddenly, by the image data of compressed video by reaching ground installation under data integrator, and by video and figure
Sheet data distinguishes simultaneously decoding display respectively, SD video can observed object motion state, high definition picture can restore more mesh
Details is marked, observation effect is greatly improved.
The working principle of double Compression photographic devices is as follows:
1) FPGA acquires CMOS video, and video format is converted to BT.1120 HD video agreement；
2) DM368 receives 1080P@25HZ video according to BT.1120 HD video agreement, and video is sent into image conduit
Interface IPIPEIF module；
3) HD video received is divided into two-way by IPIPEIF module, is sent into the RZA (figure of image conduit IPIPE all the way
As big minor adjustment) for module to video progress size adjusting to 720x576, another way is sent into picture signal interface ISIF module, and
It is ultimately delivered to compression core and carries out JPEG compression；
4) H.264 RZA module is compressed 720x576@25HZ video feeding compression core；
5) image data after JPEG compression is divided into multiple 1KB data blocks, each data block is embedded in every frame video pressure
Contracting data are backmost；
6) compressed picture and video data are sent to by 16MHZ rate by FPGA by SPI interface, FPGA presses 422
Interface rear end data integrator sends data, and is sent to ground data receiving device by antenna；
7) after ground host computer receives video pictures compressed data, according to zone bit information, by image data from video
Choose in data and recombinate, while the video chosen and picture compression data being sent to decoding display respectively.
Mainly the work of each module in the inside DM368 is described in detail below:
As shown in figure 3, the compression of dicode rate includes video acquisition thread, video pictures compression thread, compressed bit stream output
Thread.
Video acquisition thread includes video acquisition unit, and video acquisition function is received from FPGA with the transmission of BT1120 format
1080P 25HZ video, will receive video save into buffer area in case coding thread dispatching.FPGA leads to video data
Cross the IPIPEIF (image conduit interface) that BT1120 interface is sent to DM368, be then distributed to ISIF (picture signal interface) and
IPIPE (image conduit) module carries out Data Stream Processing.
The acquisition of ISIF interface is completed to generate ISIF_INTO interrupt signal, the handle in interrupt response function after a frame image
Video data passes to video compressing module and carries out high definition picture JPEG compression.IPIPE module has RSZ (the big minor adjustment of image) mould
Block.The data received are carried out image size and are adjusted to 720x576 by the module, are then forwarded to compression module and are carried out H.264
Compression, video acquisition thread work process please refer to Fig. 4.
Wherein, the process of video acquisition task is indicated in dotted line, calls AVSERVER_bufGetEmpty from video first
The address that thread obtains storage screen buffer is encoded, DRV_captureStart function is then recalled and executes video acquisition times
AVSERVER_bufputFull function is called in business later, the sky that the deposit of collected video data is obtained from coding thread
In not busy buffer area, coding thread can call the data in buffer area to be encoded.
Video compressing module respectively compresses 720x576@25HZ SD video and high definition picture, and wherein SD regards
Frequency is compressed by code rate 500kbps, and high definition picture is compressed by every 100KB size, is opened every 125 frame video compress one
Picture, to guarantee not increase transmission bandwidth, image data is carried out splitting into multiple 1KB data blocks, be added in video by the present invention
After the every frame compressed data of data, can guarantee transmission bandwidth so uniformly without increasing suddenly, by compressed video and
Image data, which passes through, reaches ground installation under data integrator.In the present invention, FPGA is led to DM368 by GPIO interface
Letter, FPGA, which sends low and high level by GPIO, to send instruction to DM368, so as to compression video resolution, code rate, frame
The key messages such as frequency are adjusted in real time, to meet different compression requirements.
Refering to Fig. 5, Video coding process is as schemed, the process of presentation code task, first AVSERVER_ in dotted line
BufGetFull function obtains the address of storage screen buffer from video acquisition thread, then recalls AVSERVER_
BufGetEmpty obtains an empty buffer zone address from coding thread, the compressed video data after being used to store coding, later
It calls ALG_vidEncRun function to execute encoding tasks, AVSERVER_bufputFull function is called, by the compression after coding
Code stream is sent to compressed bit stream output thread, while calling AVSERVER_bufPutEmpty function by an idle buffer area
Coding thread is returned in address, in case coding next time obtains freebuf when executing.
For convenience of rear end decoding, video compression data video and image data are added into flag bit respectively end to end, and pass through
Data are sent to FPGA by SPI interface by transmission module, and data are sent to data integrator by 422 interfaces by FPGA, number
It is that ground receiving equipment is ultimately routed to, Fig. 6 is to video compression data addition frame head postamble and package according to synthesizer function
Compressed bit stream output module flow chart, the interior process for indicating compressed bit stream output task of dotted line, first calling AVSERVER_
BufGetFull function obtains the address of storage compressed video data buffer area from Video coding thread, then recalls VIDEO_
Compressed bit stream is sent to FPGA by StreamFileWrite function, calls AVSERVER_bufPutEmpty function will be empty later
Not busy buffer zone address returns coding thread.
Refering to Fig. 7, FPGA can be sent a command to by host computer, then is carried out low and high level by three GPIO interfaces and matched
It sets, can compile and be sent to DM368 for various modes, according to predetermined agreement, according to demand, to acquisition video real-time perfoming code
It is compressed after rate, resolution ratio, the resetting of frame frequency.
Refering to Fig. 8, compressed data choose by the decoding of rear end host computer first carries out group for image data after the subpackage of road
Packet, and give to decoder be decoded respectively.
Claims (7)
1. a kind of double Compression photographic devices, including video acquisition module and video compressing module, it is characterised in that: use
FPGA adds the serial structure of ARM；
The video acquisition module is based on FPGA, acquires vision signal and is converted to HD video, is sent into video compressing module；
The video compressing module includes image conduit interface module IPIPEIF, image size adjustment module RZA and picture signal
Interface module ISIF；The HD video received is divided into two-way by image conduit interface module IPIPEIF, is sent into image tube all the way
The image size adjustment module RZA of road IPIPE adjusts video size to SD format, then by SD video be sent into compression core into
H.264, row video data compresses；Another way is sent into picture signal interface module ISIF, and is ultimately delivered to compression core and carries out picture number
According to JPEG compression；Image data after JPEG compression is divided into multiple data blocks, is embedded in an institute between adjacent two frames video data
State data block；It will include that the serial data of image data and video data is sent to FPGA by SPI interface, FPGA passes through
422 interface rear end data integrators send data, and are sent to ground data receiving device by antenna.
2. double Compression photographic devices according to claim 1, it is characterised in that: in the serial data, after compression
Video data and compressed image data end to end respectively be added with flag bit.
3. double Compression photographic devices according to claim 1, it is characterised in that: the video compressing module uses
TIDM368 type product.
4. double Compression photographic devices according to claim 3, it is characterised in that: the FPGA by GPIO interface with
Video compressing module is communicated.
5. double Compression photographic devices according to claim 1, it is characterised in that: the video acquisition module is will to adopt
The video signal format of collection is converted to BT.1120 HD video agreement, according to BT.1120 HD video agreement by 1080P@25HZ
HD video is sent into video compressing module；Described image size adjustment module RZA be video size is adjusted to 720x576, then
720x576@25HZ SD video is sent into compression core progress video data H.264 to compress.
6. double Compression photographic devices according to claim 1, it is characterised in that: by the picture after the JPEG compression
Each data block that data are split out is 1KB size.
7. a kind of host computer decoding apparatus corresponding to double Compression photographic devices described in claim 2, which is characterized in that packet
It includes:
Data reorganization module, after the serial data for receiving compression, according to zone bit information, by image data from video data
Choose and recombinates；
The video compression data chosen and recombinated and picture compression data are decoded display by decoder module respectively.
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| CN109729361A (en) * | 2019-01-28 | 2019-05-07 | 北京晶品特装科技有限责任公司 | A kind of terminal hardware implementation method with audiovisual compression |
| CN111770377B (en) * | 2020-04-03 | 2022-04-01 | 北京数智鑫正科技有限公司 | Compression method for video playing system |
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| US7394288B1 (en) * | 2004-12-13 | 2008-07-01 | Massachusetts Institute Of Technology | Transferring data in a parallel processing environment |
| AU2006204634B2 (en) * | 2006-08-31 | 2009-10-29 | Canon Kabushiki Kaisha | Runlength encoding of leading ones and zeros |
| CN101009803A (en) * | 2006-12-31 | 2007-08-01 | 北京华纬讯电信技术有限公司 | High-resolution video transfer system and method |
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