CN107369683B - Anti-electromagnetic interference power device - Google Patents
Anti-electromagnetic interference power device Download PDFInfo
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- CN107369683B CN107369683B CN201710502967.3A CN201710502967A CN107369683B CN 107369683 B CN107369683 B CN 107369683B CN 201710502967 A CN201710502967 A CN 201710502967A CN 107369683 B CN107369683 B CN 107369683B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 230000005669 field effect Effects 0.000 claims abstract description 24
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 24
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 24
- 210000000746 body region Anatomy 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000001629 suppression Effects 0.000 claims 1
- 230000010355 oscillation Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a power device for resisting electromagnetic interference, which comprises: the MOS power device comprises a substrate of a first conduction type, a first grid electrode and a second grid electrode, wherein the bottom end of the substrate of the first conduction type is provided with a first drain electrode of the MOS power device, and the upper end of the substrate is provided with an epitaxial layer; a channel of a second conductivity type; a second conductive type body region in which a first source is provided, and a first gate is provided at an upper end between the adjacent body regions; the upper end of the epitaxial layer is provided with a first resistor in an insulating way, a second drain and a second grid of the metal-oxide semiconductor field effect transistor are simultaneously connected with the first grid, and a second source of the metal-oxide semiconductor field effect transistor is connected with the first source in common through the first resistor. The invention solves the technical problem that the power device is easy to be interfered by electromagnetic waves.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an anti-electromagnetic interference power device.
Background
The power device comprises a power IC and a power discrete device, the power discrete device mainly comprises semiconductor devices such as a power MOSFET, a high-power transistor and an IGBT, the power device is almost used in all electronic manufacturing industries, and applied products comprise a notebook computer, a PC, a server, a display and various peripherals in the field of computers; mobile phones, telephones and other various terminals and local-end equipment in the field of network communication; traditional black and white appliances and various digital products in the consumer electronics field; industrial PCs, instruments and control devices in industrial control systems. Besides ensuring the normal operation of the devices, the power device can also play an effective energy-saving role. Due to the continuous improvement of the requirements of electronic products and energy efficiency, the market of Chinese power devices keeps a faster development speed.
The power semiconductor device is an important component of a power electronic circuit, an ideal power semiconductor device has good static and dynamic characteristics, can bear high voltage and small leakage current in an off state, can flow large current and very low tube voltage drop in an on state, and has short on and off time in switching; the on-state loss, off-state loss and switching loss are all small. Meanwhile, the system can bear high di/dt and du/dt and has a full control function.
The conventional power device has extremely fast switching characteristics and realizes higher power conversion efficiency, but in the process of opening and closing the power device, a grid is easy to vibrate, so that the switching state of the power device is instantly uncontrollable, the power device is easy to malfunction, great electromagnetic interference is generated, and the reliability of the power device is reduced.
Disclosure of Invention
In order to solve the technical problem, the invention provides an anti-electromagnetic interference power device, wherein a shunt circuit is arranged on a first grid electrode, when the grid voltage of the power device vibrates excessively, the voltage is guided through the shunt circuit, the grid voltage is prevented from vibrating, and the technical problem that the power device is easy to be subjected to electromagnetic interference is solved.
To achieve these objects and other advantages in accordance with the purpose of the invention, there is provided an anti-electromagnetic interference power device, including:
the MOS power device comprises a substrate of a first conduction type, a first power source and a second power source, wherein the bottom end of the substrate of the first conduction type is provided with a first drain electrode of the MOS power device, and the upper end of the substrate is provided with an epitaxial layer of the first conduction type;
a channel of a second conductivity type disposed at an interval in the epitaxial layer;
a body region of a second conductivity type disposed above the channel and the epitaxial layer, wherein the body region covers at least upper ends of two adjacent channels to form adjacent body regions, a first source of the first conductivity type is disposed in the body region, and a first gate is disposed at an upper end between the adjacent body regions;
at least two first independent channels and two second independent channels which are not covered by the body region exist in the channels, metal-oxide semiconductor field effect transistors are arranged on the upper portions of the first independent channels, first resistors are arranged at the upper ends of the epitaxial layers in an insulating mode, second drains and second grids of the metal-oxide semiconductor field effect transistors are connected with the first grids at the same time, second sources of the metal-oxide semiconductor field effect transistors are connected with the first sources through the first resistors in a common mode, the number of the metal-oxide semiconductor field effect transistors is at least 2, each metal-oxide semiconductor field effect transistor is independently arranged in one first independent channel, the second grids of the metal-oxide semiconductor field effect transistors are connected in parallel, the second drains of the metal-oxide semiconductor field effect transistors are connected in parallel, and the first drains of the metal-oxide semiconductor field effect transistors are connected in parallel, The second sources are connected in parallel.
Preferably, the upper end of the epitaxial layer is further provided with a second resistor in an insulated manner, and the second resistor is electrically connected with the first gate.
Preferably, a PN junction is disposed at an upper portion of the second independent channel, the second resistor is electrically connected to the first gate through the PN junction, the second resistor is connected to an anode of the PN junction, and a cathode of the PN junction is connected to the first gate.
Preferably, the second drain and the second gate of the mosfet are connected to a common end of the PN junction and the first gate.
Preferably, a source region and a drain region of the first conductivity type are spaced apart from each other at an upper portion of the first isolation channel, the second source electrode is disposed at an upper end of the source region, the second drain electrode is disposed at an upper end of the drain region, and the second gate electrode is disposed at an upper end of the source region and the drain region.
Preferably, a base region of the first conductivity type is disposed above the second isolated channel, a first region of the second conductivity type is disposed above the base region, and a second region of the first conductivity type is disposed above the base region.
Preferably, the first conductive type is N-type, the second conductive type is P-type, the first region is an anode of the PN junction, and the second region is a cathode of the PN junction.
Preferably, the first conductive type is P-type, the second conductive type is N-type, the second region is an anode of the PN junction, and the first region is a cathode of the PN junction.
Preferably, the first gate is a split gate or a full gate.
The invention at least comprises the following beneficial effects:
1. the anti-electromagnetic interference power device has the advantages that the switching speed is higher, and the switching capacity is larger;
2. the anti-electromagnetic interference capability is strong, and the reliability of the power device is higher;
3. the switching losses of the power device are lower.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
FIG. 1 is a cross-sectional view of a power device resistant to electromagnetic interference;
FIG. 2 is a top view of a power device resistant to electromagnetic interference;
fig. 3 is a partially enlarged schematic view of fig. 2.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic diagrams listed in the drawings of the specification enlarge the thicknesses of the layers and regions of the present invention, and the sizes of the listed figures do not represent actual sizes; the drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure. The embodiments listed in the specification should not be limited to the specific shapes of the regions shown in the drawings of the specification, but include the resulting shapes such as manufacturing-induced variations and the like, and the curves obtained by etching generally have curved or rounded features, which are represented by rectangles in the embodiments of the present invention.
As shown in fig. 1 to 3, the anti-electromagnetic interference power device provided by the present invention includes:
a substrate 700 of a first conductivity type, a first drain of the MOS power device being disposed at a bottom end of the substrate 700, an epitaxial layer 200 of the first conductivity type being disposed at an upper end of the substrate 700, the substrate epitaxial layer 200 preferably being made of silicon, but not limited to silicon;
a body region 300 of the second conductivity type, which is disposed above the trenches 100 and the epitaxial layer 200, specifically, the body region 300 of the second conductivity type is disposed over several trenches 100, so that the body region 300 of the second conductivity type is finally flush with the upper end of the epitaxial layer 200, wherein the body region 300 at least covers the upper ends of two adjacent trenches 100 to form adjacent body regions, a first source 310 of the first conductivity type is disposed in the body regions, and a first gate 500 is disposed at the upper end between the adjacent body regions, thereby forming a MOS power device;
at least two first independent channels 110 and two second independent channels 120 which are not covered by the body region 300 exist in the channel 100, a metal-oxide semiconductor field effect transistor is arranged on the upper portion of the first independent channel 110, a first resistor 610 is arranged on the upper end of the epitaxial layer 200 in an insulating mode, a second drain 115 and a second gate 114 of the metal-oxide semiconductor field effect transistor are simultaneously connected with the first gate 500, and a second source 113 of the metal-oxide semiconductor field effect transistor is connected with the first source 310 through the first resistor 610. The electrodes and the resistors are connected by metal wires, which is not described in the present embodiment.
When the power device is turned off, the first grid generates oscillation voltage, when the oscillation voltage is too high, the first source electrode is guided to the first source electrode through the metal-oxide semiconductor field effect tube, the high voltage is effectively reduced and absorbed through the first resistor, the oscillation of the grid voltage is avoided, when the voltage of the first grid is in a normal voltage value, the metal-oxide semiconductor field effect tube is cut off, the current cannot be guided through the metal-oxide semiconductor field effect tube, the consumption of the first resistor is avoided, the loss of the power device is reduced, the switching capacity of the power device is improved, the oscillation of the grid voltage is effectively eliminated, the super-strong anti-electromagnetic interference capacity is achieved, the reliability of the power device is improved, the switching speed is higher, and the switching capacity is higher.
In one embodiment, the first gates 500 are split-gate gates, that is, the first gates are independently disposed at the upper end of each body region, and do not connect two adjacent body regions.
In one embodiment, an insulating film 400 is formed on an upper surface of a power device, a conductive film is formed on the insulating film 400, the conductive film and the insulating film are etched, and the remaining conductive film becomes the first gate, the second gate and the first resistor, and a second resistor 620 is formed on the conductive film, wherein the second resistor 620 is connected to the first gate 500.
In one embodiment, a PN junction is disposed above the second isolation channel 120, the second resistor 620 is electrically connected to the first gate 500 through the PN junction, wherein the second resistor 620 is connected to an anode of the PN junction, a cathode of the PN junction is connected to the first gate 500, and another end of the second resistor is connected to a control terminal of the first gate.
In one embodiment, the second drain 115 and the second gate 114 of the mosfet are connected to the common terminal of the PN junction cathode and the first gate 500.
In one embodiment, the first independent channel 110 is spaced apart from a source region 112 and a drain region 111 of the first conductivity type, as shown in fig. 2 and 3, the second source 113 is disposed at an upper end of the source region 112, the second drain 115 is disposed at an upper end of the drain region 111, and the second gate 114 is disposed at an upper end of the source region and the drain region.
In one embodiment, a base region 121 of the first conductivity type is disposed above the second independent channel 120, a first region 122 of the second conductivity type is disposed above the second independent channel, and a second region 123 of the first conductivity type is disposed above the base region 121.
In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the first region is an anode of the PN junction, and the second region is a cathode of the PN junction.
In one embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the second region is an anode of the PN junction, and the first region is a cathode of the PN junction.
In one embodiment, the number of the metal-oxide semiconductor field effect transistors is at least 2, each metal-oxide semiconductor field effect transistor is independently configured in one first independent channel, and each second gate, each second drain and each second source of each metal-oxide semiconductor field effect transistor are connected in parallel, so that the diversion effect of the first gate overvoltage is enhanced, gate voltage oscillation is further reduced, and the switching-off characteristic of the power device is stabilized.
Therefore, the anti-electromagnetic interference power device provided by the invention has the advantages of higher switching speed, larger switching capacity, strong anti-electromagnetic interference capability, higher reliability and lower switching loss.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (8)
1. A power device resistant to electromagnetic interference, comprising:
the MOS power device comprises a substrate of a first conduction type, a first power source and a second power source, wherein the bottom end of the substrate of the first conduction type is provided with a first drain electrode of the MOS power device, and the upper end of the substrate is provided with an epitaxial layer of the first conduction type;
a channel of a second conductivity type disposed at an interval in the epitaxial layer;
a body region of a second conductivity type disposed above the channel and the epitaxial layer, wherein the body region covers at least upper ends of two adjacent channels to form adjacent body regions, a first source of the first conductivity type is disposed in the body region, and a first gate is disposed at an upper end between the adjacent body regions;
the upper end of the epitaxial layer is provided with a first resistor in an insulating way, a second drain and a second grid of the metal-oxide semiconductor field effect transistor are simultaneously connected with the first grid, and a second source of the metal-oxide semiconductor field effect transistor is connected with the first source in common through the first resistor;
the number of the metal-oxide semiconductor field effect transistors is at least 2, each metal-oxide semiconductor field effect transistor is independently configured in one first independent channel, and each second grid electrode, each second drain electrode and each second source electrode of each metal-oxide semiconductor field effect transistor are connected in parallel.
2. The emi suppression power device as claimed in claim 1, wherein said epitaxial layer is further provided with a second resistor at an upper end thereof in an insulated manner, and is electrically connected to said first gate.
3. The anti-emi power device as claimed in claim 2, wherein said second isolated channel is provided with a PN junction at its upper portion, said second resistor is electrically connected to said first gate through said PN junction, said second resistor is connected to an anode of said PN junction, and a cathode of said PN junction is connected to said first gate.
4. The EMI resistant power device of claim 3, wherein the second drain and the second gate of said MOSFET are connected at a common terminal of said PN junction and said first gate.
5. The EMI resistant power device as claimed in claim 4, wherein the first isolated channel is spaced apart at an upper portion thereof by a source region and a drain region of the first conductivity type, the second source electrode is disposed at an upper end of the source region, the second drain electrode is disposed at an upper end of the drain region, and the second gate electrode is disposed at an upper end of the source region and the drain region.
6. The anti-electromagnetic interference power device according to claim 5, wherein a base region of the first conductivity type is disposed on an upper portion of the second independent channel, a first region of the second conductivity type is disposed on an upper portion of the second independent channel, and a second region of the first conductivity type is disposed on an upper end of the base region.
7. The anti-electromagnetic interference power device of claim 6, wherein the first conductivity type is N-type, the second conductivity type is P-type, the first region is an anode of the PN junction, and the second region is a cathode of the PN junction.
8. The anti-electromagnetic interference power device of claim 6, wherein the first conductivity type is P-type, the second conductivity type is N-type, the second region is an anode of the PN junction, and the first region is a cathode of the PN junction.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710502967.3A CN107369683B (en) | 2017-06-27 | 2017-06-27 | Anti-electromagnetic interference power device |
| PCT/CN2017/108955 WO2019000762A1 (en) | 2017-06-27 | 2017-11-01 | Electromagnetic interference-resistant power component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710502967.3A CN107369683B (en) | 2017-06-27 | 2017-06-27 | Anti-electromagnetic interference power device |
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| CN107369683A CN107369683A (en) | 2017-11-21 |
| CN107369683B true CN107369683B (en) | 2020-06-23 |
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| CN201710502967.3A Active CN107369683B (en) | 2017-06-27 | 2017-06-27 | Anti-electromagnetic interference power device |
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| CN (1) | CN107369683B (en) |
| WO (1) | WO2019000762A1 (en) |
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| US5304802A (en) * | 1992-01-06 | 1994-04-19 | Fuji Electric Co., Ltd. | Semiconductor device including overvoltage protective circuit |
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| CN103151348A (en) * | 2011-12-06 | 2013-06-12 | 英飞凌科技奥地利有限公司 | Integrated circuit including a power transistor and an auxiliary transistor |
| TW201411809A (en) * | 2012-09-05 | 2014-03-16 | Silicongear Corp | Power MOSFET element |
| CN105161491A (en) * | 2015-09-22 | 2015-12-16 | 苏州东微半导体有限公司 | Integrated gate driver transistor (IGDT) power device and manufacturing method thereof |
| WO2016173394A1 (en) * | 2015-04-30 | 2016-11-03 | 苏州东微半导体有限公司 | Semiconductor super-junction power device and manufacturing method therefor |
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| KR101418396B1 (en) * | 2007-11-19 | 2014-07-10 | 페어차일드코리아반도체 주식회사 | Power semiconductor device |
| US8614480B2 (en) * | 2011-07-05 | 2013-12-24 | Texas Instruments Incorporated | Power MOSFET with integrated gate resistor and diode-connected MOSFET |
| US9893175B2 (en) * | 2013-09-30 | 2018-02-13 | Infineon Technologies Austria Ag | Integrated circuit with a power transistor and a driver circuit integrated in a common semiconductor body |
| US9425304B2 (en) * | 2014-08-21 | 2016-08-23 | Vishay-Siliconix | Transistor structure with improved unclamped inductive switching immunity |
| CN104952928A (en) * | 2015-04-30 | 2015-09-30 | 苏州东微半导体有限公司 | Gate-drain capacitance slow change super-junction power device and manufacturing method thereof |
| CN107256865B (en) * | 2017-06-27 | 2020-06-19 | 苏州美天网络科技有限公司 | Low-loss semiconductor power device |
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2017
- 2017-06-27 CN CN201710502967.3A patent/CN107369683B/en active Active
- 2017-11-01 WO PCT/CN2017/108955 patent/WO2019000762A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304802A (en) * | 1992-01-06 | 1994-04-19 | Fuji Electric Co., Ltd. | Semiconductor device including overvoltage protective circuit |
| CN101019319A (en) * | 2004-08-03 | 2007-08-15 | 飞思卡尔半导体公司 | A semiconductor switch arrangement and an electronic device |
| CN103151348A (en) * | 2011-12-06 | 2013-06-12 | 英飞凌科技奥地利有限公司 | Integrated circuit including a power transistor and an auxiliary transistor |
| TW201411809A (en) * | 2012-09-05 | 2014-03-16 | Silicongear Corp | Power MOSFET element |
| WO2016173394A1 (en) * | 2015-04-30 | 2016-11-03 | 苏州东微半导体有限公司 | Semiconductor super-junction power device and manufacturing method therefor |
| CN105161491A (en) * | 2015-09-22 | 2015-12-16 | 苏州东微半导体有限公司 | Integrated gate driver transistor (IGDT) power device and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN107369683A (en) | 2017-11-21 |
| WO2019000762A1 (en) | 2019-01-03 |
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