CN107102671B - Low-power consumption fast transient response low-voltage difference adjustor - Google Patents
Low-power consumption fast transient response low-voltage difference adjustor Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
Low-power consumption fast transient response low-voltage difference adjustor, it is related to field of analog integrated circuit, the present invention includes the error amplifier connecting with input bias current source, the output power pipe of input termination high level input terminal, feedback proportional resistance group, output power pipe and the tie point of feedback proportional resistance group are as final output end, it is characterized in that, being provided with the first amplification module, transient response discharge path module and Drive Module between error amplifier and output power pipe.The present invention effectively reduces the recovery time of output voltage during the descending transient changing of load.
Description
Technical field
The present invention relates to field of analog integrated circuit, it is related specifically to have the low drop voltage of fast transient response to adjust
Device.
Background technique
Low-voltage difference adjustor is an important component part in electric power management circuit, is generally used for DC-DC switch
The rear class of conversion circuit is used as POL power supply, and the loading point that is negative provides reliable and stable supply voltage, due to its pressure drop is small,
PSRR high, it is at low cost the advantages that, be widely used in portable electronic product.
In portable use field, to extend battery-powered time: system design aspect, by introducing enabled shutdown function
Can, under specific operating mode, only part of module works, and part of module is in an off state, therefore in different operating mould
In formula handoff procedure, load current meeting instantaneous abrupt change jumps to several amperes from several milliamperes, in order to reduce load current instantaneous variation
Influence to output voltage, just to the load transient response speed of low-voltage difference adjustor, more stringent requirements are proposed for this.
In addition, the transfer efficiency raising of low-voltage difference adjustor itself is also critically important, low-voltage difference adjustor is influenced
Two major parameters of transfer efficiency are low drop voltage and quiescent current, and low voltage difference is required to increase power tube area, be will cause
The grid capacitance of power tube is excessive, and low quiescent current will affect the slew rate of grid charge and discharge, to influence loop load transient
Response speed.Traditional low-voltage difference adjustor structure is as shown in Figure 1, VOUTSpike is generated in load transient variation, due to
By amplifier finite static current limit, output power tube grid VGCharge and discharge delay can very big, VOUTAgain restore to stablize to need
Regular hour, ameliorative way common for small-power low-voltage difference adjustor are increase amplifier quiescent currents, but right
In the high current voltage adjuster of 1A or more, power tube grid capacitance is very big, simple to improve transient state sound by increasing quiescent current
It answers, will increase dramatically the quiescent dissipation of entire LDO, therefore conventional low voltage difference adjustor can not combine low-power consumption and fast
Fast load transient response.
Summary of the invention
The technical problem to be solved by the present invention is to propose a kind of low-voltage difference adjustor structure, do not increasing static state
Under current condition, low-voltage difference adjustor load transient response speed can be effectively improved.
The present invention solve the technical problem the technical solution adopted is that, low-power consumption fast transient response low drop voltage tune
Whole device, it is output power pipe including the error amplifier, input termination high level input terminal that are connect with input bias current source, anti-
The tie point of feedback proportion resistor group, output power pipe and feedback proportional resistance group is as final output end, which is characterized in that accidentally
The first amplification module, transient response discharge path module and Drive Module are provided between poor amplifier and output power pipe.
First amplification module includes:
5th transistor Q5 of positive-negative-positive, emitter connect final output end, and base stage connects the output end of error amplifier,
Collector connects the collector of the 6th transistor,
6th transistor Q6 of NPN type, collector are connected with base stage, emitter ground connection, the driver connected module of base stage
Input terminal, base stage also connect the input terminal of transient response discharge path module.
Transient response discharge path module includes:
The second transistor Q2 of NPN type, base stage connect the input terminal of transient response discharge path module, and emitter connects
Ground, collector connect the first bias current sources；
The third transistor Q3 of positive-negative-positive, emitter connect high level input terminal, and base stage connects the current collection of second transistor Q2
Pole, collector are grounded by the second bias current sources；
4th transistor Q4 of NPN type, collector connect final output end, and base stage connects the collector of third transistor Q3,
Emitter ground connection.
Drive Module includes:
First NMOS tube MN1, source electrode ground connection, drain and gate are all connect with input bias current source；
4th NMOS tube MN4, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain electrode meets the 6th PMOS
The drain electrode of pipe MP6；
5th NMOS tube MN5, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain electrode connects the 9th crystal
The emitter of pipe Q9；
6th NMOS tube MN6, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain electrode meets the tenth PMOS
The drain electrode of pipe MP10；
7th NMOS tube MN7, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain driver connected mould
Block output end VG；
6th PMOS tube MP6, source electrode are connect with high level input terminal, and grid and drain electrode connect；
7th PMOS tube MP7, source electrode are connect with high level input terminal, and grid is connect with the grid of the 6th PMOS tube MP6,
Drain electrode is connect with the collector of the 8th transistor Q8；
8th PMOS tube MP8, source electrode are connect with high level input terminal, and grid is connect with the grid of the 6th PMOS tube MP6,
Drain driver connected module output end VG；
9th PMOS tube MP9, source electrode are connect with high level input terminal, and the emitter of grid and the 9th transistor Q9 connect
It connects, drain electrode is connect with the base stage of the 9th transistor Q9；
Tenth PMOS tube MP10, source electrode are connect with high level input terminal, and the emitter of grid and the 9th transistor Q9 connect
It connects, drain electrode is connect with the base stage of the tenth transistor Q10；
7th transistor Q7, base stage connect the input terminal of transient response discharge path module, emitter ground connection, and collector connects
The drain electrode of 9th PMOS tube MP9；
8th transistor Q8, base stage connect the input terminal of transient response discharge path module, emitter ground connection, and collector connects
The base stage of 11st transistor Q11；
9th transistor Q9, collector connect high level input terminal；
Tenth transistor Q10, the driver connected module output end V of emitterG, collector connects input high level；
11st transistor Q11, the driver connected module output end V of collectorG, emitter ground connection.
It is defeated to introduce AB class to low-voltage difference adjustor of the invention compared with existing similar low-voltage difference adjustor
The driver of structure out, under limit, driver quiescent current is by bias current IBIt determines, under load transient change condition,
Emitter follower Q10 and grounded emitter amplifier Q11 has very strong push-and-pull current capacity, can be to power tube MPGrid VGQuick charge and discharge
Electricity improves output power pipe grid grade VGTwo-way slew rate reduces the grid charge and discharge time, is not having to additional increase quiescent current
Under conditions of increase substantially voltage voltage difference adjustor load transient response speed.
BJT transistor Q2, Q3, Q4 and bias current I are introduced simultaneouslyB1、IB2The transient response discharge path of formation, when negative
Carry electric current from it is fully loaded change to zero load when, quick release output capacitance COOn excess charge, effectively reduce load by big
The recovery time of output voltage during to small transient changing.
Detailed description of the invention
Fig. 1 is conventional low voltage difference adjustor structural schematic diagram.
Fig. 2 is fast transient response low-voltage difference adjustor structural schematic diagram of the present invention.
Fig. 3 present invention and existing voltage adjuster output voltage simulation waveform comparison diagram.
Fig. 4 is drive circuit schematic diagram of the present invention.
Fig. 5 is operation amplifier circuit schematic diagram of the present invention.
Specific embodiment
Herein, MP indicates PMOS tube, and MN indicates NMOS tube, and Q indicates transistor.Hereinafter, for the ease of reading, sometimes
As writing a Chinese character in simplified form in a manner of " type+serial number ", for example, writing a Chinese character in simplified form using " MN4 " as " the 4th NMOS tube MN4 ", using " Q5 " as
" the 5th transistor Q5's " writes a Chinese character in simplified form.
As shown in Fig. 2, the present invention include the error amplifier being connect with input bias current source, input termination high level it is defeated
Enter output power pipe, the feedback proportional resistance group at end, the tie point conduct of output power pipe and feedback proportional resistance group is final defeated
Outlet, which is characterized in that the first amplification module is provided between error amplifier and output power pipe, transient response electric discharge is led to
Road module and Drive Module.
First amplification module includes:
5th transistor Q5 of positive-negative-positive, emitter connect final output end, and base stage connects the output end of error amplifier,
Collector connects the collector of the 6th transistor,
6th transistor Q6 of NPN type, collector are connected with base stage, emitter ground connection, the driver connected module of base stage
Input terminal, base stage also connect the input terminal of transient response discharge path module.
Transient response discharge path module includes:
The second transistor Q2 of NPN type, base stage connect the input terminal of transient response discharge path module, and emitter connects
Ground, collector connect the first bias current sources；
The third transistor Q3 of positive-negative-positive, emitter connect high level input terminal, and base stage connects the current collection of second transistor Q2
Pole, collector are grounded by the second bias current sources；
4th transistor Q4 of NPN type, collector connect final output end, and base stage connects the collector of third transistor Q3,
Emitter ground connection.
Drive Module includes:
First NMOS tube MN1, source electrode ground connection, drain and gate are all connect with input bias current source；
4th NMOS tube MN4, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain electrode meets the 6th PMOS
The drain electrode of pipe MP6；
5th NMOS tube MN5, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain electrode connects the 9th crystal
The emitter of pipe Q9；
6th NMOS tube MN6, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain electrode meets the tenth PMOS
The drain electrode of pipe MP10；
7th NMOS tube MN7, source electrode ground connection, grid are connect with the grid of the first NMOS tube MN1, and drain driver connected mould
Block output end VG；
6th PMOS tube MP6, source electrode are connect with high level input terminal, and grid and drain electrode connect；
7th PMOS tube MP7, source electrode are connect with high level input terminal, and grid is connect with the grid of the 6th PMOS tube MP6,
Drain electrode is connect with the collector of the 8th transistor Q8；
8th PMOS tube MP8, source electrode are connect with high level input terminal, and grid is connect with the grid of the 6th PMOS tube MP6,
Drain driver connected module output end VG；
9th PMOS tube MP9, source electrode are connect with high level input terminal, and the emitter of grid and the 9th transistor Q9 connect
It connects, drain electrode is connect with the base stage of the 9th transistor Q9；
Tenth PMOS tube MP10, source electrode are connect with high level input terminal, and the emitter of grid and the 9th transistor Q9 connect
It connects, drain electrode is connect with the base stage of the tenth transistor Q10；
7th transistor Q7, base stage connect the input terminal of transient response discharge path module, emitter ground connection, and collector connects
The drain electrode of 9th PMOS tube MP9；
8th transistor Q8, base stage connect the input terminal of transient response discharge path module, emitter ground connection, and collector connects
The base stage of 11st transistor Q11；
9th transistor Q9, collector connect high level input terminal；
Tenth transistor Q10, the driver connected module output end V of emitterG, collector connects input high level；
11st transistor Q11, the driver connected module output end V of collectorG, emitter ground connection.
Embodiment:
The present embodiment includes: error amplifier, two feedback proportional resistance Rf1、Rf2, output power pipe MP, driver, PNP
The 5th transistor Q5 of type, third transistor Q3, NPN type second transistor Q2, the 4th transistor Q4, the 6th transistor Q6, specifically
Connection relationship are as follows: reference voltage meets error amplifier noninverting input, the first feedback sample resistance Rf1One termination output voltage
VOUT, another termination error amplifier reverse input end, the second feedback sample resistance Rf2One termination error amplifier reversely inputs
End, other end ground connection, error amplifier output VEAConnect the base stage of the 5th transistor Q5 of positive-negative-positive, the 5th transistor Q5 emitter
Meet output voltage VOUT, the 5th transistor Q5 collector connects the collector and ground level of the 6th transistor Q6, and the 5th transistor Q5 is in altogether
Emitter-base bandgap grading amplifies configuration, the 6th transistor Q6 emitter ground connection, and collector and ground level are connected together and connect NPN type second transistor Q2's
Base stage and driver input end, the 6th transistor Q6 and second transistor Q2 and the 7th transistor Q7 of internal drive,
Eight transistor Q8 form current-mirror structure, driver output connection PMOS power tube MPGrid, PMOS power tube MPSource electrode connects input
Voltage (high level input terminal) VIN, PMOS power tube MPDrain electrode meets output VOUT。
Second transistor Q2 transmitting ground connection, collector connect the ground level and bias current I of PNP transistor Q3B1, positive-negative-positive third
Transistor Q3 emitter connects power supply, and collector connects the base stage and the second bias current sources I of the 4th transistor Q4 of NPN typeB2, the 4th is brilliant
The emitter of body pipe Q4 is grounded, and collector meets output voltage VOUT。
Working principle of the present invention is, when load current increases suddenly, can make output voltage VOUTIt reduces rapidly, output voltage
VOUTReduction by the common base configuration that the 5th transistor Q5 is formed make the 5th transistor Q5 collector current reduction, the 5th crystal
Pipe Q5 collector current by the 6th transistor Q6 collector, the 7th transistor Q7 of the 6th transistor Q6 and internal drive,
8th transistor Q8 forms current-mirror structure, and the 7th transistor Q7, the 8th transistor Q8 collector current reduce, and controls driver
The tenth internal transistor Q10 collector current increases in β (NPN transistor current gain) times, the 11st transistor Q11 current collection
Electrode current reduces in β times, improves the negative sense slew rate of power tube grid, makes to adjust PMOS power tube grid rapid decrease, increase
Add power tube to export electric current, inhibits VOUTTransient state decline.
When load current reduces suddenly, output voltage V can be madeOUTIt rises rapidly, output voltage VOUTRise through the 5th
The common base configuration that transistor Q5 is formed increases the 5th transistor Q5 collector current, and the 5th transistor Q5 collector current passes through
The 7th transistor Q7, the 8th transistor Q8 of 6th transistor Q6 collector, the 6th transistor Q6 and internal drive form electricity
Mirror structure is flowed, the 7th transistor Q7, the 8th transistor Q8 collector current increase, and control the tenth transistor of internal drive
Q10 collector current reduces in β (NPN transistor current gain) times, and the 11st transistor Q11 collector current increases in β times,
The positive slew rate for improving power tube grid makes to adjust PMOS power tube grid rapid increase, reduces power tube and exports electric current,
Inhibit VOUTTransient state rise.
Load current changes under no-load condition from heavily loaded transient state, since driver is delayed, power tube grid VGVoltage cannot
Adjustment, power tube cannot close in time in time, and the short time, which appoints, so has very big output electric current, can be to output capacitance COCharging, leads
Output voltage is caused to rise.In order to reduce quiescent dissipation, feedback proportional resistance Rf1+Rf2=100k Ω, resistance value is very big, feedback network
It cannot be to output capacitance COOn excess charge quickly bleed off.Therefore, invention increases NPN transistor Q2, Q4 and PNP crystal
Pipe Q3 and two bias current sources IB1、IB2The transient response discharge path of formation, in output voltage since load current is unexpected
Reduce and it is raised during, output voltage VOUTRise through the 5th transistor Q5 formation common base configuration make the 5th crystal
Pipe Q5 collector current increases, and the 5th transistor Q5 collector current is mirrored to second transistor Q2 by the 6th transistor Q6,
The collector current of second transistor Q2 increases, and drives PNP transistor third transistor Q3, third transistor Q3 collector current
Increase, driving the 4th transistor Q4 electric current of NPN type increases, quick release output capacitance COOn excess charge, effectively reduce negative
Carry the recovery time of output voltage during descending transient changing.
As shown in figure 3, being output voltage 2.5V, load current 10us jumps to 1mA by 5A, then jumps to the load of 5A by 1mA
Transient response characteristic curve, wherein A is the output voltage of prior art discharge off access with load current change curve, and B is this
Invention has the output voltage of discharge path with load current change curve.
As shown in figure 4, drive circuit of the invention includes PMOS tube MP6, MP7, MP8, MP9, MP10, NMOS tube MN1,
MN4, MN5, MN6, MN7, NPN transistor Q7, Q8, Q9, Q10, Q11, bias current IB, specific connection relationship are as follows: input biasing
Current source IBOne end connects input voltage VIN, the other end connects grid and the drain electrode of the first NMOS tube MN1, while connecting NMOS tube
The grid of MN4, MN5, MN6, MN7, the source electrode ground connection of NMOS tube MN1, MN4, MN5, MN6, MN7, formation current-mirror structure, the 4th
The grid of the 6th PMOS tube MP6 of NMOS tube MN4 drain electrode connection and drain electrode, while connecting the 7th PMOS tube MP7, the 8th PMOS tube
The grid of MP8, the source electrode of PMOS tube MP6, MP7, MP8 meet input voltage VIN, form current-mirror structure, transistor Q7, Q8 base stage
Q6 base stage and collector are connected, emitter ground connection forms current-mirror structure, and transistor Q7 collector connects MP9 drain electrode and crystal
Pipe Q9 base stage, metal-oxide-semiconductor MP9 grid connect MP10 grid, transistor Q9 emitter, MN5 drain electrode, MP9, MP10 source electrode, Q9 current collection
Pole connects input voltage VIN, MP9, MP10, Q9 form quick response current-mirror structure, MP10 drain electrode connection MN6 drain electrode and and Q10
Base stage is connected, and Q10 collector meets input voltage VIN, Q10 emitter connection power grid VG, emitter following configuration is formed, MN7 is
It provides bias current, and Q8 collector connects MP7 drain electrode and Q11 base stage, Q11 emitter ground connection, and Q11 collector connects power grid
Pole VG, form cascode and amplify configuration, MP8 provides bias current for it.
The drive circuit working principle of AB class export structure is as follows, internal drive transistor Q7 and Q8 and external crystal
Pipe Q6 forms current mirror, then mirror image Q6 collector current amplifies current signal, driving power tube grid.
Under steady-state working condition, by designing the breadth length ratio of NMOS tube MN6 and PMOS tube MP7, NPN transistor Q10 is controlled
With the working condition of Q11, the emitter current of NPN transistor Q10 is made to be equal to the drain current of NMOS tube MN7, NPN transistor
The collector current of Q11 is equal to the drain current of PMOS tube MP8, passes through whole system feedback loop control VGVoltage is kept defeated
Voltage stabilization out.
Under transient condition, when output electric current increases suddenly, output voltage decline, Q7, Q8 collector current reduces, Q8 electric current
Variable quantity discharges to the grid capacitance of power tube by Q11 amplification β (β=110) times, greatly increases the velocity of discharge, mentions
The high negative sense slew rate of power tube grid, quickly opens power tube, increases power tube and export electric current, inhibit VOUTTransient state under
Drop.When output electric current reduce suddenly, output voltage rise, Q7, Q8 collector current increase, Q7 current change quantity by MP9,
The quick response current-mirror structure that MP10 and Q9 is formed is mirrored to NPN transistor Q10 base stage, passes through Q10 amplification β (β=110) times
It charges to the grid capacitance of power tube, greatly increases charging rate, improve the positive slew rate of power tube grid, fastly
Speed closes power tube, reduces power tube and exports electric current, inhibits VOUTTransient state rise.
As shown in figure 5, error amplifier circuit of the invention includes PMOS tube MP1, MP2, MP3, MP4, MP5, NMOS tube
MN1, MN2, MN3, NPN transistor Q1, Q2, Q3, Q4, resistance RC, capacitor CC, bias current IB, specific connection relationship are as follows: biasing
Electric current IBOne end connects input voltage VIN, the other end connect NMOS tube MN1 grid and drain electrode, while connect NMOS tube MN2,
The grid of MN3, the source electrode ground connection of NMOS tube MN1, MN2, MN3 form current-mirror structure, NMOS tube MN2 drain electrode connection PMOS tube
The grid of MP1 and drain electrode, while the grid of PMOS tube MP2, MP3 is connected, the source electrode of PMOS tube MP1, MP2, MP3 connect input voltage
VIN, current-mirror structure is formed, MP4 grid connects feedback sample voltage VFB, drain connection Q1 collector and Q1, Q2 base stage, MP5
Grid connects reference voltage Vref, drain electrode connection Q2 collector, MP4, MP5 source electrode connects MP2 drain electrode, composition Differential Input to pipe,
Q1, Q2 transmitter ground connection form active load, and Q3 base stage connects Q2 collector, emitter ground connection, and collector connects MP3 drain electrode,
Enlarged structure is formed, Q4 base stage connects Q3 collector, and collector connects input voltage VIN, emitter connection MN3 drains and amplifier
Export VEA, form follower configuration, CCOne end connects Q3 collector, and the other end connects RC, RCOne end connects CC, other end connection
Q3 base stage forms the miller-compensated structure for having zero point.Miller-compensated structure introduces a dominant pole and a zero point, in addition defeated
The second pole that capacitor introduces out includes two poles, one zero point in whole system band, reduce system to output capacitance ESR according to
Lai Xing guarantees the stability of system loop.
Claims (3)
1. low-power consumption fast transient response low-voltage difference adjustor, including the error amplification being connect with input bias current source
Device, the output power pipe of input termination high level input terminal, feedback proportional resistance group, output power pipe and feedback proportional resistance group
Tie point as final output end, which is characterized in that the first amplification is provided between error amplifier and output power pipe
Module, transient response discharge path module and Drive Module；
First amplification module includes:
5th transistor (Q5) of positive-negative-positive, emitter connect final output end, and base stage connects the output end of error amplifier, collect
Electrode connects the collector of the 6th transistor,
6th transistor (Q6) of NPN type, collector are connected with base stage, emitter ground connection, the driver connected module of base stage it is defeated
Enter end, base stage also connects the input terminal of transient response discharge path module.
2. low-power consumption fast transient response low-voltage difference adjustor as described in claim 1, which is characterized in that transient response
Discharge path module includes:
The second transistor (Q2) of NPN type, base stage connect the input terminal of transient response discharge path module, and emitter is grounded,
Its collector connects the first bias current sources；
The third transistor (Q3) of positive-negative-positive, emitter connect high level input terminal, and base stage connects the current collection of second transistor (Q2)
Pole, collector are grounded by the second bias current sources；
4th transistor (Q4) of NPN type, collector connect final output end, and base stage connects the collector of third transistor (Q3),
Emitter ground connection.
3. low-power consumption fast transient response low-voltage difference adjustor as described in claim 1, which is characterized in that driver mould
Block includes:
First NMOS tube (MN1), source electrode ground connection, drain and gate are all connect with input bias current source；
4th NMOS tube (MN4), source electrode ground connection, grid are connect with the grid of the first NMOS tube (MN1), and drain electrode meets the 6th PMOS
Manage the drain electrode of (MP6)；
5th NMOS tube (MN5), source electrode ground connection, grid are connect with the grid of the first NMOS tube (MN1), and drain electrode connects the 9th crystal
Manage the emitter of (Q9)；
6th NMOS tube (MN6), source electrode ground connection, grid are connect with the grid of the first NMOS tube (MN1), and drain electrode meets the tenth PMOS
Manage the drain electrode of (MP10)；
7th NMOS tube (MN7), source electrode ground connection, grid are connect with the grid of the first NMOS tube (MN1), and drain driver connected mould
Block output end (VG)；
6th PMOS tube (MP6), source electrode are connect with high level input terminal, and grid and drain electrode connect；
7th PMOS tube (MP7), source electrode are connect with high level input terminal, and grid is connect with the grid of the 6th PMOS tube (MP6),
Drain electrode is connect with the collector of the 8th transistor (Q8)；
8th PMOS tube (MP8), source electrode are connect with high level input terminal, and grid is connect with the grid of the 6th PMOS tube (MP6),
Drain driver connected module output end (VG)；
9th PMOS tube (MP9), source electrode are connect with high level input terminal, and the emitter of grid and the 9th transistor (Q9) connects
It connects, drain electrode is connect with the base stage of the 9th transistor (Q9)；
Tenth PMOS tube (MP10), source electrode are connect with high level input terminal, and the emitter of grid and the 9th transistor (Q9) connects
It connects, drain electrode is connect with the base stage of the tenth transistor (Q10)；
7th transistor (Q7), base stage connect the input terminal of transient response discharge path module, emitter ground connection, and collector connects the
The drain electrode of nine PMOS tube (MP9)；
8th transistor (Q8), base stage connect the input terminal of transient response discharge path module, emitter ground connection, and collector connects the
The base stage of 11 transistors (Q11)；
9th transistor (Q9), collector connect high level input terminal；
Tenth transistor (Q10), the driver connected module output end (V of emitterG), collector connects input high level；
11st transistor (Q11), the driver connected module output end (V of collectorG), emitter ground connection.
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| CN114756083A (en) * | 2022-04-01 | 2022-07-15 | 广东省大湾区集成电路与系统应用研究院 | Low-dropout linear voltage stabilizing circuit and electronic equipment |
| CN115097894B (en) * | 2022-07-08 | 2023-05-30 | 北京理工大学 | High-power supply rejection ratio push-pull type LDO (low dropout regulator) without off-chip capacitor |
| CN115097893B (en) * | 2022-08-15 | 2023-08-18 | 深圳清华大学研究院 | LDO circuit and MCU chip capable of outputting capacitor without plug-in |
| CN118051089B (en) * | 2024-04-12 | 2024-06-11 | 北京中天星控科技开发有限公司成都分公司 | Bidirectional current low-dropout linear voltage regulator |
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