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CN107065350B - Eight farmland 3T dot structures - Google Patents

Eight farmland 3T dot structures Download PDF

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Publication number
CN107065350B
CN107065350B CN201710229371.0A CN201710229371A CN107065350B CN 107065350 B CN107065350 B CN 107065350B CN 201710229371 A CN201710229371 A CN 201710229371A CN 107065350 B CN107065350 B CN 107065350B
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area
electrode
tft
primary area
film transistor
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CN107065350A (en
Inventor
甘启明
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/13624Active matrix addressed cells having more than one switching element per pixel
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Power Engineering (AREA)

Abstract

The present invention provides a kind of eight farmland 3T dot structures.The dot structure includes that multiple sub-pixels are arranged in liquid crystal display panel in array, each sub-pixel is divided into primary area and time area, a scan line is respectively set in corresponding every a line sub-pixel, and for the scan line between the primary area and secondary area, a data line is respectively set in corresponding each column sub-pixel;It further include primary area thin film transistor (TFT) and primary area storage capacitance, secondary area's thin film transistor (TFT) and secondary area's storage capacitance and shared thin film transistor (TFT);The primary area storage capacitance is formed by the first primary area storage electrode within the scope of primary area with opposite public electrode;Secondary area's storage capacitance is formed by the second primary area storage electrode within the scope of secondary area's range Nei Ci area's storage electrode and primary area with opposite public electrode;The grid of the shared thin film transistor (TFT) connects scan line, and source electrode and drain electrode is separately connected time area's storage electrode and the second primary area storage electrode.Dot structure of the invention can achieve the purpose of control primary area and secondary area's pressure difference ratio.

Description

Eight farmland 3T dot structures
Technical field
The present invention relates to field of liquid crystal, more particularly to a kind of eight farmland 3T dot structures.
Background technique
Liquid crystal display panel usually by colored filter substrate, thin-film transistor array base-plate and is configured between two substrates Liquid crystal layer constituted, and respectively two substrates relative inner be arranged pixel electrode, public electrode, pass through apply voltage control Liquid crystal molecule changes direction, and the light refraction of backlight module is come out and generates picture.Liquid crystal display includes twisted-nematic (TN) The plurality of display modes such as mode, birefringent (ECB) mode of electronic control, vertical orientation (VA), wherein VA mode is that one kind has High contrast, wide viewing angle, the common display pattern without advantages such as friction matchings.But since VA mode is using the liquid vertically rotated The diversity ratio of crystalline substance, liquid crystal molecule birefringence is larger, causes colour cast (color shift) problem under big visual angle than more serious.
With the development of LCD technology, show that the size of screen is increasing, conventionally employed 4domain (4 farmland) PSVA (polymer stabilizing vertical orientation) pixel can highlight the bad performance of visual angle colour cast.In order to promote the performance of panel visual angle, 3T_ The PSVA pixel of 8domain (8 farmland, 3 transistor) is gradually applied to the design of large size TV panel, makes the same sub-pixel 4 farmlands in main area (main) and the rotational angle of the liquid crystal molecule on 4 farmlands in time area (sub) are different in (sub pixel), from And improve colour cast.As shown in Figure 1, it is the circuit diagram of existing 3T dot structure.Multiple sub- pictures in liquid crystal display panel Element is arranged in array, and each sub-pixel can be divided into main area (main) Qu Heci (sub), including primary area thin film transistor (TFT) TFT_m, Primary area liquid crystal capacitance Clc_m, primary area storage capacitance Cst_m, secondary area's thin film transistor (TFT) TFT_s, secondary area's liquid crystal capacitance Clc_s are secondary A scanning is respectively set in area storage capacitance Cst_s and shared thin film transistor (TFT) TFT_share, corresponding every a line sub-pixel A data line Data is respectively set in line Gate, corresponding each column sub-pixel;The grid connection of primary area thin film transistor (TFT) TFT_m is swept Line Gate is retouched, source/drain connects data line Data, between its drain/source and public electrode A_com (or C_com) It is connected in parallel primary area liquid crystal capacitance Clc_m and primary area storage capacitance Cst_m;The grid connection of secondary area's thin film transistor (TFT) TFT_s is swept Line Gate is retouched, source/drain connects data line Data, between its drain/source and public electrode A_com (or C_com) It is connected in parallel time area liquid crystal capacitance Clc_s and time area storage capacitance Cst_s;The grid of shared thin film transistor (TFT) TFT_share connects Scan line Gate is met, source electrode and drain electrode is separately connected the drain/source and public electrode A_ of secondary area's thin film transistor (TFT) TFT_s com.It will be understood by those skilled in the art that although public electrode A_com and C_com title is different, in practical liquid crystal surface Usually current potential is identical both in plate, can only be indicated with public electrode A_com;For thin film transistor (TFT), due to its source electrode and The characteristic of drain electrode is the same, therefore its source electrode and drain electrode is not particularly limited in circuit;In the solid of liquid crystal display panel In structure, the two poles of the earth of liquid crystal capacitance and storage capacitance usually respectively correspond pixel electrode and (or identical with pixel electrode current potential deposit Storage pole) and public electrode.
8 farmland pixels have become the pixel designer trends of large scale TV panel, but under the high refreshing frequency of high-resolution, (Flicker) phenomenon is flashed to improve, the balance of primary area and time best common voltage in area (best vcom) is a difficulty always Point.How to solve this difficult point is the major issue that must be taken into consideration using existing 3T pixel.
Summary of the invention
Therefore, the purpose of the present invention is to provide a kind of eight farmland dot structures, the pressure difference in balance primary area and time area is when most Good common voltage.
To achieve the above object, the present invention provides a kind of eight farmland 3T dot structures, including multiple sub-pixels are in liquid crystal Show in panel and arrange in array, each sub-pixel is divided into primary area and time area, and corresponding every a line sub-pixel is respectively set one and sweeps Line is retouched, for the scan line between the primary area and secondary area, a data line is respectively set in corresponding each column sub-pixel;It further include master Area's thin film transistor (TFT) and primary area storage capacitance, secondary area's thin film transistor (TFT) and secondary area's storage capacitance and shared thin film transistor (TFT); The primary area storage capacitance is formed by the first primary area storage electrode within the scope of primary area with opposite public electrode;Secondary area's storage electricity The second primary area storage electrode and opposite public electrode shape within the scope of the area Rong Youci range Nei Ci area's storage electrode and primary area At;The grid of the primary area thin film transistor (TFT) connects scan line, and source/drain connects data line, drain/source connection first Primary area storage electrode or the pixel electrode in primary area;The grid of secondary area's thin film transistor (TFT) connects scan line, source/drain connection Data line, drain/source connect the pixel electrode in time area's storage electrode or secondary area;The grid connection of the shared thin film transistor (TFT) Scan line, source electrode and drain electrode are separately connected time area's storage electrode and the second primary area storage electrode.
Wherein, the primary area and time area respectively correspond to the liquid crystal molecule on four farmlands.
Wherein, first primary area storage electrode is connected via via hole with the pixel electrode in primary area.
Wherein, secondary area's storage electrode is connected via via hole with the pixel electrode in time area.
Wherein, first primary area storage electrode, secondary area's storage electrode and the second primary area storage electrode pass through same metal Layer production.
Wherein, the grid of the primary area thin film transistor (TFT), the grid of secondary area's thin film transistor (TFT) share the grid of thin film transistor (TFT) Pole and scan line are made by same metal layer.
Wherein, the source electrode and drain electrode of the primary area thin film transistor (TFT), the source electrode and drain electrode of secondary area's thin film transistor (TFT), shares thin The source electrode and drain electrode and data line of film transistor are made by same metal layer.
Wherein, the pixel electrode in the primary area and time area is made of tin indium oxide.
It wherein, is PSVA pixel.
To sum up, eight farmland 3T dot structures of the invention increase time area storage capacitance by reducing primary area storage capacitance, can be with Achieve the purpose that control primary area and secondary area's pressure difference ratio;In addition, due to the not formed access directly to discharge with public electrode A_com, There is no the too big problems of the best common voltage difference in primary area and secondary area.
Detailed description of the invention
With reference to the accompanying drawing, by the way that detailed description of specific embodiments of the present invention, technical solution of the present invention will be made And other beneficial effects are apparent.
In attached drawing,
Fig. 1 is the circuit diagram of existing 3T dot structure;
Fig. 2 is the circuit diagram of eight farmland 3T dot structures of the invention;
Fig. 3 is the schematic diagram of eight farmland 3T dot structures of the invention.
Specific embodiment
Referring to Fig. 3, for the schematic diagram of eight farmland 3T dot structures of the invention.It will be understood by those skilled in the art that this hair The bright improvement focused on to eight farmland 3T dot structures, therefore to include in liquid crystal display panel and pixel one in following explanation As structure repeat no more.
Eight farmland 3T dot structures of the invention, including multiple sub-pixels are arranged in liquid crystal display panel in array, often A sub-pixel is divided into primary area 10 and time area 20, and a scan line 30 is respectively set in corresponding every a line sub-pixel, which is situated between Between the primary area 10 and secondary area 20, a data line 40 is respectively set in corresponding each column sub-pixel;It further include that primary area film is brilliant Body pipe 11 and primary area storage capacitance, secondary area's thin film transistor (TFT) 21 and secondary area's storage capacitance and shared thin film transistor (TFT) 24;It should Primary area storage capacitance is formed by the primary area storage electrode 12 in 10 range of primary area with opposite public electrode 50;Secondary area's storage electricity Primary area storage electrode 13 and opposite common electrical in 20 area range Nei Ci storage electrode 22 of the area Rong Youci and 10 range of primary area Pole 50 is formed;The grid of the primary area thin film transistor (TFT) 11 connects scan line 30, and source/drain connects data line 40, drain/ Source electrode connects the pixel electrode 14 in primary area storage electrode 12 or primary area 10;The grid of secondary area's thin film transistor (TFT) 21 connects scan line 30, source/drain connects data line 40, and drain/source connects the pixel electrode 23 in time area's storage electrode 22 or secondary area 20; The grid of the shared thin film transistor (TFT) 24 connects scan line 30, and source electrode and drain electrode is separately connected secondary area's storage electrode 22 and master Area's storage electrode 13.
Primary area 10 and time area 20 respectively correspond the liquid crystal molecule on four farmlands.In processing procedure, primary area storage electrode 12 can be via Via hole is connected with pixel electrode 14;Secondary area's storage electrode 22 can be connected via via hole with pixel electrode 23.Primary area storage Electrode 12, secondary area's storage electrode 22 and primary area storage electrode 13 can be made by same metal layer.Primary area thin film transistor (TFT) 11 Grid, the grid of secondary area's thin film transistor (TFT) 21, share thin film transistor (TFT) 24 grid and scan line 30 can be by same Metal layer production.The source electrode and drain electrode of primary area thin film transistor (TFT) 11, the source electrode and drain electrode of secondary area's thin film transistor (TFT) 21 share film The source electrode and drain electrode and data line 40 of transistor 24 can be made by same metal layer.Pixel electrode 14 and pixel electrode 23 can be made of tin indium oxide.Eight farmland 3T dot structures of the invention can be PSVA pixel.
Referring to fig. 2, it is the circuit diagram of eight farmland 3T dot structures of the invention, is further appreciated that in conjunction with Fig. 2 and Fig. 3 The present invention.Multiple sub-pixels are arranged in array in liquid crystal display panel, and each sub-pixel can be divided into primary area and time area, including master Area thin film transistor (TFT) TFT_m, primary area liquid crystal capacitance Clc_m, primary area storage capacitance Cst_m, secondary area's thin film transistor (TFT) TFT_s are secondary Area liquid crystal capacitance Clc_s, secondary area's storage capacitance Cst_s share thin film transistor (TFT) TFT_share and secondary area's storage capacitance A scan line Gate is respectively set in Cst_s1, corresponding every a line sub-pixel, and a number is respectively set in corresponding each column sub-pixel According to line Data;The grid of primary area thin film transistor (TFT) TFT_m connects scan line Gate, and source/drain connects data line Data, Primary area liquid crystal capacitance Clc_m and primary area storage electricity are connected in parallel between its drain/source and public electrode A_com (or C_com) Hold Cst_m;The grid of secondary area's thin film transistor (TFT) TFT_s connects scan line Gate, and source/drain connects data line Data, Time area liquid crystal capacitance Clc_s, secondary area's storage capacitance are connected in parallel between its drain/source and public electrode A_com (or C_com) Cst_s;The grid of shared thin film transistor (TFT) TFT_share connects scan line Gate, and it is thin that source electrode and drain electrode is separately connected time area The drain/source of film transistor TFT_s and time area storage capacitance Cst_s1, another termination of secondary area's storage capacitance Cst_s1 are public Electrode A _ com.Core of the invention thought is exactly according to time area shown in Fig. 2 by across scan line Gate, in the public of primary area Form storage capacitance Cst_s1 above electrode A _ com, the area Shi Ci storage capacitance increases to ultimate attainment, while also relatively reducing primary area Storage capacitance can achieve the purpose of control primary area and secondary area's pressure difference ratio;And only in shared thin film transistor (TFT) TFT_share When unlatching, capacitor charging access is just formed, reduces time area and maintains (holding) voltage;In addition, due to being the capacitive junctions to be formed Structure not will form strong discharge path, is formed not as the circuit of the existing 3T dot structure of Fig. 1 and is directly put with A_com The access of electricity, so the problem too big there is no the best common voltage difference in primary area and secondary area.
To sum up, eight farmland 3T dot structures of the invention increase time area storage capacitance by reducing primary area storage capacitance, can be with Achieve the purpose that control primary area and secondary area's pressure difference ratio;In addition, due to the not formed access directly to discharge with public electrode A_com, There is no the too big problems of the best common voltage difference in primary area and secondary area.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the appended right of the present invention It is required that protection scope.

Claims (9)

1. a kind of eight farmland 3T dot structures, multiple sub-pixels are arranged in liquid crystal display panel in array, each sub-pixel point For primary area and time area, a scan line is respectively set in corresponding every a line sub-pixel, the scan line between the primary area and secondary area, A data line is respectively set in corresponding each column sub-pixel, which is characterized in that further includes that primary area thin film transistor (TFT) and primary area are deposited Storage appearance, secondary area's thin film transistor (TFT) and secondary area's storage capacitance and shared thin film transistor (TFT);The primary area storage capacitance is by primary area model The first primary area storage electrode in enclosing is formed with opposite public electrode;Secondary area's storage capacitance is deposited by the secondary area area's range Nei Ci The second primary area storage electrode within the scope of storage pole and primary area is formed with opposite public electrode;The grid of the primary area thin film transistor (TFT) Pole connects scan line, and source/drain connects data line, and drain/source connects the picture in the first primary area storage electrode or primary area Plain electrode;The grid of secondary area's thin film transistor (TFT) connects scan line, and source/drain connects data line, drain/source connection Secondary area's storage electrode or the pixel electrode in secondary area;The grid of the shared thin film transistor (TFT) connects scan line, source electrode and drain electrode point It Lian Jie not time area's storage electrode and the second primary area storage electrode.
2. eight farmlands 3T dot structure as described in claim 1, which is characterized in that the primary area and time area respectively correspond to four farmlands Liquid crystal molecule.
3. eight farmlands 3T dot structure as described in claim 1, which is characterized in that first primary area storage electrode is via via hole It is connected with the pixel electrode in primary area.
4. eight farmlands 3T dot structure as described in claim 1, which is characterized in that secondary area's storage electrode via via hole and time The pixel electrode in area is connected.
5. eight farmlands 3T dot structure as described in claim 1, which is characterized in that first primary area storage electrode, secondary area deposits Storage pole and the second primary area storage electrode are made by same metal layer.
6. eight farmlands 3T dot structure as described in claim 1, which is characterized in that the grid of the primary area thin film transistor (TFT), it is secondary The grid of area's thin film transistor (TFT), the grid and scan line of shared thin film transistor (TFT) are made by same metal layer.
7. eight farmlands 3T dot structure as described in claim 1, which is characterized in that the source electrode of the primary area thin film transistor (TFT) and leakage Pole, the source electrode and drain electrode of secondary area's thin film transistor (TFT), the source electrode and drain electrode and data line for sharing thin film transistor (TFT) pass through same gold Belong to layer production.
8. eight farmlands 3T dot structure as described in claim 1, which is characterized in that the pixel electrode in the primary area and time area is by oxygen Change indium tin to be made.
9. eight farmlands 3T dot structure as described in claim 1, which is characterized in that it is PSVA pixel.
CN201710229371.0A 2017-04-10 2017-04-10 Eight farmland 3T dot structures Active CN107065350B (en)

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