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CN106847761B - 一种具有半导体元件封装保护结构的堆栈芯片 - Google Patents

一种具有半导体元件封装保护结构的堆栈芯片 Download PDF

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Publication number
CN106847761B
CN106847761B CN201610072873.2A CN201610072873A CN106847761B CN 106847761 B CN106847761 B CN 106847761B CN 201610072873 A CN201610072873 A CN 201610072873A CN 106847761 B CN106847761 B CN 106847761B
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chip
stack
semiconductor component
protection structure
component packing
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CN106847761A (zh
Inventor
廖珮淳
丁柏玮
江志烽
吴玉凯
张宇凡
林瑞钦
蔡绪孝
林正国
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WIN Semiconductors Corp
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WIN Semiconductors Corp
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Abstract

本发明公开了一种具有半导体元件封装保护结构的堆栈芯片，包括：相互堆栈的一第一芯片以及一第二芯片，其中该第一芯片具有一第一表面，该第二芯片具有一第二表面，该第一表面以及该第二表面为两个相互面对面的表面，其中至少一金属凸块形成于该第一表面及该第二表面中的至少之一上且与该第一表面及该第二表面中的另一个相连接，至少一保护环形成于该第一表面及该第二表面中的至少之一上且与该第一表面及该第二表面中的另一个之间具有一第一间隙，以及至少一电子元件形成于该第一表面及该第二表面中的至少之一上，且该至少一电子元件位于该至少一保护环的至少之一所围绕的范围内。

Description

一种具有半导体元件封装保护结构的堆栈芯片
技术领域
本发明涉及一种具有半导体元件封装保护结构的堆栈芯片，尤指一种具有高结构强度及具有半导体元件封装保护结构的堆栈芯片。
背景技术
系统封装(system in package,SIP)中若包含了表面声波元件或体声波元件等元件，于封装时，若封装材料直接覆盖住表面声波元件或体声波元件，则会对表面声波元件或体声波元件的元件特性造成不利影响。此外，系统封装中若包含了表面声波元件或体声波元件，于封装时，若封装材料直接覆盖住微机电元件或陀螺仪元件，有时甚至连微机电元件或陀螺仪元件的功能都无法实现。因此，现有技术中，当系统封装中包含表面声波元件、体声波元件、表面声波元件或体声波元件等元件时，通常会于这些元件的周围形成一个空腔，使得封装材料无法与这些元件相接触，以避免上述问题。
如图15～图15C所示为一现有技术的一具体实施例的制作流程剖面图。图15中包括：一基板80、一声波元件81、一牺牲层82以及一第一SU8光阻层83。声波元件81形成于基板80上。牺牲层82形成在声波元件81以及基板80上且包覆住声波元件81。第一SU8光阻层83为牺牲层82形成在以及基板80上且包覆住第一SU8光阻层83。图15A中，第一SU8光阻层83被蚀刻出许多蚀刻孔86，且蚀刻孔86的底部为第一SU8光阻层83。图15B中，经由许多蚀刻孔86使一蚀刻液与牺牲层82相接触，以蚀刻去除牺牲层82而形成一空腔85。图15C中，于第一SU8光阻层83上形成一第二SU8光阻层84，其中蚀刻孔86亦被第二SU8光阻层84所填满，因而使得空腔85成为一密闭的空腔85。然而，当声波元件81所占的面积较大时，空腔85的面积亦需随之增大，此时会造成SU8光阻的结构强度不足，从而使第一SU8光阻层83及第二SU8光阻层84有可能呈现向下凹陷的情况。甚至，若第一SU8光阻层83的底部碰触到声波元件81，则会对声波元件81的元件特性造成不利影响。
有鉴于此，本案发明人开发出简便的设计，以克服上述缺点并兼顾使用弹性与经济性等考虑，因此遂有本发明的产生。
发明内容
本发明所欲解决的技术问题为于表面声波元件、体声波元件或微机电等元件的周遭形成一空腔，且该空腔的四周需具有高结构强度，以避免这些元件与该空腔的四周相接触而对元件的特性造成不利的影响。
为了解决上述问题以达到所预期的目的，本发明提供了一种具有半导体元件封装保护结构的堆栈芯片，其包括相互堆栈的一第一芯片以及一第二芯片，其中该第一芯片具有一第一表面，该第二芯片具有一第二表面，该第一表面以及该第二表面为两个相互面对面的表面，其中至少一金属凸块形成于该第一表面及该第二表面中的至少之一上且与该第一表面及该第二表面中的另一个相连接，至少一保护环形成于该第一表面及该第二表面中的至少之一上且与该第一表面及该第二表面中的另一个之间具有一第一间隙，以及至少一电子元件形成于该第一表面及该第二表面中的至少一之上，且该至少一电子元件位于该至少一保护环的至少之一所围绕的范围内。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中该第一间隙的尺寸大于1μm且小于30μm。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中该至少一保护环的高度大于1μm且小于100μm。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中构成该至少一保护环的材料包括以下至少之一：铜、金、锡、铟、金合金、铜合金、锡合金以及铟合金。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中构成该至少一保护环的材料包括以下至少之一：感光材料、光阻、SU8光阻以及压克力材料。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中该至少一保护环的厚度大于1μm且小于100μm。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中该至少一电子元件包括一表面声波元件、一体声波元件、一微机电元件以及一陀螺仪元件中的至少之一。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中构成该第一芯片的基板的材料包括以下之一：钽酸锂、铌酸锂、石英、硅、砷化镓、磷化镓、蓝宝石、氧化铝、磷化铟、碳化硅、钻石、氮化镓以及氮化铝。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中构成该第二芯片的基板的材料包括以下之一：钽酸锂、铌酸锂、石英、硅、砷化镓、磷化镓、蓝宝石、氧化铝、磷化铟、碳化硅、钻石、氮化镓以及氮化铝。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中构成该至少一金属凸块的材料包括以下至少之一：铜、金、金合金以及铜合金。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中该至少一金属凸块的上还镀有一熔接金属层，该至少一金属凸块通过该熔接金属层与该第一表面或该第二表面相连接。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中构成该熔接金属层的材料包括以下至少之一：铟、锡、铟合金以及锡合金。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中于该第一表面以及该第二表面上皆形成有该至少一保护环。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中形成于该第一表面上的该至少一保护环中的至少一个与上下相对位置相同处且形成于该第二表面上的该至少一保护环中的至少一个之间具有一第二间隙。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中该第二间隙的尺寸大于1μm且小于30μm。
于实施时，前述的具有半导体元件封装保护结构的堆栈芯片，其中该第一芯片堆栈于该第二芯片上或该第二芯片堆栈于该第一芯片上。
为进一步了解本发明，以下举较佳的实施例，配合图式、图号，将本发明的具体构成内容及其所达成的功效详细说明如下。
附图说明
图1～图1B分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图2、图2A分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图；
图2B为图2的具体实施例经封装后的剖面示意图；
图3～图3B分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图4～图4B分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图4C为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例芯片堆栈前的俯视图；
图5～图5C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图6～图6C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图7～图7B分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图8～图8C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图9～图9C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图10～图10C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图11～图11C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图12～图12C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图12D为图12的具体实施例经封装后的剖面示意图；
图13～图13C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图14～图14C分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图；
图15～图15C为一现有技术的一具体实施例的制作流程剖面图。
附图标记说明：1-第一芯片；10-第一芯片的基板；11-第一芯片的第一表面；12-第一芯片的金属凸块；13,13’-第一芯片的保护环；14-第一芯片的电子元件；15-第一芯片的熔接金属层；16-第一芯片的保护环的高度；17-第一芯片的保护环的厚度；2-第二芯片；20-第二芯片的基板；21-第二芯片的第二表面；22-第二芯片的金属凸块；23,23’-第二芯片的保护环；24-第二芯片的电子元件；25-第二芯片的熔接金属层；26-第二芯片的保护环的高度；27-第二芯片的保护环的厚度；3-堆栈芯片；4-第二芯片的保护环与第一芯片间的第一间隙；4’-第一芯片的保护环与第二芯片间的第一间隙；5-第二间隙；6-封装材料；7-空腔；80-基板；81-声波元件；82-牺牲层；83-第一SU8光阻层；84-第二SU8光阻层；85-空腔；86-蚀刻孔；a—a’、b—b’-剖面线；
具体实施方式
如1～图1B所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。堆栈芯片3包括一第一芯片1以及一第二芯片2。其中第一芯片1包括一第一基板10以及一第一表面11。第二芯片2包括一第二基板20、一第二表面21、至少一金属凸块22、一保护环23以及至少一电子元件24。其中第一芯片1的第一表面11与第二芯片2的第二表面21相互面对面。构成第一芯片1的基板10的材料包括以下之一：钽酸锂、铌酸锂、石英、硅、砷化镓、磷化镓、蓝宝石、氧化铝、磷化铟、碳化硅、钻石、氮化镓以及氮化铝。构成第二芯片2的基板20的材料包括以下之一：钽酸锂、铌酸锂、石英、硅、砷化镓、磷化镓、蓝宝石、氧化铝、磷化铟、碳化硅、钻石、氮化镓以及氮化铝。金属凸块22形成于第二芯片2的第二表面21上。构成金属凸块22的材料包括以下至少之一：铜、金、金合金以及铜合金。其中金属凸块22除了可用于第一芯片1及第二芯片2之间传递信号外，还可做为堆栈芯片3的支撑结构。保护环23形成于第二芯片2的第二表面21上。构成保护环23的材料包括以下至少之一：铜、金、锡、铟、金合金、铜合金、锡合金以及铟合金。构成保护环23的材料亦可包括以下至少之一：感光材料、光阻、SU8光阻以及压克力材料。电子元件24形成于第二芯片2的第二表面21上，其中电子元件24位于第二芯片2的保护环23所围绕的范围内，且其中金属凸块22亦位于第二芯片2的保护环23所围绕的范围内。电子元件24包括一表面声波元件、一体声波元件、一微机电元件以及一陀螺仪元件中的至少其中之一。其中第二芯片2堆栈于第一芯片1上而形成堆栈芯片3，使得第二芯片2的保护环23与第一芯片1之间具有一第一间隙4。其中第二芯片2的保护环23与第一芯片1之间的第一间隙4的尺寸大于1μm且小于30μm。
如图2、图2A所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图。此实施例的主要结构与图1～图1B所示的实施例大致相同，但是，其中金属凸块22上还镀有一熔接金属层25，金属凸块22通过熔接金属层25与第一芯片1的第一表面11相连接。构成熔接金属层25的材料包括选自以下至少之一：铟、锡、铟合金以及锡合金。其中保护环23的高度26大于1μm且小于100μm。保护环23的厚度27大于1μm且小于100μm。
如图2B所示为图2、图2A的具体实施例经封装后的剖面示意图。当要将第二芯片2堆栈至第一芯片1上时，第二芯片2于第二表面21这一面会先去沾黏一助焊剂，之后再将第二芯片2堆栈至第一芯片1上，使得金属凸块22通过熔接金属层25与第一芯片1的第一表面11相连接。此时仍有许多助焊剂留存在第二芯片2的第二表面21这一面上，需要被清除干净。第二芯片2的保护环23与第一芯片1之间的第一间隙4的功能就在于能为清除溶剂提供一间隙，使得清除溶剂能通过第一间隙4进入第二芯片2的保护环23所环绕的范围内，以清除残留的助焊剂。此外，第一间隙4还提供另一种功能，在封装时，若选择适当的一黏滞系数的一封装材料6，则堆栈芯片3经封装材料6封装后，封装材料6不会经由第一间隙4渗入保护环23所环绕的范围内，而是在保护环23所环绕的范围内形成一空腔7。此空腔7为电子元件24，如表面声波元件、体声波元件、微机电元件以及陀螺仪元件所需，使得电子元件24不会与封装材料6相接触，如此可确保电子元件24的元件特性不会受到影响。
在其他的实施例中，第一芯片1亦可堆栈于第二芯片2上；电子元件、保护环以及金属凸块却并不限定必须形成在第一芯片1或第二芯片2上；电子元件、保护环以及金属凸块可以只形成在第一芯片1的第一表面11上，或只形成在第二芯片2的第二表面21上，亦或是同时形成在第一芯片1的第一表面11上及第二芯片2的第二表面21上。
如图3～图3B所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图2、图2A所示的实施例大致相同，但是，其中第一芯片1堆栈于第二芯片2上而形成堆栈芯片3，使得第一芯片1的一保护环13与第二芯片2之间具有一第一间隙4’，且其中第一芯片1包括至少一金属凸块12、保护环13以及至少一电子元件14。金属凸块12形成于第一芯片1的第一表面11上。构成金属凸块12的材料包括以下至少之一：铜、金、金合金以及铜合金。其中金属凸块12除了可用于第一芯片1及第二芯片2之间传递信号外，还可做为堆栈芯片3的支撑结构。金属凸块12上镀有一熔接金属层15，金属凸块12通过熔接金属层15与第二芯片2的第二表面21相连接。构成熔接金属层25的材料包括以下至少之一：铟、锡、铟合金以及锡合金。保护环13形成于第一芯片1的第一表面11上。保护环13的高度16大于1μm且小于100μm。保护环13的厚度17大于1μm且小于100μm。构成保护环13的材料包括以下至少之一：铜、金、锡、铟、金合金、铜合金、锡合金以及铟合金。构成保护环13的材料亦可包括以下至少之一：感光材料、光阻、SU8光阻以及压克力材料。电子元件14形成于第一芯片1的第一表面11上，其中电子元件14位于第一芯片1的保护环13所围绕的范围内，且其中金属凸块12亦位于第一芯片1的保护环13所围绕的范围内。电子元件14包括一表面声波元件、一体声波元件、一微机电元件以及一陀螺仪元件中的至少其中之一。其中第一芯片1的保护环13与第二芯片2之间的第一间隙4’的尺寸大于1μm且小于30μm。其中第一间隙4’具有与前述第一间隙4相同的功能。
如图4～图4B所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图2、图2A所示的实施例大致相同，但是，其中金属凸块22位于第二芯片2的保护环23所围绕的范围外。
如图4C所示为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例芯片堆栈前的俯视图。此实施例的主要结构与图4～图4B所示的实施例大致相同，但是，其中部分金属凸块22位于第二芯片2的保护环23所围绕的范围内，而另一部分金属凸块22位于第二芯片2的保护环23所围绕的范围外。
如图5～图5C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图2、图2A所示的实施例大致相同，但是，其中于第一芯片1的第一表面11上及第二芯片2的第二表面21上分别形成金属凸块12及金属凸块22。在此实施例中，金属凸块12及金属凸块22并不存在于同一相对位置上。
如图6～图6C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图4～图4B所示的实施例大致相同，但是，其中于第一芯片1的第一表面11上及第二芯片2的第二表面21上分别形成金属凸块12及金属凸块22。在此实施例中，金属凸块12及金属凸块22并不存在于同一相对位置上。
如图7～图7B所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图2、图2A所示的实施例大致相同，但是，其中八个小区域的电子元件24分别位于八个第二芯片2的保护环23所围绕的范围内。
如图8～图8C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图7～图7B所示的实施例大致相同，但是，其中于第一芯片1的第一表面11上及第二芯片2的第二表面21上分别形成金属凸块12及金属凸块22，且于第一芯片1的第一表面11上及第二芯片2的第二表面21上亦分别形成保护环13及保护环23。在此实施例中，金属凸块12及金属凸块22并不存在于同一相对位置上，且保护环13及保护环23亦并不存在于同一相对位置上。八个小区域的电子元件24分别位于四个第一芯片1的保护环13所围绕的范围内以及四个第二芯片2的保护环23所围绕的范围内。
如图9～图9C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图2、图2A所示的实施例大致相同，但是，其中保护环13形成于第一芯片1的第一表面11上。
如图10～图10C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图7～图7B所示的实施例大致相同，但是，其中保护环13形成于第一芯片1的第一表面11上。八个小区域的电子元件24分别位于八个第一芯片1的保护环13所围绕的范围内。
如图11～图11C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图2、图2A所示的实施例大致相同，但是，其中于第一芯片1的第一表面11上及第二芯片2的第二表面21上分别形成电子元件14及电子元件24。相较于若只在一片芯片形成所有电子元件14及电子元件24，则同时分别于第一芯片1的第一表面11上及第二芯片2的第二表面21上去形成电子元件14及电子元件24的状况所占的面积将可减少一半，非常有利于缩小芯片的尺寸。
如图12～图12C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图11～图11C所示的实施例大致相同，但是，其中于第一芯片1的第一表面11上及第二芯片2的第二表面21上分别形成保护环13及保护环23。在此实施例中，保护环13及保护环23并不存在于同一相对位置上。八个小区域的电子元件14及八个小区域的电子元件24分别位于四个第一芯片1的保护环13所围绕的范围内以及四个第二芯片2的保护环23所围绕的范围内。
如图12D所示为图12～图12C的具体实施例经封装后的剖面示意图。堆栈芯片3经封装材料6封装后，于四个第一芯片1的保护环13所围绕的范围内以及四个第二芯片2的保护环23所围绕的范围内分别形成了八个空腔7。
如图13～图13C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图7图～图7B所示的实施例大致相同，但是，其中于第一芯片1的第一表面11上及第二芯片2的第二表面21上分别形成保护环13及保护环23，且只在第一芯片1的第一表面11上形成电子元件14，于第二芯片2的第二表面21上并未形成电子元件24。在此实施例中，保护环13及保护环23并不存在于同一相对位置上。八个小区域的电子元件24分别位于四个第一芯片1的保护环13所围绕的范围内以及四个第二芯片2的保护环23所围绕的范围内。
如图14～图14C所示分别为本发明提供的具有半导体元件封装保护结构的堆栈芯片的一具体实施例的剖面图以及芯片堆栈前的剖面分解图及俯视图。此实施例的主要结构与图12～图12C所示的实施例大致相同，但是，其中于第一芯片1的第一表面11上形成保护环13及保护环13’，且于第二芯片2的第二表面21上形成保护环23及保护环23’。在此实施例中，保护环13及保护环23并不存在于同一相对位置上；保护环13’及保护环23’却是位于同一相对位置上。第一芯片1的保护环13’与第二芯片2的保护环23’之间具有一第二间隙5。其中第二间隙5具有与前述第一间隙4相同的功能。其中第二间隙5的尺寸大于1μm且小于30μm。
以上所述是本发明的具体实施例及所运用的技术手段，根据本文的揭露或教导可衍生推导出许多的变更与修正，仍可视为本发明的构想所作的等效改变，其所产生的作用仍未超出说明书及图式所涵盖的实质精神，均应视为在本发明的技术范畴之内，合先陈明。

Claims (16)

1.一种具有半导体元件封装保护结构的堆栈芯片，其特征在于，包括：
相互堆栈的一第一芯片以及一第二芯片，其中该第一芯片具有一第一表面，该第二芯片具有一第二表面，该第一表面以及该第二表面为两个相互面对面的表面，其中至少一金属凸块形成于该第一表面及该第二表面中的至少之一上且与该第一表面及该第二表面中的另一个相连接，至少一保护环形成于该第一表面及该第二表面中的至少之一上且与该第一表面及该第二表面中的另一个之间具有一第一间隙，以及至少一电子元件形成于该第一表面及该第二表面中的至少之一上，且该至少一电子元件位于该至少一保护环的至少之一所围绕的范围内，其中一空腔由该第一表面、该第二表面以及该至少一保护环所环绕而形成，其中该空腔通过该第一间隙与外界相连通。
2.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，该第一间隙的尺寸大于1μm且小于30μm。
3.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，该至少一保护环的高度大于1μm且小于100μm。
4.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，构成该至少一保护环的材料包括以下至少之一：铜、金、锡、铟、金合金、铜合金、锡合金以及铟合金。
5.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，构成该至少一保护环的材料包括以下至少之一：感光材料、光阻、SU8光阻以及压克力材料。
6.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，该至少一保护环的厚度大于1μm且小于100μm。
7.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，该至少一电子元件包括一表面声波元件、一体声波元件、一微机电元件以及一陀螺仪元件中的至少之一。
8.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，构成该第一芯片的基板的材料包括以下之一：钽酸锂、铌酸锂、石英、硅、砷化镓、磷化镓、蓝宝石、氧化铝、磷化铟、碳化硅、钻石、氮化镓以及氮化铝。
9.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，构成该第二芯片的基板的材料包括以下之一：钽酸锂、铌酸锂、石英、硅、砷化镓、磷化镓、蓝宝石、氧化铝、磷化铟、碳化硅、钻石、氮化镓以及氮化铝。
10.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，构成该至少一金属凸块的材料包括以下至少之一：铜、金、金合金以及铜合金。
11.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，该至少一金属凸块上还镀有一熔接金属层，该至少一金属凸块通过该熔接金属层与该第一表面或该第二表面相连接。
12.根据权利要求11所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，构成该熔接金属层的材料包括以下至少之一：铟、锡、铟合金以及锡合金。
13.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，于该第一表面以及该第二表面上皆形成有该至少一保护环。
14.根据权利要求13所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，形成于该第一表面上的该至少一保护环中的至少一个与上下相对位置相同处且形成于该第二表面之上的该至少一保护环中的至少一个之间具有一第二间隙。
15.根据权利要求14所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，该第二间隙的尺寸大于1μm且小于30μm。
16.根据权利要求1所述的具有半导体元件封装保护结构的堆栈芯片，其特征在于，该第一芯片堆栈于该第二芯片上或该第二芯片堆栈于该第一芯片上。
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