CN106710544B

CN106710544B - Shift register circuit, gate drive circuit and display device

Info

Publication number: CN106710544B
Application number: CN201611137653.XA
Authority: CN
Inventors: 李骏
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2016-12-12
Filing date: 2016-12-12
Publication date: 2019-12-31
Anticipated expiration: 2036-12-12
Also published as: CN106710544A

Abstract

The invention provides a shift register circuit, a grid drive circuit and a display device, wherein the shift register circuit comprises: the input module is connected to the signal input end, the first clock signal end and the first node and used for outputting an input signal to the first node under the control of the first clock signal and the input signal; the energy storage module is connected between the first node and the signal output end and used for storing and maintaining the voltage signal of the first node; the pull-down module is connected to the first node, the first voltage end, the second clock signal end, the third clock signal end and the signal output end and is used for outputting the second clock signal to the signal output end under the control of the voltage of the first node; the pull-up module is connected to the first node, the third clock signal terminal, the first voltage terminal, the second voltage terminal and the signal output terminal, and is configured to output a second voltage signal of the second voltage terminal to the signal output terminal under the control of the third clock signal.

Description

Shift register circuit, gate drive circuit and display device

Technical Field

The present invention relates generally to the field of display technologies, and more particularly, to a shift register circuit, a gate driving circuit and a display device.

Background

Liquid Crystal Displays (LCDs) and Active Matrix Driving Organic Light Emitting Diode (OLED) displays are widely used in the field of high performance displays due to their advantages of high Display quality, low price, convenience in carrying, and the like.

At present, the panel driving technology of the liquid crystal display or the active matrix organic light emitting diode display tends to adopt the GOA (gate Drive on array) technology, i.e. the array substrate driving technology, which is a driving mode of realizing line-by-line scanning on the substrate by using the thin film transistor array. Specifically, the GOA circuit may output a gate scan driving signal to drive a gate line in the panel, and turn on a Thin Film Transistor (TFT) in the display region to charge the pixel. The GOA technology can simplify the manufacturing process of the flat panel display panel, improve the yield, reduce the product cost, and simultaneously improve the integration level of the display panel so that the display panel is more suitable for manufacturing narrow-frame display products to meet the visual pursuit of modern people.

However, for the flexible OLED display, since the voltage drift needs to be suppressed, more gate scan driving signals need to be provided, but the existing display device provided with the GOA circuit cannot provide more gate scan driving signals.

Disclosure of Invention

In view of the above, the present invention provides a shift register circuit, a gate driving circuit and a display device, so as to solve the problem that the conventional display device provided with a GOA circuit cannot provide more gate scanning signals to suppress voltage drift.

According to an aspect of exemplary embodiments of the present invention, there is provided a shift register circuit, including: the input module is connected to the signal input end, the first clock signal end and the first node and used for outputting a voltage signal of the signal input end to the first node under the control of a first clock signal and an input signal; the energy storage module is connected between the first node and the signal output end and used for storing and maintaining the voltage signal of the first node; the pull-down module is connected to the first node, the first voltage end, the second clock signal end, the third clock signal end and the signal output end and is used for outputting a second clock signal to the signal output end under the control of the voltage signal of the first node; the pull-up module is connected to the first node, the third clock signal terminal, the first voltage terminal, the second voltage terminal and the signal output terminal, and is configured to output a second voltage signal of the second voltage terminal to the signal output terminal under the control of the third clock signal.

Optionally, the input module comprises a first transistor and a second transistor, wherein a gate and a first pole of the first transistor are connected to the signal input terminal, and a second pole is connected to a first pole of the second transistor; and the grid electrode of the second transistor is connected to the first clock signal end, and the second pole of the second transistor is connected to the first node, wherein the first transistor and the second transistor are PMOS transistors.

Optionally, the energy storage module comprises a first capacitor, wherein one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the signal output end.

Optionally, the pull-down module includes a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to a third clock signal terminal, a first pole is connected to the first node, and a second pole is connected to a first voltage terminal; and a gate of the fourth transistor is connected to the first node, a first pole is connected to the signal output end, and a second pole is connected to the second clock signal end, wherein the third transistor and the fourth transistor are PMOS transistors.

Optionally, the pull-up module includes a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor, wherein a gate of the fifth transistor is connected to the third clock signal terminal, a first pole is connected to the second voltage terminal, and a second pole is connected to the second node; a gate of the sixth transistor is connected to the second node, a first pole is connected to the first voltage terminal, and a second pole is connected to the signal output terminal; a gate of the seventh transistor is connected to the first node, a first pole is connected to the second node, and a second pole is connected to the first voltage terminal; and one end of the second capacitor is connected to the second voltage end, and the other end of the second capacitor is connected to the second node, wherein the fifth transistor, the sixth transistor and the seventh transistor are PMOS transistors.

Optionally, a level of the first voltage signal of the first voltage terminal is higher than a level of the second voltage signal of the second voltage terminal.

According to another aspect of exemplary embodiments of the present invention, there is provided a gate driving circuit, comprising a plurality of stages of shift register circuits, each stage of shift register circuit being a shift register circuit as described above, wherein a signal input terminal of each stage of shift register circuit is connected to a signal output terminal of a previous stage of shift register circuit, and a signal input terminal of a first stage of shift register circuit is connected to a start driving signal input terminal.

According to another aspect of exemplary embodiments of the present invention, there is provided a display device including the gate driving circuit as described above.

According to the shift register circuit, the gate drive circuit and the display device of the shift register circuit, the number of transistors can be reduced, and more line scanning drive signals can be provided through the shift register, so that the manufacturing process is saved, and the production efficiency is improved.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

fig. 1 shows a schematic configuration diagram of a shift register circuit according to an exemplary embodiment of the present invention;

fig. 2 shows an example of a shift register circuit according to an exemplary embodiment of the present invention;

fig. 3 illustrates a signal timing diagram of a shift register circuit according to an exemplary embodiment of the present invention;

fig. 4 illustrates a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present invention.

Detailed Description

Various exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which some exemplary embodiments are shown, and in which like reference numerals refer to like parts throughout.

Fig. 1 illustrates a schematic configuration diagram of a shift register circuit according to an exemplary embodiment of the present invention.

As shown in fig. 1, a shift register circuit according to an exemplary embodiment of the present invention includes: an input module 10, an energy storage module 20, a pull-up module 30 and a pull-down module 40.

Specifically, the input module 10 is connected to a signal input terminal IN, a first clock signal terminal, and a first node M, for outputting a voltage signal of the signal input terminal IN to the first node M under control of the first clock signal and an input signal. Here, the first clock signal terminal receives the first clock signal from the clock signal line CK 1.

The energy storage module 20 is connected between the first node M and the signal OUTPUT terminal OUTPUT, and is configured to store and maintain the voltage signal of the first node M.

The pull-down module 30 is connected to the first node M, the first voltage terminal VGH, the second clock signal terminal, the third clock signal terminal, and the signal OUTPUT terminal OUTPUT, and is configured to OUTPUT the second clock signal to the signal OUTPUT terminal OUTPUT under the control of the voltage signal of the first node M. Here, the second and third clock signal terminals receive the second and third clock signals from the clock signal line CK2 and the clock signal line CK3, respectively.

The pull-up module 40 is connected to the first node M, the third clock signal terminal, the first voltage terminal VGH, the second voltage terminal VGL, and the signal OUTPUT terminal OUTPUT, and is configured to OUTPUT the second voltage signal of the second voltage terminal VGL to the signal OUTPUT terminal OUTPUT under the control of the third clock signal.

Here, as an example, the level of the first voltage signal of the first voltage terminal VGH is higher than the level of the second voltage signal of the second voltage terminal VGL.

As can be seen from the above description, the signal OUTPUT terminal OUTPUT may be controlled to OUTPUT the corresponding gate scan driving signal according to actual conditions.

The specific structure of each block in the shift register circuit is illustrated in detail by specific embodiments.

Fig. 2 illustrates an example of a shift register circuit according to an exemplary embodiment of the present invention.

As shown IN fig. 2, the input module 10 includes a first transistor T1 and a second transistor T2, wherein a gate and a first pole of the first transistor T1 are connected to the signal input terminal IN, and a second pole is connected to a first pole of the second transistor T2; the gate of the second transistor T2 is connected to the first clock signal terminal, and the second pole is connected to the first node M, where the first transistor T1 and the second transistor T2 are PMOS transistors.

The energy storage module 20 comprises a first capacitor C1, wherein one end of the first capacitor C1 is connected to the first node M and the other end is connected to the signal OUTPUT terminal OUTPUT.

The pull-down module 30 includes a third transistor T3 and a fourth transistor T4, wherein a gate of the third transistor T3 is connected to the third clock signal terminal, a first pole is connected to the first node M, and a second pole is connected to the first voltage terminal VGH; the fourth transistor T4 has a gate connected to the first node M, a first pole connected to the signal OUTPUT terminal OUTPUT, and a second pole connected to the second clock signal terminal, where the third transistor T3 and the fourth transistor T4 are PMOS transistors.

The pull-up module 40 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a second capacitor C2, wherein a gate of the fifth transistor T5 is connected to the third clock signal terminal, a first pole is connected to the second voltage terminal VGL, and a second pole is connected to the second node N; a gate of the sixth transistor T6 is connected to the second node N, a first pole is connected to the first voltage terminal VGH, and a second pole is connected to the signal OUTPUT terminal OUTPUT; a gate of the seventh transistor is connected to the first node M, a first pole is connected to the second node N, and a second pole is connected to the first voltage terminal VGH; one end of the second capacitor C2 is connected to the second voltage terminal VGL and the other end is connected to the second node N, where the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are PMOS transistors.

Fig. 3 illustrates a signal timing diagram of a shift register circuit according to an exemplary embodiment of the present invention.

Hereinafter, the operation states of the respective devices in the shift register circuit shown in fig. 2 will be described in detail with reference to fig. 3. It should be noted that, in the exemplary embodiment of the present invention, the first voltage terminal VGH is inputted with a high level, and the second voltage terminal VHL is inputted with a low level or grounded, for example, the on and off processes of the transistors in the exemplary embodiment of the present invention are all described by taking all transistors as PMOS type transistors as an example.

IN the first stage of the shift register circuit operation, IN is 0, CK1 is 0, CK2 is 1, and CK3 is 1; where "0" represents a low level signal and "1" represents a high level signal.

Since the signal input terminal IN inputs a low level signal, the first transistor T1 is turned on, the first clock signal terminal receives the first clock signal of low level from the clock signal line CK1, the second transistor T2 is turned on, and at this time, the low level signal of the signal input terminal IN is output to the first node M, and the first capacitor C1 stores and holds the low level signal of the signal input terminal IN; since the third clock signal terminal receives the third clock signal of high level from the clock signal line CK3, the third transistor T3 is turned off, the fifth transistor T5 is turned off, the gate of the seventh transistor T7 is turned on by receiving the low level signal of the first node M, at this time, the high level signal of the first voltage terminal VGH is OUTPUT to the gate of the sixth transistor T6 via the turned-on seventh transistor T7, the sixth transistor T6 is turned off, the second capacitor C2 stores and holds the high level signal of the first voltage terminal VGH, the fourth transistor T4 is turned on by receiving the low level signal of the first node M at its gate, so that the second clock signal of high level, which the second clock signal terminal receives from the clock signal line CK2, is OUTPUT to the signal OUTPUT terminal put, at this time, the OUTPUT signal of the signal OUTPUT terminal put is a high level signal.

IN the second stage of the shift register circuit operation, IN is 1, CK1 is 1, CK2 is 0, and CK3 is 1.

Since the signal input terminal IN inputs a high level signal and the first clock signal terminal receives the first clock signal of a high level from the clock signal line CK1, the first transistor T1 and the second transistor T2 are turned off; since the third clock signal terminal receives the third clock signal of a high level from the clock signal line CK3, the third transistor T3 and the fifth transistor T5 are turned off, the gate of the sixth transistor T6 is in a turned-off state due to the reception of the high level signal of the previous stage held by the second capacitor C2, and the gate of the fourth transistor T4 is turned on due to the reception of the low level signal of the first stage held by the first capacitor C1, so that the signal OUTPUT terminal OUTPUT OUTPUTs the second clock signal of a low level received by the second clock signal terminal from the clock signal line CK 2. In addition, the seventh transistor T7 may also be turned on due to its gate receiving the low level signal of the first stage held by the first capacitor C1, but does not affect the OUTPUT signal of the OUTPUT terminal OUTPUT.

IN the third stage of the shift register circuit operation, IN is 1, CK1 is 1, CK2 is 1, and CK3 is 0.

Since the signal input terminal IN inputs a high level and the first clock signal terminal receives the first clock signal of the high level from the clock signal line CK1, the first transistor T1 and the second transistor T2 are turned off; since the third clock signal terminal receives the third clock signal of a low level from the clock signal line CK3, the third transistor T3 and the fifth transistor T5 are turned on, the first capacitor C1 stores and holds the high level signal inputted from the first voltage terminal VGH, the second capacitor C2 stores and holds the low level signal inputted from the second voltage terminal VGL, and the gate of the sixth transistor T6 is turned on by receiving the low level signal inputted from the second voltage terminal VGL through the turned-on fifth transistor T5, so that the signal OUTPUT terminal OUTPUT OUTPUTs the high level signal inputted from the first voltage terminal VGH. In addition, the fourth transistor T4 and the seventh transistor T7 are turned off by receiving the high level signal inputted from the first voltage terminal VGH through the turned-on third transistor T3 at their gates, and thus do not affect the OUTPUT signal of the OUTPUT terminal OUTPUT.

As shown in fig. 4, the gate driving circuit according to the exemplary embodiment of the present invention may be a GOA circuit, and the GOA circuit includes multiple stages of the shift register circuits as described above, and since the structure of the shift register circuit has been described in detail in the foregoing embodiments, the details are not repeated herein.

Specifically, the signal input terminal of each stage of the shift register circuit is connected to the signal output terminal of the previous stage of the shift register circuit, and the signal input terminal IN of the first stage of the shift register circuit is connected to the start driving signal input terminal STV. Here, the start driving signal STV is used to drive the GOA circuit to sequentially output a scan driving signal to each gate line (G1, G2 · Gn).

Further, in order to cause the GOA circuit to sequentially output the scan driving signals to the respective gate lines (G1, G2 · · · · Gn), the clock signals of the clock signal lines CK1, CK2, and CK3 are alternately output to the shift register circuits of the respective stages as the first clock signal, the second clock signal, and the third clock signal. For example, a clock signal of the clock signal line CK1 is output as a first clock signal, a clock signal of the clock signal line CK2 is output as a second clock signal, and a clock signal of the clock signal line CK3 is output as a third clock signal to the first stage shift register circuit; a clock signal of the clock signal line CK1 is output to the second stage shift register circuit as a third clock signal, a clock signal of the clock signal line CK2 is output as a first clock signal, and a clock signal of the clock signal line CK3 is output as a second clock signal; the clock signal of the clock signal line CK1 is output to the third stage shift register circuit as the second clock signal, the clock signal of the clock signal line CK2 is output as the third clock signal, the clock signal of the clock signal line CK3 is output as the first clock signal, and so on. Meanwhile, for the first stage shift register circuit, the start drive signal STV should be synchronized with the clock signal of the clock signal line CK 1.

By the mode, the shift register function can be realized, and when one grid scanning driving signal is output, the next grid scanning driving signal is output through clock control and is sequentially transmitted.

Due to the adoption of the shift register circuit with all PMOS transistors, the number of transistors required by the GOA circuit is obviously reduced, and narrow-frame design is facilitated. In addition, the adoption of the full PMOS transistor can effectively save the manufacturing process and improve the production efficiency.

In addition, exemplary embodiments of the present invention also provide a display device including the gate driving circuit as described above. Since the foregoing embodiments have described the structure of the gate driving circuit in detail, the description is omitted here.

It is to be understood that the scope of the present invention is not limited to the specific embodiments disclosed, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register circuit, comprising: an input module, an energy storage module, a pull-up module and a pull-down module, wherein,

the input module is connected to the signal input end, the first clock signal end and the first node and used for outputting a voltage signal of the signal input end to the first node under the control of the first clock signal and the input signal;

the energy storage module is connected between the first node and the signal output end and used for storing and maintaining the voltage signal of the first node;

the pull-down module is connected to the first node, the first voltage end, the second clock signal end, the third clock signal end and the signal output end and is used for outputting a second clock signal to the signal output end under the control of the voltage signal of the first node;

the pull-up module is connected to the first node, the third clock signal terminal, the first voltage terminal, the second voltage terminal and the signal output terminal, and is used for outputting a second voltage signal of the second voltage terminal to the signal output terminal under the control of the third clock signal;

the pull-down module comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor is connected to a third clock signal end, the first pole of the third transistor is connected to the first node, and the second pole of the third transistor is connected to the first voltage end; a gate of the fourth transistor is connected to the first node, a first pole of the fourth transistor is connected to the signal output end, and a second pole of the fourth transistor is connected to the second clock signal end, wherein the third transistor and the fourth transistor are PMOS transistors;

the pull-up module comprises a fifth transistor, a sixth transistor, a seventh transistor and a second capacitor, wherein the gate of the fifth transistor is connected to the third clock signal terminal, the first pole is connected to the second voltage terminal, and the second pole is connected to the second node; a gate of the sixth transistor is connected to the second node, a first pole is connected to the first voltage terminal, and a second pole is connected to the signal output terminal; a gate of the seventh transistor is connected to the first node, a first pole is connected to the second node, and a second pole is connected to the first voltage terminal; and one end of the second capacitor is connected to the second voltage end, and the other end of the second capacitor is connected to the second node, wherein the fifth transistor, the sixth transistor and the seventh transistor are PMOS transistors.

2. The shift register circuit of claim 1, wherein the input block includes a first transistor and a second transistor, wherein,

a gate and a first pole of the first transistor are connected to the signal input terminal, and a second pole of the first transistor is connected to the first pole of the second transistor;

a gate of the second transistor is connected to a first clock signal terminal, a second pole is connected to the first node,

the first transistor and the second transistor are PMOS transistors.

3. The shift register circuit of claim 1, wherein the energy storage block comprises a first capacitor, wherein one end of the first capacitor is connected to the first node and the other end is connected to a signal output terminal.

4. The shift register circuit according to claim 1, wherein a level of the first voltage signal of the first voltage terminal is higher than a level of the second voltage signal of the second voltage terminal.

5. A gate driver circuit comprising a plurality of stages of shift register circuits, each of the stages of shift register circuits being the shift register circuit according to any one of claims 1 to 4,

the signal input end of each stage of shift register circuit is connected with the signal output end of the previous stage of shift register circuit, and the signal input end of the first stage of shift register circuit is connected with the initial driving signal input end.

6. A display device comprising the gate driver circuit according to claim 5.