CN106548741A - Shift register and time sequence control method thereof - Google Patents

Abstract

A shift register and a time sequence control method thereof are provided, wherein the shift register comprises a plurality of first shift register units. The first shift register unit comprises a first pull-up circuit and a first pull-down circuit. The first shift register unit includes a first clamp circuit including a first transistor and a second transistor. The main control end of the first transistor is electrically connected with the external signal end, and the first end of the first transistor receives the second clock pulse signal. The main control end of the second transistor is electrically connected to the second end of the first transistor, the first end of the second transistor is electrically connected to the first control signal of the first shift register unit, and the second end of the second transistor receives the reference voltage. The invention also provides a time sequence control method of the shift register.

Description

A shift register and its timing control method

technical field

The invention relates to a shift register and a timing control method thereof, in particular to a shift register aimed at stress effects and a timing control method thereof.

Background technique

Under the environment of increasingly fierce competition in the panel industry, the goal pursued by major panel manufacturers is to make the panel size light, thin and short. In order to achieve the narrow frame of the panel and reduce the cost, integrating the gate driver IC (Gate Driver IC) on the glass substrate, that is, the technology of GOA (Gate Driver on Array) has become an important research direction. As far as the current actual circuit design is concerned, the last multiple shift register circuits need to rely on external signals to perform the pull-down action. However, due to current technology, cost and space considerations, external signals are limited. Therefore, the stress effect of the subsequent shift register circuits is more significant than that of the front shift register circuits, thereby reducing the lifespan of the panel product.

Contents of the invention

The technical problem to be solved by the present invention is to provide a shift register and its timing control method, which can reduce the stress effect on multiple shift register circuits at the back of the panel, so as to prolong the life of panel products.

In order to achieve the above object, the present invention provides a shift register, which includes N first shift register units, the N first shift register units are connected in series, and N is an integer greater than 1, wherein the first The first shift register unit of the i stage includes a first pull-up circuit and a first pull-down circuit. The first pull-up circuit adjusts the first output signal to the potential of the first clock signal according to the first control signal of the first shift register unit of the i-th stage. The first pull-down circuit adjusts the first output signal and the first control signal to the reference voltage according to the first control signal and the pull-down signal of the first shift register unit of the i-th stage. Wherein i is a positive integer less than or equal to N, and the first shift register unit of the Nth stage further includes a first clamping circuit. The first clamping circuit includes a first transistor and a second transistor. The first transistor has a main control terminal, a first terminal and a second terminal. The main control end of the first transistor is electrically connected to the external signal end. The first terminal of the first transistor receives the second clock signal. The second transistor has a main control terminal, a first terminal and a second terminal. The main control end of the second transistor is electrically connected to the second end of the first transistor. The first end of the second transistor is electrically connected to the first control signal of the first shift register unit of the Nth stage. The second end of the second transistor receives a reference voltage.

In order to better achieve the above object, the present invention also provides a timing control method of a shift register, including an external signal at the negative of the first clock signal of the first shift register unit of the Nth stage edge before switching from a low voltage to a high voltage.

In order to better achieve the above object, the present invention also provides a shift register, including a pull-up circuit, a pull-down circuit and a first clamping circuit. The pull-up circuit adjusts the output signal to the potential of the first clock signal according to the control signal. The pull-down circuit adjusts the output signal and the control signal to the reference voltage according to the control signal and the pull-down signal. The first clamping circuit includes a first transistor and a second transistor. The first transistor has a main control terminal, a first terminal and a second terminal. The main control end of the first transistor is electrically connected to the external signal end. The first terminal of the first transistor receives the second clock signal. The second transistor has a main control terminal, a first terminal and a second terminal. The main control end of the second transistor is electrically connected to the second end of the first transistor. The first end of the second transistor is electrically connected to the control signal. A second terminal of the second transistor receives a reference voltage.

Technical effect of the present invention is:

Based on the above, the shift register and its timing control method proposed by the present invention, through the setting of the first transistor of the first clamping circuit, and with timing control, make the Nth stage in the shift register The stress effect suffered by the first shift temporary storage unit is reduced.

The present invention will also be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

FIG. 1 is a structural diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a schematic block diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a first shift register unit according to an embodiment of the present invention;

5 is a schematic circuit diagram of a first shift register unit according to an embodiment of the present invention;

FIG. 6 is a timing control waveform diagram according to an embodiment of the present invention;

7 is a schematic circuit diagram of a second shift register according to another embodiment of the present invention;

8 is a schematic circuit diagram of a first shift register unit according to another embodiment of the present invention;

9 is a schematic circuit diagram of a second shift register unit according to another embodiment of the present invention;

FIG. 10A is a structural diagram of a shift register according to another embodiment of the present invention;

FIG. 10B is a schematic circuit diagram of shift register units from the first stage to the fourth stage shown in the embodiment of FIG. 10A according to the present invention;

FIG. 10C is a schematic circuit diagram of shift register units from the fifth level to the (n-4)th level shown in the embodiment of FIG. 10A according to the present invention;

FIG. 10D is a schematic circuit diagram of shift register units from the (n-3)th level to the nth level shown in the embodiment of FIG. 10A according to the present invention;

FIG. 11 is a timing control waveform diagram of an external signal and a first control signal according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a part of the display panel according to an embodiment of the present invention.

Among them, reference signs

1, 2: shift register

1_C: charging structure

1_S: Charge sharing structure

1_DMC: Virtual charging structure

1_FDMS: front-end virtual charge sharing structure

1_RDMS: back stage virtual charge sharing structure

2_1～2_N: shift temporary storage unit

10-_1～10-_1088: the first shift temporary storage unit

12_1～12_1096: The second shift temporary storage unit

20: Display panel

LC1, LC2: pull-down signal

102: The first pull-up circuit

202: Second pull-up circuit

104: The first pull-down circuit

204: Second pull-down circuit

106, 106_1: the first clamping circuit

206: Second clamping circuit

306: The third clamping circuit

Q(5), Qdm(1088), Qsdm(1095), Qsdm(1096): the first control signal

G(5), Gdm(1088), Sdm(1095), Sdm(1096): the first output signal

HC1～HC8, HC(n－4), HC(n+4): clock signal

G(9): output signal

Q(n): control signal

T11～T64: Transistors

ST, ST(n-4), ST(n+4): external signal

S_ST: external signal terminal

S1～S1080: scanning line

VGHD: Voltage

VSS, VSSQ: reference voltage

C-_PE: Negative edge of the first clock signal

C-_NE: Positive edge of the first clock signal

Q-_PE1～Q-_PE4: positive edge of the first control signal

P1: the first period

P2: the second period

P3: the third period

t1: time point

detailed description

Below in conjunction with accompanying drawing, structural principle and working principle of the present invention are specifically described:

Please refer to FIG. 1 . FIG. 1 is a structural diagram of a shift register according to an embodiment of the present invention. As shown in FIG. 1 , the shift register 1 includes a charging structure 1_C and a charge sharing structure 1_S. In this embodiment, the charging structure 1_C includes a plurality of first shift register units 10_1˜10_1088. The charge sharing structure 1_S includes a plurality of second shift register units 12_1˜12_1096. The virtual charging structure 1_DMC in the charging structure 1_C is the first shift register unit 10_1081˜10_1088 including the last eight stages. The front dummy charge sharing structure 1_FDMS in the charge sharing structure 1_S is the second shift register unit 12_1 - 12_8 including the first eight stages. The second stage of the dummy charge sharing structure 1_RDMS includes the last eight stages of the second shift register units 12_1089˜12_1096. Please refer to FIG. 2 . FIG. 2 is a schematic block diagram of a shift register according to an embodiment of the present invention. As shown in FIG. 2 , in the charging structure 1_C, a plurality of first shift register units 10_1 - 10_1088 included in the shift register 1 are connected in series with each other. Please refer to FIG. 3 . FIG. 3 is a schematic block diagram of a shift register according to an embodiment of the present invention. As shown in FIG. 3 , the plurality of second shift register units 12_1 - 12_1096 included in the shift register 1 are connected in series with each other. In this embodiment, the shift register 1 has a one-to-three and five-to-one structure. For example, the first shift register unit 10_1 transmits its output signal G(1) to the first shift register unit 10_3 as an activation signal, and the first shift register unit 10_5 is used to control the first shift register unit 10_5 The pull-down of the output signal G(1) of the storage unit 10_1.

In one embodiment, the shift register 1 includes a charging structure 1_C and a charge sharing structure 1_S. In another embodiment, the shift register 1 only includes the charging structure 1_C. Please refer to FIG. 2 and FIG. 4 together. FIG. 4 is a schematic circuit diagram of a first shift register unit according to an embodiment of the present invention, which corresponds to the first shift register unit 10_5 of the fifth stage. . As shown in FIG. 4 , the first shift register unit 10_5 of the fifth stage includes a first pull-up circuit 102 and a first pull-down circuit 104 . The first pull-up circuit 102 adjusts the first output signal G(5) to the potential of the clock signal HC5 according to the first control signal Q(5) of the first shift register unit of the fifth stage. In one embodiment, when the first control signal Q(5) is at a high potential, the transistor T21 is turned on. At this moment, the first output signal G(5) is adjusted to the clock signal HC5.

The first pull-down circuit 104 combines the first output signal G(5) with the first control signal Q (5) Adjust to the reference voltage VSS. In one embodiment, when the potential of at least one of the pull-down signal LC1 or the pull-down signal LC2 is at a high level, the potentials of the first control signal Q(5) and the first output signal G(5) are adjusted to Reference voltage VSS. As shown in FIG. 4 , the first shift register unit 10_5 of the fifth stage further includes a first clamping circuit 106 . The first clamping circuit 106 includes a transistor T41 and a transistor T31. The main control terminal of the transistor T41 is electrically connected to the output signal G(9), the first terminal is electrically connected to the first control signal Q(5), and the second terminal receives the reference voltage VSS. The main control end of the transistor T31 is electrically connected to the output signal G(9), the first end is electrically connected to the first output signal G(5), and the second end receives the reference voltage VSS. The first clamping circuit 106 adjusts the first output signal G(5) and the first control signal Q(5) to the reference voltage VSS according to the output signal G(9). The first shift register unit 10_5 of the fifth stage is only for illustration. In one embodiment, the first shift register units of other stages included in the shift register 1 of the present invention have the same structure.

Please refer to FIG. 5 . FIG. 5 is a schematic circuit diagram of a first shift register unit according to an embodiment of the present invention, which corresponds to the first shift register unit 10_1088 of the 1088th stage in the architecture of FIG. 2 . Except that the first shift register unit 10_1088 of the 1088th stage has the same circuit structure as the first shift register unit 10_5 of the fifth stage, the first clamping circuit 106 it includes is different from that of the first to 1087 The first clamping circuit 106 included in the stage. As shown in FIG. 5 , the first clamping circuit 106 in the first shift register unit 10_1088 of the 1088th stage includes a transistor T44 and a transistor T41 . The transistor T44 has a master terminal, a first terminal and a second terminal. The master terminal of the transistor T44 is electrically connected to the external signal terminal S_ST. The first end of the transistor T44 receives the clock signal HC4. The transistor T41 has a main control terminal, a first terminal and a second terminal. The master terminal of the transistor T41 is electrically connected to the second terminal of the transistor T44. The first end of the transistor T41 is electrically connected to the first control signal Qdm (1088) of the first shift register unit 10_1088 of the 1088th stage. The second terminal of the transistor T41 receives the reference voltage VSS. In one embodiment, the clock signal HC4 is the clock signal of the first shift register unit 10_1084 of the 1084th stage. In one embodiment, the on-resistance of the transistor T41 is greater than the on-resistance of the transistor T44. In this embodiment, when the external signal ST provided by the external signal terminal S_ST is at a high potential and the clock signal HC4 is at a low potential, the transistor T41 is not turned on. When the external signal ST provided by the external signal terminal S_ST is high and the clock signal HC4 changes from low to high, the first control signal Qdm ( 1088 ) is adjusted to the reference voltage VSS.

Specifically, please refer to FIG. 5 and FIG. 6 together. FIG. 6 is a timing control waveform diagram according to an embodiment of the present invention. As shown in Figure 5 and Figure 6, when the external signal ST is at a high potential and the clock signal HC4 is at a low potential, the transistor T41 is not turned on, so that the first control signal Qdm (1088) is in the first phase P1 to the third Phase P3 maintains a high potential. When both the external signal ST and the clock signal HC4 are at a high potential, the transistor T41 is turned on. The first control signal Qdm (1088) is pulled down to the reference voltage VSS. In this way, the time of the first control signal Qdm (1088) in the third phase P3 is shortened, as shown in FIG. 6 . That is to say, the first shift register unit 10_1088 of the 1088th stage cooperates with the clock signal HC4 and pulls down the potential of the first control signal Qdm (1088) to the reference voltage VSS at the time point t1. At this time, the first control The time of the signal Qdm (1088) in the third stage P3 is roughly shortened (approximately 14.4 microseconds) to be equal to the first stage P1 and the second stage P2, thereby reducing the time required by the first shift register unit 10_1088 of the 1088th stage The stress effect received. In the above embodiment, the shift register 1 only includes the charging structure 1_C, and the first shift register units 10_1081-10_1088 of the last eight stages are virtual shift register units, and the first shift register units of the 1088th stage The first clamping circuit 106 in a shift register unit 10_1088 has the arrangement of the transistor T44 as shown in FIG. 5 , which can be used to reduce the stress effect on the first shift register unit 10_1088 of the 1088th stage. In another embodiment, the shift register 1 also only includes the charging structure 1_C, but does not have the virtual last eight first shift register units 10_1081˜10_1088. That is to say, in this embodiment, the charging structure 1_C of the shift register 1 has only the first shift register units 10_1˜10_1080, wherein the first shift register unit 10_1080 of the 1080th stage A clamping circuit 106 is configured with the transistor T44 of FIG. 5 to reduce the stress effect on the first shift register unit 10_1080 of the 1080th stage.

In one embodiment, the first clamping circuit 106 of the shift register 1 further includes a transistor T31 having a master control terminal, a first terminal and a second terminal. The master terminal of the transistor T31 is electrically connected to the second terminal of the transistor T44, and the first terminal of the transistor T31 is electrically connected to the first output signal Gdm (1088). The second terminal of the transistor T31 receives the reference voltage VSS. In practice, since the first control signal Qdm (1088) maintains a high potential through capacitive coupling in the second phase P2 and the third phase P3. In a practical example, the leakage speed of the first control signal Qdm(1088) in the second phase P2 and the third phase P3 is fast, resulting in the first output signal Gdm( 1088) is not sufficiently pulled down. At this time, the potential of the first output signal Gdm ( 1088 ) can be auxiliary pulled down by the setting of the transistor T31 .

In one embodiment, the shift register 1 includes a charging structure 1_C and a charge sharing structure 1_S. In practice, the pixels in the panel can be divided into main pixels and sub-pixels, and since the charge-sharing structure 1_S has the front-stage dummy charge-sharing structure 1_FDMS, which includes the first eight stages of second shift register units 12_1-12_8, therefore The timing is delayed, so that the potentials of the sub-pixels can be staggered. In this embodiment, the first shift register unit 10_1088 of the 1088th stage in the charging structure 1_C has a circuit structure similar to that shown in FIG. 5 . In the charge sharing structure 1_S, the second shift register unit 12_1096 of the 1096th stage included in the shift register 1 receives an external signal from the external signal terminal S_ST. Please refer to FIG. 7 . FIG. 7 is a schematic circuit diagram of a second shift register according to another embodiment of the present invention, which corresponds to the second shift register unit 12_1096 of level 1096 in FIG. 3 . As shown in FIG. 7 , the second shift register unit 12_1096 of the 1096th stage includes a second pull-up circuit 202 and a second pull-down circuit 204 . The second pull-up circuit 202 adjusts the second output signal Sdm (1096) to the potential of the clock signal HC8 according to the first control signal Qsdm (1096) of the second shift register unit 12_1096 of the 1096th stage. The second pull-down circuit 204 converts the second output signal Sdm(1096) to the first control signal Qsdm( 1096) to adjust to the reference voltage VSS. The second shift register unit 12-_1096 of the 1096th stage includes a second clamping circuit 206 . The second clamping circuit 206 includes a transistor T41 and a transistor T44. The transistor T44 has a master terminal, a first terminal and a second terminal. The master terminal of the transistor T44 is electrically connected to the external signal terminal S_ST. The first end of the transistor T44 receives the clock signal HC4. The transistor T41 has a main control terminal, a first terminal and a second terminal. The master terminal of the transistor T41 is electrically connected to the second terminal of the transistor T44. The first end of the transistor T41 is electrically connected to the first control signal Qsdm (1096) of the second shift register unit 12_1096 of the 1096th stage. The second terminal of the transistor T41 receives the reference voltage VSS.

In another embodiment, please refer to FIG. 8 . FIG. 8 is a schematic circuit diagram of a first shift register unit according to another embodiment of the present invention, which corresponds to the first shift of the 1088th stage in FIG. 2 . Bit temporary storage unit 10_1088. As shown in FIG. 8 , the first shift register unit 10_1088 of the 1088th stage includes a second pull-up circuit 202 , a second pull-down circuit 204 and a second clamping circuit 206 . The main control terminal of the transistor T41 is electrically connected to the output signal terminal S_Sdm (1092) of the second shift register unit 10_1092 of the 1092nd stage, and the first end of the transistor T41 is electrically connected to the first shift register unit of the 1088th stage 10_1088 of the first control signal Qdm (1088). The second terminal of the transistor T41 receives the VSS reference voltage. FIG. 8 has substantially the same circuit structure as the embodiment of FIG. 5 , but the difference is that the second clamping circuit in the embodiment of FIG. 8 includes only one transistor, that is, the transistor T41 .

Please refer to FIG. 1 , FIG. 7 and FIG. 8 together. In this embodiment, the shift register 1 includes a charging structure 1_C and a charge sharing structure 1_S. Wherein, the second shift register unit 12_1096 of the 1096th stage receives the external signal ST from the external signal terminal S_ST, and the first shift register unit 10_1088 of the 1088th stage does not receive the external signal ST from the external signal terminal S_ST. Specifically, compared with the plurality of first shift register units 10_1˜10_1088, since the plurality of second shift register units 12_1˜12_1096 have eight more levels of shift register units, that is, the first shift register units Temporary storage units 12_1089~12_1096. Therefore, in this embodiment, the first shift register unit 10_1088 of the 1088th stage does not need to set an additional transistor (transistor T44 in FIG. 5 ) for receiving the external signal ST as in the embodiment of FIG. Control signal Qdm (1088) pull-down potential. In practice, in this example, the potential of the first control signal Qdm ( 1088 ) can be pulled down by the second shift register unit 12_1092 of the 1092nd stage.

Please refer to FIG. 9 . FIG. 9 is a schematic circuit diagram of a second shift register unit according to another embodiment of the present invention, which corresponds to the 1095th stage included in the shift register 1 of FIG. 1 Two shift temporary storage unit 12_1095. In this embodiment, the second shift register unit 12_1095 of the 1095th stage includes a third clamping circuit 306, and the third clamping circuit 306 includes a transistor T44 and a transistor T41, and has a master control terminal, a first terminal and a second terminal. The main control terminal of the transistor T44 is electrically connected to the external signal terminal S_ST, and the first terminal of the transistor T44 receives the clock signal HC3. The transistor T41 has a main control terminal, a first terminal and a second terminal. The master terminal of the transistor T41 is electrically connected to the second terminal of the transistor T44. The first end of the transistor T41 is electrically connected to the first control signal Qsdm (1095) of the second shift register unit 12_1095 of the 1095th stage. The second terminal of the transistor T41 receives the reference voltage VSS. The operation mode of the second shift register unit 12_1095 at the 1095th stage is the same as that of the second shift register unit 12_1096 at the 1096th stage, and will not be repeated here. In one embodiment, the plurality of second shift register units 12_1093 - 12_1096 all have the circuit structure of the embodiment in FIG. 9 .

Please refer to FIG. 10A , which is a structural diagram of a shift register according to another embodiment of the present invention. As shown in FIG. 10A, the shift register 2 has n shift register units, including shift register units 2_1 to 2_4 from the first stage to the fourth stage, and the shift register units 2_1 to 2_4 from the fifth stage to the (n-4)th stage shift register units 2_5-2_(n-4), and shift register units 2_(n-3)-2_n of the (n-3)th to n-th stages. Please refer to FIGS. 10B to 10D together. FIG. 10B is a schematic circuit diagram of shift register units from the first stage to the fourth stage according to the embodiment shown in FIG. 10A of the present invention. FIG. 10C is a schematic circuit diagram of shift register units from the fifth level to the (n−4)th level shown in the embodiment of FIG. 10A according to the present invention. FIG. 10D is a schematic circuit diagram of shift register units from the (n−3)th level to the nth level according to the embodiment shown in FIG. 10A of the present invention. As shown in Figures 10B to 10D, the shift register unit of the shift register 2 has a structure similar to that of the aforementioned first shift register unit and second shift register unit. The difference is that FIGS. 10B-10D all have a transistor T11, the first end of which is electrically connected to the control signal Q(n), and the second end receives the voltage VGHD. In FIG. 10C and FIG. 10D, the main control end of the transistor T11 receives the external signal ST(n-4), and in FIG. The two terminals are electrically connected to receive the clock signal HC(n-4), and the master terminal receives the external signal ST. Among them, for the first clamping circuit 106_1, FIG. 10D has a transistor T44, the main control terminal of which receives the external signal ST, the first terminal is electrically connected to the main control terminal of the transistor T41, and the second terminal receives the clock signal HC(n+4 ), the first end of the transistor T41 receives the reference voltage VSSQ, and the second end is electrically connected to the control signal Q(n).

However, FIG. 10B and FIG. 10C only have the transistor T41, the first end of which also receives the reference voltage VSS, and the second end is electrically connected to the control signal Q(n). Different from the above-mentioned embodiments, in this embodiment, based on the above-mentioned circuit structure, the shift register 2 can have the capability of forward and reverse scanning. As an example, when performing a positive scan, the voltage VGHD is 30 volts, and the reference voltage VSSQ is negative 12 volts, and the clock signal HC1 to the clock signal HC8 are provided sequentially, so that the shift register 2 is The shift register unit 2_1 of the first stage is enabled sequentially to the shift register unit 2_n of the last stage. That is, when reverse scanning is performed, the voltage VGHD is negative 12 volts, and the reference voltage VSSQ is 30 volts, and the clock signal HC8 to the clock signal HC1 are provided sequentially, so that the shift register 2 is reversed by the last one. The shift register unit 2_n of the stage is enabled sequentially to the shift register unit 2_1 of the first stage. In other words, when performing forward and reverse scanning, the order of transmitting the clock signal HC1 to the clock signal HC8 is reversed, and the voltage VGHD and the reference voltage VSSQ are also exchanged to achieve the function of forward and reverse scanning.

Please refer to FIG. 11 . FIG. 11 is a timing control waveform diagram of an external signal and a first control signal according to an embodiment of the present invention, which is applicable to the shift register 1 . As shown in FIG. 11 , in one embodiment, the external signal ST is switched from a low voltage to a high voltage before the negative edge C−_NE of the clock signal HC8 of the first shift register unit 10_1088 of the 1088th stage. In one embodiment, the external signal ST is switched from a low voltage to a high voltage before the positive edge C−_PE of the clock signal HC8 of the first shift register unit 10_1088 of the 1088th stage. In another embodiment, the external signal ST is switched from a low voltage to the high voltage before the positive edge Q-_PE1 of the first control signal Qdm (1088 ) of the first shift register unit 10_1088 of the 1088th stage. In another example, the external signal ST is generated by Low voltage to high voltage conversion.

Please refer to FIG. 12 . FIG. 12 is a schematic structural diagram of a part of the display panel according to an embodiment of the present invention. In this embodiment, the charging structure 1_C included in the shift register 1 does not have the dummy charging structure 1_DMC. Wherein, as shown in FIG. 12 , the display panel 20 has 1080 scan lines S1-S1080, and the 1080 first shift registers 1-0_1-10-_1080 included in the charging structure 1_C are connected to the scan lines in one-to-one correspondence. S1～S1080.

Based on the above, the shift register disclosed in the present invention receives an external signal through the first transistor of the first clamping circuit in the first shift register unit, and is matched with timing control so that the first control signal is The time of the third stage can be shortened, thereby reducing the stress effect on the first shift temporary storage unit.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (15)

1. a kind of shift registor, it is characterised in that include：

N number of first displacement temporary storage unit, N number of first displacement temporary storage unit are mutually concatenated, and N is the integer more than 1, wherein i-th First displacement temporary storage unit of level is included：

One first pull-up circuit, according to one first control signal of the first displacement temporary storage unit of the i-stage, by one first output Signal is adjusted to the current potential of one first clock signal；And

One first pull-down circuit, according to first control signal and a pulldown signal of the first displacement temporary storage unit of the i-stage, First output signal and first control signal are adjusted to a reference voltage；

Wherein i is the positive integer less than or equal to N, and the first displacement temporary storage unit of N levels is also included：

One first clamped circuit, comprising：

One the first transistor, with main control end, first end and the second end, the main control end of the first transistor is electrically connected with outside one Portion's signal end, the first end of the first transistor receive one second clock signal；And

One transistor seconds, with main control end, first end and the second end, the main control end of the transistor seconds be electrically connected with this Second end of one transistor, the first end of the transistor seconds are electrically connected with the first displacement temporary storage unit of the N levels First control signal, second end of the transistor seconds receive the reference voltage.

2. shift registor as claimed in claim 1, it is characterised in that also include：

N-m the second displacement temporary storage unit, the N-m the second displacement temporary storage unit are mutually concatenated, and the second displacement of N-m levels is temporary First displacement temporary storage unit of memory cell and the N levels receives the external signal from the external signal terminal, and m is less than N Positive integer.

3. shift registor as claimed in claim 2, it is characterised in that the second displacement temporary storage unit of j-th stage is included：

One second pull-up circuit, according to one first control signal of the second displacement temporary storage unit of the j-th stage, by one second output Signal is adjusted to the current potential of one the 3rd clock signal；And

One second pull-down circuit, according to first control signal and the pulldown signal of the second displacement temporary storage unit of the j-th stage, Second output signal and first control signal are adjusted to the reference voltage；

Wherein j is the positive integer less than or equal to N-m, and the second displacement temporary storage unit of the N-m levels is also included：

One second clamped circuit, comprising：

One third transistor, with main control end, first end and the second end, the main control end of the third transistor is electrically connected with N- One output signal end of 4 grades of the first displacement temporary storage unit, the first end of the third transistor are electrically connected with the N-m levels One first control signal of the second displacement temporary storage unit, second end of the third transistor receive the reference voltage.

4. shift registor as claimed in claim 2, it is characterised in that the second displacement temporary storage unit of kth level is included：

One second pull-up circuit, according to one first control signal of the second displacement temporary storage unit of the kth level, by one second output Signal is adjusted to the current potential of one the 3rd clock signal；And

One second pull-down circuit, according to first control signal and the pulldown signal of the second displacement temporary storage unit of the kth level, Second output signal and first control signal are adjusted to the reference voltage；

Wherein k is the positive integer less than or equal to N-m, and the second displacement temporary storage unit of N-m levels is also included：

One second clamped circuit, comprising：

One the 4th transistor, with main control end, first end and the second end, it is outer that the main control end of the 4th transistor is electrically connected with this Portion's signal end, the first end of the 4th transistor receive one the 4th clock signal；And

One the 5th transistor, with main control end, first end and the second end, the main control end of the 5th transistor be electrically connected with this Second end of four transistors, the first end of the 5th transistor are electrically connected with the second displacement temporary storage unit of the N-m levels One first control signal, second end of the 5th transistor receives the reference voltage.

5. shift registor as claimed in claim 1, it is characterised in that first clamped circuit is also included：

One the 6th transistor, with main control end, first end and the second end, the main control end of the 6th transistor be electrically connected with this Second end of one transistor, the first end of the 6th transistor are electrically connected with first output signal, the 6th transistor Second end receive the reference voltage.

6. the shift registor as described in any one of claim 1 to 5, it is characterised in that the conduction impedance of the transistor seconds More than the conduction impedance of the first transistor.

7. the shift registor as described in any one of claim 1 to 5, it is characterised in that second clock signal is N-4 levels The first displacement temporary storage unit first clock signal.

8. the shift registor as described in any one of claim 1 to 5, it is characterised in that the shift registor is applied to and shows Show panel, the display floater has N bar scan lines, and N number of first displacement temporary storage unit is connected to the N bars correspondingly and sweeps Retouch line.

9. shift registor as claimed in claim 1, it is characterised in that the first displacement temporary storage unit of N-1 levels is also included：

One the 3rd clamped circuit is included：

One the 7th transistor, with main control end, first end and the second end, it is outer that the main control end of the 7th transistor is electrically connected with this Portion's signal end, the first end of the 7th transistor receive one the 5th clock signal；And

One the 8th transistor, with main control end, first end and the second end, the main control end of the 8th transistor be electrically connected with this Second end of seven transistors, the first end of the 8th transistor are electrically connected with the first displacement temporary storage unit of the N-1 levels One first control signal, second end of the 8th transistor receives the reference voltage.

10. a kind of sequential control method of shift registor, it is adaptable to the shift register as described in any one of claim 1 to 9 Device, it is characterised in that include：

The external signal is before the negative edge of first clock signal of the first displacement temporary storage unit of the N levels by a low-voltage Change to a high voltage.

The sequential control method of 11. shift registors as claimed in claim 10, it is characterised in that the external signal in this By the low voltage transition to the high voltage before the positive edge of first clock signal of the first displacement temporary storage unit of N levels.

The sequential control method of 12. shift registors as claimed in claim 11, it is characterised in that the external signal in this By the low voltage transition to the high voltage before the positive edge of first control signal of the first displacement temporary storage unit of N levels.

13. a kind of shift registors, it is characterised in that include：

One pull-up circuit, according to a control signal, an output signal is adjusted to the current potential of one first clock signal；

One pull-down circuit, according to the control signal and a pulldown signal, the output signal and the control signal is adjusted to a ginseng Examine voltage；And

One first clamped circuit, comprising：

One the first transistor, with main control end, first end and the second end, the main control end of the first transistor is electrically connected with outside one Portion's signal end, the first end of the first transistor receive one second clock signal；And

One transistor seconds, with main control end, first end and the second end, the main control end of the transistor seconds be electrically connected with this Second end of one transistor, the first end of the transistor seconds are electrically connected with the control signal, the transistor seconds should Second end receives the reference voltage.

14. shift registors as claimed in claim 13, it is characterised in that the conduction impedance of the transistor seconds more than this The conduction impedance of one transistor.

15. shift registors as claimed in claim 13, it is characterised in that first clamped circuit is also included：

One third transistor, with main control end, first end and the second end, the main control end of the third transistor be electrically connected with this Second end of one transistor, the first end of the third transistor are electrically connected with the output signal, the third transistor should Second end receives the reference voltage.