CN106526460B - A kind of fault localization method and device - Google Patents
A kind of fault localization method and device Download PDFInfo
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- CN106526460B CN106526460B CN201611247451.0A CN201611247451A CN106526460B CN 106526460 B CN106526460 B CN 106526460B CN 201611247451 A CN201611247451 A CN 201611247451A CN 106526460 B CN106526460 B CN 106526460B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2843—In-circuit-testing
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Abstract
The present invention provides a kind of fault localization method and device, the fault localization method, input be based on circuit normally under malfunction emulation data and circuit network building analog circuit test exchange format file and test routing file；Above-mentioned file is parsed, the information such as test and excitation needed for obtaining circuit test and fault diagnosis, test node, instrument mapping, test routing and test criteria；According to acquired information is parsed, the file comprising testing process is generated, and by executing flow file, realizes test and fault location to circuit board.Utilize the above method and device, it solves prior art and depends on the testing sequence that corresponding test node information is manually entered and determines node, caused heavy workload, the degree of automation be not high and leads to the quantity of test node and the distribution not enough not strong technical problem of optimization, topological logic.
Description
Technical field
The present invention relates to circuit test and fault diagnosis field more particularly to a kind of fault localization methods and device.
Background technique
With the rapid development of electronic technology, circuit test diagnosis especially analog circuit fault diagnosing becomes increasingly complex.
Circuit board needs to measure acquisition to the data of intermediate node in fault location, carries out circuit state according to measurement result
Judge and analyzes the Test Strategy for being inferred to next step；At present in board failure positioning, depends on and phase is manually entered
The testing sequence of the test node information and determining node answered, it is not high so as to cause heavy workload, the degree of automation, and cause
The quantity of test node and the distribution not enough not strong problem of optimization, topological logic.
Summary of the invention
It is an object of the present invention to which there are heavy workloads, automation when to solve using manual testing's circuit node information
Degree is not high, and leads to the quantity and the distribution not enough not strong problem of optimization, topological logic of test node, provides one kind
Board failure localization method and device.
The fault localization method, input be based on circuit normally with the emulation data and electricity under malfunction
The analog circuit test exchange format file (referred to as: ATIF) and test routing file of road network building；Above-mentioned file is carried out
Parsing obtains circuit test and sentences with test and excitation, test node needed for fault diagnosis, instrument mapping, test routing and test
According to etc. information；According to acquired information is parsed, test program is generated, and by executing test program, realizes the survey to circuit board
Examination and fault location.
To achieve the above object, a kind of fault localization method provided by the invention, this method comprise the following steps:
Step 1) import analog circuit test exchange format file and test routing file, and parse obtain circuit test with
Test and excitation needed for fault diagnosis, test node, instrument mapping, test routing and test criteria information, parse the number finished
In the database according to storage；The analog circuit test exchange format file using circuit normally with the emulation under malfunction
Data and circuit network are built-up, describe the status information during analog circuit test, and the test routing file is retouched
State the connection relation information between input, output channel and the circuit-under-test test node of test equipment.
Step 2) completes the configuration to power channel and its parameter according to parsing data, and generating includes test and excitation operation stream
The file of journey configures the parameter and input, output channel of test equipment, generates the file comprising test operation process；
Step 3) executes the file comprising test and excitation operating process generated in step 2), includes test operation process
File, control test equipment realize test and fault location to circuit-under-test plate.This method has been applied to analog circuit event
In barrier diagnosis, and show superior performance.
As a further improvement of the above technical scheme, the step 2) includes:
Step 201) extracts test and excitation and test node information in analog circuit test exchange format file, and surveys
The power channel in routing file and the connection relation information between circuit node are tried, power channel and its parameter are matched in completion
It sets, generates test and excitation operating process；
Step 202) generates the test operation process of each module in circuit-under-test, and the test operation process includes circuit
Test operation process and fault diagnosis operating process, the circuit testing operation process is for determining that each module is normal or event
Barrier state, and fault diagnosis operating process is executed by the module to malfunction, it is obtained with acquisition for judging fault type
Response data；
Step 203) by the test and excitation operating process in step 201), the circuit testing operation process in step 202) and
Fault diagnosis operating process is respectively written into specified flow file.
As a further improvement of the above technical scheme, the generation step of the circuit testing operation process are as follows: foundation
The test routing letter extracted in the test and excitation information extracted in analog circuit test exchange format file, test routing file
Breath, configures the parameter and input channel of test equipment；According to the response message extracted in analog circuit test exchange format file
Test routing iinformation with extracting in test routing file, configures the parameter and output channel of test equipment；The failure is examined
The generation step of disconnected operating process are as follows: according to the excitation information extracted in analog circuit test exchange format file, test routing
The routing iinformation extracted in file configures the parameter and input channel of test equipment；According to analog circuit test exchange format text
The information for needing acquisition node is extracted in part, configures the parameter and output channel of test equipment, and the configuration dialog box, prompts test
Node and probe pen type, the PCB scintillation parameter of configuration output test node.
As a further improvement of the above technical scheme, the analog circuit test exchange format file packet in the step 1)
It includes: header file, UUT file group, exciter response file group and fault knowledge file group；
The header file stores the number for generating time, fault dictionary file of the version number of fault dictionary, fault dictionary
Amount, number and grouping information；
The UUT file group include: net meter file, circuit unit file, input node file, output node file,
Can not test pin file, pin node mapped file and node map pins file, respectively store artificial circuit netlist letter
Breath, circuit assembly information, input node information, output node information, can not test pin information, corresponding the reflecting to node of pin
Penetrate the corresponding map information to pin of information, node；
The exciter response file group includes: excitation types file, excitation property file, quiescent point response file
With steady-state response file, quiescent point when storing excitation types information, excitation attribute information, functional simulation respectively responds letter
Breath, steady-state response information；
The fault knowledge file group includes: failure number file, quiescent point fault set file, steady state fault collection
File, untestable fault collection file, fuzzy set schema file, quiescent point fuzzy set file, stable state fuzzy set file, static state
Operating point fault dictionary file, steady state fault dictionary file and homomorphism failure file store failure number, quiescent point respectively
Failure name information, steady state fault name information, untestable fault information, fuzzy set pattern information, quiescent point fuzzy set
Information, stable state fuzzy set information, quiescent point fault dictionary information, steady state fault dictionary information, homomorphism fault message.
As a further improvement of the above technical scheme, the test routing file in the step 1) includes: input pin
Information, output pin information, excitation mapping and response mapping；
If it is determined that pin is excitation load pin, then input pin is defined as, if it is decided that pin is that response load is drawn
Foot is then defined as output pin；
The excitation mapping is indicated according to input pin load excitation test equipment input used, output channel；Institute
The response mapping stated indicates to establish test equipment input, output channel and circuit-under-test connector output pin according to output pin
Connection.
As a further improvement of the above technical scheme, the step 3) includes:
Step 301) load step 201) in the file comprising test and excitation operating process that generates, by power channel and its
The configuration of parameter is transmitted in power supply, control power supply output；
Step 302) is according to the file comprising circuit testing operation process generated in step 203), in circuit-under-test one
A module loading test and excitation that do not test configures the parameter and input channel of test equipment, realizes excitation output；
Step 303) is according to the file comprising circuit testing operation process generated in step 203), in step 302)
Module loading test response, configures the parameter and output channel of test equipment, realizes response acquisition；It is sequentially completed and all needs to adopt
After the response of collection, according to the response data criterion that exciter response file group parses in analog circuit test exchange format file,
Judge to obtain the module currently tested for normal condition or malfunction；
If the module tested in step 304) step 303) is normal condition, output module normal state information is right
302) one module that do not test is re-execute the steps；If the module tested in step 303) is malfunction, according to step
Rapid 203) the middle file comprising fault diagnosis operating process generated configures the ginseng of test equipment to module loading test and excitation
Several and input channel realizes excitation output；
Step 305) adds according to the file comprising fault diagnosis operating process generated in step 203) in step 304)
Module loading after carrying test and excitation tests response, and the connection of probe pen and tested node is completed according to prompt, clicks in dialog box
Continue to execute after, complete the configuration and control of test equipment, realize response acquisition；It is sequentially completed the response for all needing to acquire
Afterwards, step 306) is executed；
Step 306) is to all response messages acquired in step 305) according in analog circuit test exchange format file
Fuzzy set schema file carry out type matching, after matching obtains fuzzy integrated mode, with the fuzzy set in fuzzy set file
Match, if all response messages of judgement have matched fuzzy set range, shows that malfunction is what matching obtained
The corresponding failure of fuzzy set.
As a further improvement of the above technical scheme, comprising: document analysis module, testing process generation module, test
Flow executing modules and test equipment；
The document analysis module: for importing analog circuit test exchange format file and test routing file, and
Test and excitation needed for parsing obtains circuit test and fault diagnosis, test node, instrument mapping, test routing and test criteria
Information；The analog circuit test exchange format file using circuit normally with the emulation data and circuit network under malfunction
Network is built-up, describes the status information during analog circuit test, it is defeated that the test routing file describes test equipment
Enter, the link information between output channel and circuit-under-test test node；
The testing process generation module: the information for being obtained according to the parsing of document analysis module is completed to power supply
The configuration of channel and its parameter, generate include test and excitation operating process file, configure the parameter of test equipment and input, defeated
Channel out generates the file comprising test operation process；
Testing process execution module: for execute generated in testing process generation module comprising test and excitation operating process
File, the file comprising test operation process, control test equipment realizes test and fault location to circuit.
A kind of fault localization method of the invention and device advantage are:
Using device and method provided by the invention, it is fixed to can be realized the fault based on circuit network and graph search
Position realizes the functions such as test imports, tests parsing, testing process file is automatically generated and executed, solves prior art
Depend on be manually entered corresponding test node information and determine node testing sequence, caused heavy workload, from
Dynamicization degree is not high and leads to the quantity of test node and the distribution not enough not strong technical problem of optimization, topological logic.
Detailed description of the invention
Fig. 1 is a kind of fault localization method flow chart provided by the invention.
Fig. 2 is the ATIF file composition frame diagram in the present invention.
Fig. 3 is the test operation automatic process generating schematic diagram in the embodiment of the present invention.
Fig. 4 is that the test operation process in the embodiment of the present invention executes schematic diagram.
Specific embodiment
A kind of fault localization method of the present invention and device are carried out with reference to the accompanying drawings and examples detailed
Explanation.
As shown in Figure 1, a kind of fault localization method provided by the invention, this method comprises:
Step 1) import analog circuit test exchange format file and test routing file, and parse obtain circuit test with
Test and excitation needed for fault diagnosis, test node, instrument mapping, test routing and test criteria information；The simulation electricity
Drive test try exchange format file using circuit normally under malfunction emulation data and circuit network it is built-up, describe mould
Status information in quasi- circuit testing procedures, the test routing file describe test equipment input, output channel and are tested
Link information between circuit test node；
The information that step 2) is obtained according to step 1) parsing, completes the configuration to power channel and its parameter, automatically generates
File comprising test and excitation operating process configures the parameter and input, output channel of test equipment, and generating includes test operation
The file of process；
Step 3) executes the file comprising test and excitation operating process generated in step 2), includes test operation process
File, control test equipment realize test and fault location to circuit.
As shown in Fig. 2, the analog circuit test exchange format file in the step 1) includes: header file, UUT file
Group, exciter response file group, fault knowledge file group composition；
The version number of the header file storage fault dictionary, the number of the generation time and fault dictionary file of fault dictionary
Amount, number and grouping information；
The UUT file group by net meter file, circuit unit file, input node file, output node file, can not
7 test pin file, pin node mapped file, node map pins file file compositions, store institute's artificial circuit respectively
Netlist information, circuit assembly information, output and input nodal information, can not test pin information, pin it is corresponding to node
The corresponding map information to pin of map information, node；
The exciter response file group is by excitation types file, excitation property file, quiescent point response file, steady
4 file compositions of state response file, store quiescent operation when excitation types information, excitation attribute information and functional simulation respectively
Point response message, steady-state response information；
The fault knowledge file group is by failure number file, quiescent point fault set file, steady state fault collection text
Part, untestable fault collection file, fuzzy set schema file, quiescent point fuzzy set file, stable state fuzzy set file, static work
Make point failure dictionary file, steady state fault dictionary file, homomorphism failure file 10 files composition, store respectively failure number,
Quiescent operation point failure name information, steady state fault name information, untestable fault information, fuzzy set pattern information, static work
Make point fuzziness collection information, stable state fuzzy set information, quiescent point fault dictionary information, steady state fault dictionary information, homomorphism event
Hinder information.
In the database by the storage of above-mentioned ATIF document analysis data, the number automatically generated as follow-up test flow file
According to source.The information stored in the database and the information parsed in ATIF file are completely the same, respectively with the UUT in ATIF file
File group, exciter response file group, fault knowledge file group are corresponding.
Test routing file describes the link information of test equipment and test point.Routing file is tested by parsing,
Obtain being described as follows for parsing information:
Input/output pinout information: if it is determined that pin is excitation load pin, then it is defined as input pin, if sentenced
Pin is determined for response load pin, then is defined as output pin；
Excitation/response mapping: the excitation mapping indicates defeated according to input pin load excitation test equipment used
Enter, output channel；The response mapping indicates to establish test equipment input, output channel and circuit-under-test according to output pin
The connection of connector output pin；
In the database by above-mentioned test routing file parsing information preservation, it is automatically generated as follow-up test flow file
Data source.
In testing process generating process, it is necessary first to automatically generate excitation；Then according to the (test of the blocking information of circuit
Circuit board is formed in advance according to its function in routing file, circuit board is divided into the module of several function opposite independents), point
The test operation process of each circuit module is not generated.
In the present embodiment, the file generated process in the step 2) comprising test operation process specifically includes:
Step 201) presses function in test and excitation operating process generating process, according to the blocking information of circuit, such as circuit board
Energy module is divided into 5 modules, then the test and excitation operating process symbiosis generated is at 7 parts；First part is for controlling electricity
The operation of source loading module；The part 2-6 is used to control the operation of 5 functional modules；7th part controls power supply closedown module
Operation；With power supply loading module extract ATIF file in test and excitation and test node information, from test routing file in mention
Connection relation information between the power channel taken and circuit node completes the configuration to power channel and its parameter, realizes electricity
The load of source forcing, and it is always maintained at power supply closing, test and excitation operating process is automatically generated to realize.Terminating to test
Afterwards, shutoff operation is arranged by respective channel of the power supply closedown module to power supply, to terminate test operation.By above-mentioned configuration information
Store into test TP file.
Step 202) generates the testing process of each circuit module according to the blocking information of circuit respectively；Each circuit mould
The test of block includes circuit testing operation process and fault diagnosis operating process two parts.The circuit testing operation process is used
In determining that each module is normal or malfunction, and fault diagnosis operating process is executed by the module to malfunction, to adopt
Collection obtains the response data for judging fault type.By taking any one in 5 circuit modules as an example, the circuit test
The generation step of operating process are as follows: extracted according to from the test and excitation information extracted in ATIF file, in test routing file
Routing iinformation is tested, the parameter and input channel of test equipment are configured；Secondly according to extracted from ATIF file response message,
The test routing iinformation extracted in test routing file, configures the parameter and output channel of test equipment；By the letter of above-mentioned generation
Breath saves as TP；The generation step of the fault diagnosis operating process are as follows: need to acquire section according to extracting from ATIF file
The excitation information of point tests the routing iinformation extracted in routing file, configures the parameter and input channel of test equipment, foundation
The information for needing acquisition node is extracted in ATIF file, is configured the parameter and output channel of test equipment, and the configuration dialog box, is mentioned
Show test node and probe pen type, configuration exports the PCB scintillation parameter of the node；By the information preservation of above-mentioned generation at TP text
Part.
The fault diagnosis operating process is equipped with PCB flashing and dialog box prompt operation, and the position of flashing is directed toward current
Measured point or tested component, and the probe pen type for prompting current test to need by dialog box and measured point, test when
Wait the position that prompt needs to be implemented the test point currently tested.
File implementation procedure in the step 3) comprising test operation process specifically includes:
Step 301) load step 201) in generate the file comprising test and excitation operating process, specifically: according to electricity
Loading module corresponding test and excitation process in source executes power supply load operation；When being executed, pass through the driving of software transfer power supply
The channel of power supply and its configuration parameter are transmitted in power supply by function, control power supply output；
Step 302) is according to the file comprising circuit testing operation process generated in step 202), in circuit-under-test one
A module loading test and excitation that do not test, and the parameter of test equipment, input channel configuration and control are completed, realize that excitation is defeated
Out；
Step 303) is according to the file comprising circuit testing operation process generated in step 202), in step 302)
Module loading test response, and the parameter of test equipment, output channel configuration and control are completed, realize response acquisition；It is successively complete
At the response for all needing to acquire, and according to the response data criterion parsed from the exciter response file group in ATIF file,
Judge to obtain the module currently tested in circuit for normal condition or malfunction；
If the functions of modules tested in step 304) step 303) is normal, next step functional test is carried out, i.e., under
302) one module that do not test is re-execute the steps；If the functions of modules tested in step 303) is abnormal, according to step
Rapid 202) the middle file comprising fault diagnosis operating process generated tests the module again, tests module loading and swashs
It encourages, configures the parameter and input channel of test equipment, excitation output is realized, until realizing fault location；
Step 305) adds according to the file comprising fault diagnosis operating process generated in step 202) in step 304)
Module loading after carrying test and excitation tests response, and the connection of probe pen and tested node is completed according to prompt, clicks in dialog box
Continue to execute after, complete the configuration and control of instrument, realize response acquisition；The information of acquisition is all stored；It is complete wait need
After the completion of the information collection of portion's acquisition, step 306) is executed；
Step 306) is to each response message acquired in step 305) according to the fuzzy set schema file in ATIF file
Type matching is carried out, after matching obtains fuzzy integrated mode, is matched with the fuzzy set in fuzzy set file, judges acquired information
Whether within the scope of the matched fuzzy set of institute, and after being sequentially completed the judgement of whole response messages, judging result is obtained: if complete
When portion's response message is within the scope of same or certain several matched fuzzy set, then show that current circuit state is the mould
Paste collection or the corresponding failure of certain several fuzzy set.
The fuzzy set schema file is directed to different waveforms, and the fuzzy set type of the waveform is depicted；With sine wave
For signal, fuzzy integrated mode includes: upper amplitude limit, amplitude lower limit, upper frequency limit, lower-frequency limit, the biasing upper limit and biasing
Lower limit.
The fuzzy set file is for the different state of circuit, according to the signal type of test node in this state,
According to fuzzy set schema file, the fuzzy set of each test node under every kind of state is described, if certain test node is sinusoidal letter
Number, then its fuzzy set is expressed as under certain state: 0.5 1,1,000 1005,0.25 0.3.
Embodiment one
Referring to shown in Fig. 3, in the present embodiment, testing process is carried out using foregoing circuit Fault Locating Method and is automatically generated
Process include the following steps:
Firstly, test and excitation generates；According to excitation routing iinformation, complete operating software automatically generate control and excitation from
It is dynamic to generate；
Secondly, retrieving the signal attribute and routing iinformation of the pin according to test output pin, circuit testing operation is realized
Process generates, comprising: operating software automatically generates control, routing closure generates, Self -adaptive and routing are disconnected and being generated；Wherein,
Self -adaptive refers to the configuration of test equipment；
Finally, retrieving the signal attribute of the pin according to tested pin, realize that fault diagnosis operating process generates, packet
Include: test pin information configuration and PCB flash for prompting generate；Wherein, test pin information configuration includes: test prompts information,
Test equipment configuration.
Referring to shown in Fig. 4, in the present embodiment, the mistake of testing process execution is carried out using foregoing circuit Fault Locating Method
Journey includes the following steps:
Firstly, carrying out test and excitation application by test and excitation operating process；
Then, test operation is executed to n circuit module of division；By being tested automatically circuit module, the electricity is detected
Road module whether there is failure；If fault-free, next circuit module is tested automatically, until whole circuit modules are completed；
If there are failures for circuit module, enters the fault diagnosis operating process of the circuit module, flash and talk with by PCB node
Frame information alert carries out probe pen test, and by the test to all test nodes of the circuit module, realizes Fault Isolation；Such as
Fruit whole test point is completed, and not can determine that failure, then needs to regenerate and optimize ATIF file, continue to execute above-mentioned step
Suddenly.
In addition, being based on foregoing circuit Fault Locating Method, the present invention goes back while providing a kind of fault positioning device,
It include: document analysis module, testing process generation module, testing process execution module and test equipment；
The document analysis module: for importing analog circuit test exchange format file and test routing file, and
Test and excitation needed for parsing obtains circuit test and fault diagnosis, test node, instrument mapping, test routing and test criteria
Information；The analog circuit test exchange format file using circuit normally with the emulation data and circuit network under malfunction
Network is built-up, describes the status information during analog circuit test, and the routing file describes test equipment and inputs, is defeated
Link information between channel and circuit-under-test test node out；
The testing process generation module: the information for being obtained according to the parsing of document analysis module is completed to power supply
The configuration of channel and its parameter automatically generates the file comprising test and excitation operating process, configures the parameter of test equipment and defeated
Enter, output channel, generates the file comprising test operation process；
Testing process execution module: for execute generated in testing process generation module comprising test and excitation operating process
File, the file comprising test operation process, control test equipment realizes test and fault location to circuit.
It should be noted last that the above examples are only used to illustrate the technical scheme of the present invention and are not limiting.Although ginseng
It is described the invention in detail according to embodiment, those skilled in the art should understand that, to technical side of the invention
Case is modified or replaced equivalently, and without departure from the spirit and scope of technical solution of the present invention, should all be covered in the present invention
Scope of the claims in.
Claims (6)
1. a kind of fault localization method characterized by comprising
Step 1) imports analog circuit test exchange format file and test routing file, and parses and obtain circuit test and failure
Test and excitation needed for diagnosis, test node, instrument mapping, test routing and test criteria information；The analog circuit is surveyed
Try exchange format file using circuit normally under malfunction emulation data and circuit network it is built-up, description simulation electricity
Status information during drive test examination, the test routing file describe test equipment input, output channel and circuit-under-test
Link information between test node；
The information that step 2) is obtained according to step 1) parsing, completes the configuration to power channel and its parameter, generates comprising test
The file for motivating operating process configures the parameter and input, output channel of test equipment, generates the text comprising test operation process
Part；
Step 3) executes the file comprising test and excitation operating process generated in step 2), the text comprising test operation process
Part, control test equipment realize test and fault location to circuit；
The step 2) includes:
Step 201) extracts test and excitation and test node information in analog circuit test exchange format file, and test road
By the power channel in file and the connection relation information between circuit node, the configuration to power channel and its parameter is completed,
Generate test and excitation operating process；
Step 202) generates the test operation process of each module in circuit-under-test, and the test operation process includes circuit test
Operating process and fault diagnosis operating process, the circuit testing operation process is for determining that each module is normal or failure shape
State, and fault diagnosis operating process is executed by the module to malfunction, to acquire the sound obtained for judging fault type
Answer data；
Step 203) is by the test and excitation operating process in step 201), the circuit testing operation process in step 202) and failure
Diagnostic operation process is respectively written into specified flow file.
2. fault localization method according to claim 1, which is characterized in that the circuit testing operation process
Generation step are as follows: mentioned according to the test and excitation information extracted in analog circuit test exchange format file, in test routing file
The test routing iinformation taken configures the parameter and input channel of test equipment；According in analog circuit test exchange format file
The test routing iinformation extracted in the response message and test routing file of extraction, parameter and the output for configuring test equipment are logical
Road；The generation step of the fault diagnosis operating process are as follows: swash according to what is extracted in analog circuit test exchange format file
It encourages information, test the routing iinformation extracted in routing file, configure the parameter and input channel of test equipment；According to analog circuit
The information for needing acquisition node is extracted in test exchange format file, configures the parameter and output channel of test equipment, and configure
Dialog box prompts test node and probe pen type, the PCB scintillation parameter of configuration output test node.
3. fault localization method according to claim 2, which is characterized in that the analog circuit in the step 1) is surveyed
Trying exchange format file includes: header file, UUT file group, exciter response file group and fault knowledge file group；
The version number of the header file storage fault dictionary, the generation time of fault dictionary, the quantity of fault dictionary file, volume
Number and grouping information；
The UUT file group include: net meter file, circuit unit file, input node file, output node file, can not
Test pin file, pin node mapped file and node map pins file store netlist information, the electricity of artificial circuit respectively
Road module information, input node information, output node information, can not test pin information, the corresponding mapping to node of pin believe
The corresponding map information to pin of breath, node；
The exciter response file group includes: excitation types file, excitation property file, quiescent point response file and steady
State response file, respectively store excitation types information, excitation attribute information, functional simulation when quiescent point response message,
Steady-state response information；
The fault knowledge file group includes: failure number file, quiescent point fault set file, steady state fault collection text
Part, untestable fault collection file, fuzzy set schema file, quiescent point fuzzy set file, stable state fuzzy set file, static work
Make point failure dictionary file, steady state fault dictionary file and homomorphism failure file, stores failure number, quiescent point event respectively
Hinder name information, steady state fault name information, untestable fault information, fuzzy set pattern information, quiescent point fuzzy set letter
Breath, stable state fuzzy set information, quiescent point fault dictionary information, steady state fault dictionary information, homomorphism fault message.
4. fault localization method according to claim 2, which is characterized in that the test in the step 1) routes text
Part includes: input pin information, output pin information, excitation mapping and response mapping；
If it is determined that pin is excitation load pin, then input pin is defined as, if it is decided that pin is response load pin, then
It is defined as output pin；
The excitation mapping is indicated according to input pin load excitation test equipment input used, output channel；Described
Response mapping indicates that test equipment input, output channel and circuit-under-test connector output pin are established according to output pin to be connected
It connects.
5. fault localization method according to claim 3, which is characterized in that the step 3) includes:
Step 301) load step 201) in generate the file comprising test and excitation operating process, by power channel and its parameter
Configuration be transmitted in power supply, control power supply output；
Step 302) is according to the file comprising circuit testing operation process generated in step 203), not to one in circuit-under-test
The module loading test and excitation of test configures the parameter and input channel of test equipment, realizes excitation output；
Step 303) is according to the file comprising circuit testing operation process generated in step 203), to the module in step 302)
Load test response, configures the parameter and output channel of test equipment, realizes response acquisition；It is sequentially completed what all needs acquired
After response, according to the response data criterion that exciter response file group parses in analog circuit test exchange format file, judgement
Obtaining the module currently tested is normal condition or malfunction；
If the module tested in step 304) step 303) is normal condition, output module normal state information, to one
302) module that do not test is re-execute the steps；If the module tested in step 303) is malfunction, according to step
203) file comprising fault diagnosis operating process generated in configures the parameter of test equipment to module loading test and excitation
And input channel, realize excitation output；
Step 305) surveys load in step 304) according to the file comprising fault diagnosis operating process generated in step 203)
Examination excitation after module loading test response, according to prompt complete probe pen and tested node connection, click dialog box in after
After continuous execution, the configuration and control of test equipment are completed, realizes response acquisition；After being sequentially completed the response for all needing to acquire,
Execute step 306)；
Step 306) is to all response messages acquired in step 305) according to the mould in analog circuit test exchange format file
It pastes integrated mode file and carries out type matching, after matching obtains fuzzy integrated mode, match, sentence with the fuzzy set in fuzzy set file
If disconnected all response messages have matched fuzzy set range, show that malfunction is the fuzzy set that matching obtains
Corresponding failure.
6. the fault positioning device based on fault localization method described in one of claim 1-5, which is characterized in that
It include: document analysis module, testing process generation module, testing process execution module and test equipment；
The document analysis module: it for importing analog circuit test exchange format file and test routing file, and parses
Test and excitation needed for obtaining circuit test and fault diagnosis, test node, instrument mapping, test routing and test criteria are believed
Breath；The analog circuit test exchange format file using circuit normally with the emulation data and circuit network under malfunction
It is built-up, describe analog circuit test during status information, the test routing file describe test equipment input,
Link information between output channel and circuit-under-test test node；
The testing process generation module: the information for being obtained according to the parsing of document analysis module is completed to power channel
And its configuration of parameter, the file comprising test and excitation operating process is generated, the parameter and input, output for configuring test equipment are led to
Road generates the file comprising test operation process；
The execution step of the module includes:
Step 201) extracts test and excitation and test node information in analog circuit test exchange format file, and test road
By the power channel in file and the connection relation information between circuit node, the configuration to power channel and its parameter is completed,
Generate test and excitation operating process；
Step 202) generates the test operation process of each module in circuit-under-test, and the test operation process includes circuit test
Operating process and fault diagnosis operating process, the circuit testing operation process is for determining that each module is normal or failure shape
State, and fault diagnosis operating process is executed by the module to malfunction, to acquire the sound obtained for judging fault type
Answer data；
Step 203) is by the test and excitation operating process in step 201), the circuit testing operation process in step 202) and failure
Diagnostic operation process is respectively written into specified flow file；
Testing process execution module: for executing the text comprising test and excitation operating process generated in testing process generation module
Part, the file comprising test operation process, control test equipment realize test and fault location to circuit.
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| CN111858216B (en) * | 2020-07-23 | 2024-09-24 | 记忆科技(深圳)有限公司 | Method, device, equipment and medium for improving testability coverage rate of SSD |
| CN112485644B (en) * | 2020-11-26 | 2024-04-05 | 惠州市德赛西威汽车电子股份有限公司 | Fault detection circuit, fault detection system and method |
| CN114441947A (en) * | 2021-12-24 | 2022-05-06 | 成都天奥测控技术有限公司 | Automatic test system signal routing method based on ATML |
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