CN106506005B - Background calibration circuit and method for eliminating breakpoints in pipeline analog-to-digital converter transmission curve - Google Patents
Background calibration circuit and method for eliminating breakpoints in pipeline analog-to-digital converter transmission curve Download PDFInfo
- Publication number
- CN106506005B CN106506005B CN201610943059.3A CN201610943059A CN106506005B CN 106506005 B CN106506005 B CN 106506005B CN 201610943059 A CN201610943059 A CN 201610943059A CN 106506005 B CN106506005 B CN 106506005B
- Authority
- CN
- China
- Prior art keywords
- calibration
- digital converter
- res
- analog
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000005540 biological transmission Effects 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000009466 transformation Effects 0.000 claims description 4
- 238000012937 correction Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 230000008859 change Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses it is a kind of the invention discloses it is a kind of eliminate production line analog-digital converter transmission curve breakpoint background calibration circuit and method, the calibration method is suitable for flow-line modulus converter, mainly calibrates analog-digital converter transmission curve breakpoint caused by more bit first order or capacitance mismatch in what preceding circuit and amplifier finite gain.Circuit mainly includes multi-stage pipeline analog-digital converter main circuit, delay alignment, dislocation summation module, calibration parameter computing module, and N bit counter exports calibration module.Pass through the calibration of this method, can numeric field eliminate because of capacitance mismatch and amplifier finite gain error caused by transmission curve breakpoint error, calibration method is simple and easy, does not change main circuit structure, the transformed error for significantly reducing production line analog-digital converter, improves its linearity and signal-to-noise ratio.
Description
Technical field
The present invention relates to the background calibration circuits and method of eliminating production line analog-digital converter transmission curve breakpoint, especially suitable
For the transformed error as caused by capacitance mismatch in circuit and amplifier finite gain.
Background technique
Analog-digital converter is the circuit module for converting analog signals into digital signal, in sensing system, is automatically controlled
It is all essential module in system and modern communication systems.Flow-line modulus converter takes in terms of speed and precision two
Good trade-off was obtained, therefore, becomes the only selection of the stringent application of requirement of high-speed, high precision.In high speed and super precision
In the production line analog-digital converter circuit of degree, there are a large amount of non-ideal characteristics, such as capacitance mismatch, amplifier finite gain to miss
Difference, amplifier are non-linear etc., and the performance of analog-digital converter is made to degenerate.Fig. 3 is common the first level production line of 1.5bit modulus
The transfer curve of converter (with error caused by non-ideal factor) input signal and output residual signal, it can be seen that non-
Perfect error results in the deviation of each section of slope of curve；Fig. 4 is analog-digital converter entirety transfer curve, it can be seen that is being adjudicated
At level-Vref/4 and Vref/4, due to the presence of error, results in analog-digital converter entirety transmission function and breakpoint occurs,
Lead to biggish error and non-linear.The reduction of this performance under the technological development trend being increasingly miniaturized instantly increasingly
Seriously.
In order to inhibit the influence of non-ideal factor, high performance production line analog-digital converter is calibrated.Calibration point
For analog calibration and digital calibration.Analog calibration be in the circuit of analog-digital converter additionally increase calibration circuit, to error into
Row calibration, therefore analog calibration needs to increase additional chip area and power consumption.And the integrated circuit technology development being miniaturized becomes
Gesture allows digital circuit to obtain faster speed and smaller power consumption, more advantageous relative to analog circuit, so number
The method of word calibration is more more favourable than analog calibration.Digital calibration has Foreground calibration and background calibration, and Foreground calibration is in modulus
Converter starts to carry out calibration process before conversion, extracts circuit error parameter, then will accidentally in next conversion process
Subtractive is gone, and calibration only carries out in system electrification primary；Background calibration is then to carry out error in the analog-to-digital conversion device course of work
It extracts and calibration operation, calibration carries out in system work process always with conversion process.Due to the parameter of circuit, capacitor is removed
It outside mismatch, can all drift about during the work time, therefore the scheme of Foreground calibration has certain limitation.And background calibration exists
It is carried out always in the circuit course of work, avoids this problem.But background calibration generally requires to introduce pseudo random number, calibration electricity
Road is complex, and needs longer convergence time.
Summary of the invention
Goal of the invention: in order to overcome the deficiencies in the prior art, the present invention provides a kind of for eliminating assembly line mould
The background calibration circuit and method of number converter transmission curve breakpoint reduce capacitance mismatch, amplifier finite gain error convection current
The performance of the first order circuit of waterline type analog-to-digital converter or even whole analog-digital converter influences, and calibration circuit does not need to introduce pseudo-
The modules such as random number, solve the deficiencies in the prior art.
Technical solution: to achieve the above object, the technical solution adopted by the present invention are as follows: be used for flow-line modulus converter
The background calibration circuit that transmission curve breakpoint is eliminated, which is characterized in that including multi-stage pipeline analog-digital converter main circuit, delay
Alignment, dislocation summation module, calibration parameter computing module, N bit counter and output calibration module；
The multi-stage pipeline analog-digital converter main circuit is analog-digital converter circuit to be calibrated, generates conversion numbers at different levels
Word amount；Wherein the same level ADC is level-one to be calibrated, is 1.5bit structure；Prime ADC and rear class ADC is respectively grade to be calibrated
Front and rear grade；It is above-mentioned at different levels all with 1 redundant digit for error correction；
The delay alignment, dislocation summation module are realized will be at different levels with superfluous in multi-stage pipeline analog-digital converter main circuit
Not calibrated output digital quantity D is calculated in remaining position output result arrangementOut, coarse；
The calibration parameter computing module according to output digital quantity Dn and Dres extracting parameter g1l, g1r, g2l, g2r, and
Calibration parameter g1, g2 is calculated by algorithm；
The N bit counter is according to sample clock frequency from zero to 2N- 1 carries out cycle count, and exports after meter is full
Calibration control signal rst control calibration calculates；
The output digital quantity D after calibration is calculated using calibration parameter g1, g2 for the output calibration moduleOut, fine；
Analog signal inputs the multi-stage pipeline analog-digital converter main circuit, passes through prime ADC, the same level ADC and rear class
ADC exports the output signal with a redundancy respectively, and above-mentioned output signal is as delay alignment, the input of dislocation summation module
Signal；Wherein the output signal of the same level ADC and the output signal of rear class ADC are used as the input of calibration parameter computing module to believe simultaneously
Number；The output signal of N bit counter is calibration control signal rst, the input signal as calibration parameter computing module；Delay
It is aligned, the output signal conduct of the output signal, the output signal of the same level ADC and calibration parameter computing module of dislocation summation module
The input signal for exporting calibration module obtains overall output signal after output calibration module calibration.
Further, a kind of school for the background calibration circuit eliminated for flow-line modulus converter transmission curve breakpoint
Quasi- method, which is characterized in that method includes the following steps:
1) calibration parameter g1, g2 is set to zero；
2) variable g1l, g2l are set to minimum value MIN, as zero, variable g1r, g2r are set to maximum value MAX, i.e., it is digital
To be all ' 1 '；
3) the transformation result prime ADC at different levels for obtaining analog-digital converter main circuit export Dn-1, and the same level ADC exports Dn,
Rear class ADC exports Dres；
If 4) Dn=' 00 ', work as DresWhen > g1l, g1l is set to Dres, otherwise directly go to step 5)；
If Dn=' 10 ', work as DresWhen < g2r, g2r is set to Dres, otherwise directly go to step 5)；
If Dn=' 01 ', work as DresWhen > g2l, g2l is set to Dres；Work as DresWhen < g1r, g1r is set to Dres, two kinds of situations
It does not comply with, directly goes to step 5)；
If 5) Dn=' 00 ', according to DOut, fine=Dres+2m-1Dn+2mDn-1+ g1 exports result after calculating calibration；
If Dn=' 10 ', according to DOut, fine=Dres+2m-1Dn+2mDn-1- g2 exports result after calculating calibration；
If Dn=' 01 ', according to formula DOut, fine=Dres+2m-1Dn+2mDn-1Result is exported after calculating calibration；After wherein m is
Grade ADC converts digit, i.e. DresDigit；
Wherein m is that rear class ADC converts digit, i.e. DresDigit；
If 6) detect, counter counts are full, calculate calibration parameter according to following formula:
It calculates and updates calibration parameter g1, g2, then go to step 2)；If not counting completely, step 3) is gone to.
The utility model has the advantages that production line analog-digital converter background calibration algorithm provided by the invention can be in background calibration by capacitor
Mismatch, amplifier finite gain bring transmission curve breakpoint error, significantly improve the performance of analog-digital converter, and it is linear to improve it
Degree and signal-to-noise ratio.Meanwhile the calibration method does not change original circuit structure of production line analog-digital converter, does not increase any simulation
Circuit overhead only increases calibration parameter computing module, N bit counter, output three numbers of calibration module outside original circuit
Word circuit module, calibration circuit structure is simple, and hardware spending is small, and calibration calculates simple and quick.
Detailed description of the invention
Fig. 1 is integrated circuit figure of the invention；
Fig. 2 is flow chart of the method for the present invention；
Fig. 3 is 1.5 bit flow-line modulus converter the same level ADC with capacitance mismatch, amplifier finite gain error
For the margin voltage Vres (ordinate) of output with input voltage vin (abscissa) change curve, solid line is song ideally
Line, dotted line are the curve actually having in the case of error；
Fig. 4 is converter overall transfer curve, and abscissa is input voltage, and ordinate is output digital quantity.
Specific embodiment
The present invention will be further explained with reference to the accompanying drawing.
A kind of background calibration circuit eliminated for flow-line modulus converter transmission curve breakpoint, it is main in application
For calibrating the transformed error of the first order or what preceding circuit, to simplify the analysis, first order error is only calibrated herein.Such as Fig. 1 institute
Show, including multi-stage pipeline analog-digital converter main circuit, delay alignment, dislocation summation module, calibration parameter computing module, N
Bit counter exports calibration module；Wherein:
The multi-stage pipeline analog-digital converter main circuit is analog-digital converter circuit to be calibrated, generates conversion numbers at different levels
Word amount, transformation result have transformed error, and wherein the same level ADC is level-one to be calibrated, are 1.5bit structure, transfer function
It is at different levels to be all used for error correction with 1 redundant digit such as the forward and backward grade that Fig. 3, prime ADC and rear class ADC are grade to be calibrated；
The delay alignment, dislocation summation module, which are realized, is calculated non-school with redundant digit output result arrangement at different levels
Quasi- output digital quantity DOut, coarse；
The calibration parameter computing module according to output digital quantity Dn and Dres extracting parameter g1l, g1r, g2l, g2r, and
Calibration parameter g1, g2 is calculated by algorithm；
The N bit counter is according to sample clock frequency from zero to 2N- 1 carries out cycle count, and exports after meter is full
Signal rst control calibration is controlled to calculate；
The output digital quantity D after calibration is calculated using calibration parameter g1, g2 for the output calibration moduleOut, fine。
For eliminating the background calibration method of production line analog-digital converter transmission curve breakpoint, which is characterized in that including such as
Lower specific steps (such as Fig. 2):
Step 1, calibration parameter g1, g2 is set to zero；
Step 2, variable g1l, g2l are set to minimum value MIN, as zero, variable g1r, g2r are set to maximum value MAX, i.e.,
Number is to be all ' 1 '；
Step 3, the transformation result D at different levels of analog-digital converter main circuit are obtainedn-1, Dn, Dres；
Step 4, if Dn=' 00 ', work as DresWhen > g1l, g1l is set to Dres, otherwise pass directly to step 5；If Dn=
' 10 ', work as DresWhen < g2r, g2r is set to Dres, otherwise pass directly to step 5；If Dn=' 01 ' works as DresWhen > g2l, by g2l
It is set to Dres, as Dres < g1r, g1r is set to Dres, do not meet either way, pass directly to step 5；
Step 5,
If Dn=' 00 ', according to DOut, fine=Dres+2m-1Dn+2mDn-1+ g1 exports result after calculating calibration；
If Dn=' 10 ', according to DOut, fine=Dres+2m-1Dn+2mDn-1- g2 exports result after calculating calibration；
If Dn=' 01 ', according to formula DOut, fine=Dres+2m-1Dn+2mDn-1Result is exported after calculating calibration；Wherein m is
Rear class ADC converts digit, i.e. DresDigit；
Step 6, if detecting, counter counts are full, calculate calibration parameter according to following formula:
It calculates and updates calibration parameter g1, g2, then go to step 2；If not counting completely, step 3 is gone to.
The above is only a preferred embodiment of the present invention, it should be pointed out that: for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (2)
1. eliminating the background calibration circuit of production line analog-digital converter transmission curve breakpoint, which is characterized in that including multistage flowing water
Line analog-digital converter main circuit, delay alignment, dislocation summation module, calibration parameter computing module, N bit counter and output school
Quasi-mode block；
The multi-stage pipeline analog-digital converter main circuit is analog-digital converter circuit to be calibrated, generates conversion numbers at different levels
Amount；Wherein the same level ADC is level-one to be calibrated, is 1.5bit structure；Before prime ADC and rear class ADC is respectively grade to be calibrated
And rear class；It is above-mentioned at different levels all with 1 redundant digit for error correction；
The delay alignment, dislocation summation module, which are realized, has redundant digit at different levels in multi-stage pipeline analog-digital converter main circuit
Not calibrated output digital quantity D is calculated in output result arrangementOut, coarse；
The calibration parameter computing module passes through according to output digital quantity Dn and Dres extracting parameter g1l, g1r, g2l, g2r
Calibration parameter g1, g2 is calculated in algorithm；
The N bit counter is according to sample clock frequency from zero to 2N- 1 carries out cycle count, and the output calibration control after meter is full
Signal rst control calibration processed calculates；
The output digital quantity D after calibration is calculated using calibration parameter g1, g2 for the output calibration moduleOut, fine；
Analog signal inputs the multi-stage pipeline analog-digital converter main circuit, passes through prime ADC, the same level ADC and rear class ADC points
The output signal of a redundancy Shu Chu not be had, above-mentioned output signal is as delay alignment, the input signal of dislocation summation module；
Wherein the output signal of the same level ADC and the output signal of rear class ADC are used as the input signal of calibration parameter computing module simultaneously；N
The output signal of bit counter is calibration control signal rst, the input signal as calibration parameter computing module；Delay alignment,
The output signal conduct output of the output signal, the output signal of the same level ADC and calibration parameter computing module of the summation module that misplaces
The input signal of calibration module obtains overall output signal after output calibration module calibration.
2. eliminating the calibration side of the background calibration circuit of production line analog-digital converter transmission curve breakpoint as described in claim 1
Method, which is characterized in that method includes the following steps:
1) calibration parameter g1, g2 is set to zero；
2) variable g1l, g2l are set to minimum value MIN, as zero, variable g1r, g2r is set to maximum value MAX, i.e., number is complete
It is ' 1 '；
3) the transformation result prime ADC at different levels for obtaining analog-digital converter main circuit export Dn-1, the same level ADC output Dn, rear class ADC
Export Dres；
If 4) Dn=' 00 ', work as DresWhen > g1l, g1l is set to Dres, otherwise directly go to step 5)；
If Dn=' 10 ', work as DresWhen < g2r, g2r is set to Dres, otherwise directly go to step 5)；
If Dn=' 01 ', work as DresWhen > g2l, g2l is set to Dres；Work as DresWhen < g1r, g1r is set to Dres, either way
It does not meet, directly goes to step 5)；
If 5) Dn=' 00 ', according to DOut, fine=Dres+2m-1Dn+2mDn-1+ g1 exports result after calculating calibration；
If Dn=' 10 ', according to DOut, fine=Dres+2m-1Dn+2mDn-1- g2 exports result after calculating calibration；
If Dn=' 01 ', according to formula DOut, fine=Dres+2m-1Dn+2mDn-1Result is exported after calculating calibration；Wherein m is rear class
ADC converts digit, i.e. DresDigit；
If 6) detect, counter counts are full, calculate calibration parameter according to following formula:
It calculates and updates calibration parameter g1, g2, then go to step 2)；If not counting completely, step 3) is gone to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610943059.3A CN106506005B (en) | 2016-10-26 | 2016-10-26 | Background calibration circuit and method for eliminating breakpoints in pipeline analog-to-digital converter transmission curve |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610943059.3A CN106506005B (en) | 2016-10-26 | 2016-10-26 | Background calibration circuit and method for eliminating breakpoints in pipeline analog-to-digital converter transmission curve |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106506005A CN106506005A (en) | 2017-03-15 |
| CN106506005B true CN106506005B (en) | 2019-04-09 |
Family
ID=58321745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610943059.3A Active CN106506005B (en) | 2016-10-26 | 2016-10-26 | Background calibration circuit and method for eliminating breakpoints in pipeline analog-to-digital converter transmission curve |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106506005B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113114247B (en) * | 2021-04-19 | 2022-05-24 | 电子科技大学 | Pipeline ADC interstage gain calibration method based on comparison time detector |
| CN115987281A (en) * | 2022-12-31 | 2023-04-18 | 重庆吉芯科技有限公司 | High-speed high-precision analog-to-digital converter and performance improvement method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103460605A (en) * | 2011-03-31 | 2013-12-18 | 美国亚德诺半导体公司 | Pipelined ADC having error correction |
| CN105959005A (en) * | 2016-04-20 | 2016-09-21 | 北京交通大学 | Digital background calibration device for pipeline ADC |
| CN106027051A (en) * | 2016-05-12 | 2016-10-12 | 东南大学 | Background calibration circuit and calibration method for pipelined analog-to-digital converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7623050B2 (en) * | 2005-12-13 | 2009-11-24 | Broadcom Corporation | Digital calibration loop for an analog to digital converter |
-
2016
- 2016-10-26 CN CN201610943059.3A patent/CN106506005B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103460605A (en) * | 2011-03-31 | 2013-12-18 | 美国亚德诺半导体公司 | Pipelined ADC having error correction |
| US9148161B2 (en) * | 2011-03-31 | 2015-09-29 | Analog Devices, Inc. | Pipelined ADC having error correction |
| CN105959005A (en) * | 2016-04-20 | 2016-09-21 | 北京交通大学 | Digital background calibration device for pipeline ADC |
| CN106027051A (en) * | 2016-05-12 | 2016-10-12 | 东南大学 | Background calibration circuit and calibration method for pipelined analog-to-digital converter |
Non-Patent Citations (1)
| Title |
|---|
| "高精度流水线A/D转换器系统建模和校准技术";黄敏慧;《中国优秀硕士学位论文全文数据库 信息科技辑》;20141015(第10期);38-42 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106506005A (en) | 2017-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108471313B (en) | A TIADC system calibration method based on digital-analog mixed signal | |
| CN102386921B (en) | Mismatch calibration method for streamline ADC (Analog-to-Digital Converter) multi-bit sub DAC (Digital-to0Analog Converter) capacitor | |
| CN104639164B (en) | Binary capacitor array and its redundancy calibration method applied to single-ended SAR ADC | |
| CN106027051B (en) | A kind of background calibration circuit and calibration method suitable for production line analog-digital converter | |
| CN103051339B (en) | A kind of AD sampling value correcting method and system | |
| CN107359878B (en) | A Front-End Calibration Method for Pipeline ADC Based on Minimum Quantization Error | |
| CN201957001U (en) | Pipeline analog-to-digital converter capable of carrying out background digital calibration | |
| CN103078640B (en) | A kind of RLS adaptive-filtering calibration steps for ADC | |
| CN101465649A (en) | Comparator with adjustable reference voltage | |
| CN102353836A (en) | Method for dynamically adjusting current channel gain of wide-range electric energy meter | |
| CN101924554B (en) | Common mode error calibrating circuit of charge coupled pipeline analog-to-digital converter (ADC) | |
| CN107453756B (en) | Front-end calibration method for pipeline ADC | |
| CN105141312B (en) | A kind of digital background calibration algorithm of N channel time domain intertexture analog-digital converter clock jitter | |
| CN107070450A (en) | Multichannel DAC phase errors calibration circuit based on charge-domain signal transacting | |
| CN109150183A (en) | The Capacitor Mismatch Calibration of SAR-ADC based on metastable state detection | |
| CN112737583B (en) | A high-precision pipeline ADC and front-end calibration method | |
| CN115021754B (en) | TIADC sampling time mismatch digital correction method and system | |
| CN106899300B (en) | A redundant cyclic averaging method for successive approximation analog-to-digital converters | |
| CN106506005B (en) | Background calibration circuit and method for eliminating breakpoints in pipeline analog-to-digital converter transmission curve | |
| CN101888246A (en) | Charge coupling pipelined analogue-to-digital converter with error correction function | |
| CN111917413A (en) | Method for calibrating time sequence deviation between TI-ADC (time delay-analog converter) channels | |
| CN110504966B (en) | Calibration system and method of analog-to-digital converter | |
| CN112564703B (en) | A Foreground Time Error Correction Circuit for Multi-channel Time Domain Interleaved Data Converter | |
| CN102006071B (en) | Allowance gain circuit for analog-to-digital converter in pipeline structure | |
| CN107272395B (en) | Time-to-digit converter and its conversion method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |