CN106505069B - A kind of eeprom memory part and preparation method thereof, electronic device - Google Patents
A kind of eeprom memory part and preparation method thereof, electronic device Download PDFInfo
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- CN106505069B CN106505069B CN201510566157.5A CN201510566157A CN106505069B CN 106505069 B CN106505069 B CN 106505069B CN 201510566157 A CN201510566157 A CN 201510566157A CN 106505069 B CN106505069 B CN 106505069B
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- 229910052751 metal Inorganic materials 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
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- 238000002347 injection Methods 0.000 description 11
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- 238000007667 floating Methods 0.000 description 9
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
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Abstract
The present invention relates to a kind of eeprom memory parts and preparation method thereof, electronic device.The method includes the steps S1: providing substrate, is formed with gate structure over the substrate, is formed with drain region in the substrate of the gate structure side, be also formed with dummy gate structure on the substrate between the gate structure and the drain region；Step S2: above the dummy gate structure, the gate structure close to the dummy gate structure a upper side and drain region central area two sides top formed self-aligned silicide barrier layer；Step S3: self-alignment silicide layer is formed in the top of side and the drain region central area of the gate structure far from the dummy gate structure.The preparation method of the structure, which only passes through, increases by two patterned mask layers, i.e., gate patterning mask layer and from can be realized to silicide mask layer, and processing step is simple, not will cause the increase of cost, while can greatly improve device performance.
Description
Technical field
The present invention relates to semiconductor field, in particular it relates to a kind of eeprom memory part and preparation method thereof,
Electronic device.
Background technique
Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable ProgrammableRead-
Only Memory), it is the storage chip that data are not lost after a kind of power down；It can be wiped on computers or on special equipment
Existing information, reprograms.EEPROM is nonvolatile memory, and flash-EEPROM therein is quickly grown.EEPROM ratio
DRAM is complicated, therefore the integrated level of EEPROM is difficult to improve.
The part of the storage information of one EEPROM memory cell is just as a normally closed or normally opened transistor, when floating gate fills
When electric, accommodate charge or electronics is hindered to flow to silicon from control gate；Charging is electric in applying on control gate by the way that source/drain to be grounded
Pressure is to complete；Apply backward voltage, flow of charge silicon substrate will be made.In this way, storing 1 (bit) number based on a storage unit
According to large-scale memory cell array structure, chip size increases.
With the continuous diminution of dimensions of semiconductor devices, chip acupuncture treatment test (the circuit prober of EEPROM
Test, CP) yield decline, the reason of finding after physical analysis and electroanalysis, causing the problem is in some CP test
High pressure NMOS part is caused the destruction of grid oxygen by high pressure induction, makes the breakdown performance and saturated drain current (Idsat) of device
It is affected, reduces the performance and yield of device.
Therefore, it is necessary to be improved further to current described high pressure NMOS part and preparation method thereof, on eliminating
State problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of preparation method of eeprom memory part, comprising:
Substrate；
Gate structure is located on the substrate；
Drain region, in the substrate of the gate structure side；
Dummy gate structure, on the substrate between the gate structure and the drain region；
Self-alignment silicide layer, far from the leakage above the central area in the drain region and on the gate structure
The top of the side in area.
Optionally, interconnection structure is also formed with above the self-alignment silicide layer.
Optionally, clearance wall, the grid are also formed on the gate structure and the side wall of the dummy gate structure
The clearance wall of structure contacts or is isolated with the clearance wall of the dummy gate structure.
Optionally, deep leakage is formed between the gate structure and the dummy gate structure in the substrate of lower section to mix
Miscellaneous region.
Optionally, the drain region is also formed with deep leakage doped region.
The present invention also provides a kind of preparation methods based on above-mentioned eeprom memory part, comprising:
Step S1: substrate is provided, is formed with gate structure over the substrate, the lining in the gate structure side
It is formed with drain region in bottom, is also formed with dummy gate structure on the substrate between the gate structure and the drain region；
Step S2: above the dummy gate structure, the gate structure is close to the side of the dummy gate structure
The top of top and drain region central area two sides forms self-aligned silicide barrier layer；
Step S3: in side of the gate structure far from the dummy gate structure and the drain region central area
Top forms self-alignment silicide layer.
Optionally, under may further include between the gate structure and the dummy gate structure in the step S1
The step of deep leakage doped region is formed in the substrate of side.
Optionally, the step S1 includes:
Step S11: gate material layers are formed over the substrate；
Step S12: forming patterned mask layer in the gate material layers, to define the gate structure and described
The shape of dummy gate structure；
Step S13: using the mask layer as gate material layers described in mask etch, to form the gate structure and described
Dummy gate structure.
Optionally, it may further include the step of drain region executes deep leakage doping after forming the drain region, with
Form deep leakage doped region.
The present invention also provides a kind of electronic devices, including above-mentioned eeprom memory part.
In order to solve the problems in the existing technology the present invention, provides a kind of eeprom memory part and its preparation side
Method is inserted into dummy gate structure between gate structure end and drain terminal in the high-pressure MOS of eeprom memory part of the present invention,
The breakdown voltage of high-pressure MOS component can be improved by the change of the structure, while will not influence other property of high-pressure MOS
Can, further improve the performance and yield of eeprom memory part.
In addition, the preparation method of the structure, which only passes through, increases by two patterned mask layers, i.e., gate patterning exposure mask
Layer and from can be realized to silicide mask layer, processing step is simple, not will cause the increase of cost, while can greatly mention
High device performance.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the structural schematic diagram of eeprom memory part described in the embodiment of the invention；
Fig. 2 is the preparation process schematic diagram of eeprom memory part described in the embodiment of the invention；
Fig. 3 is the preparation technology flow chart of eeprom memory part described in the embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Embodiment 1
In order to solve the problems in the existing technology, the present invention provides a kind of preparation sides of eeprom memory part
Method, 1 pair of eeprom memory part is described further with reference to the accompanying drawing.
In order to solve the problems in the existing technology the present invention provides a kind of eeprom memory part, including high-voltage field
Effect transistor, wherein the high voltage field effect transistor includes:
Substrate 101；
Gate structure 102 is located on the substrate 101；
Drain region, in the substrate 101 of 102 side of gate structure；
Dummy gate structure 103, on the substrate between the gate structure 102 and the drain region；
Self-alignment silicide layer 110, far from institute above the central area in the drain region and on the gate structure
State the top of the side in drain region.
In this embodiment, the nonvolatile memory EEPROM can be separate gate structures.With separate gate structures
EEPROM include control gate, the grid of floating gate and high voltage transistor, wherein control gate is set on floating gate, control gate and floating gate
The two is side compensation (laterally offset).Wherein, high voltage transistor is that high pressure field-effect of the present invention is brilliant
Body pipe below will be described in detail the part, it should be noted that eeprom memory part can further include
Other customary components, such as floating gate, control gate as known to those skilled in the art etc. are no longer done in detail herein in order to avoid obscuring
Most explanation.
Wherein, the substrate can be following at least one of the material being previously mentioned: silicon, silicon-on-insulator (SOI), absolutely
Silicon (SSOI) is laminated on edge body, SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and absolutely are laminated on insulator
Germanium (GeOI) etc. on edge body.
In this embodiment, the substrate selects silicon or polysilicon, and further, the substrate selects P-type silicon substrate.
Wherein, the gate structure 102 and dummy gate structure 103 are disposed adjacent, the gate structure 102 and virtual grid
Pole structure 103 can be common gate structure in eeprom memory part, such as polysilicon gate, but be not limited to that should
Example.
Further, the gate structure 102 and dummy gate 103 can be formed or are respectively formed by a step,
It is not limited to a certain kind.
Such as the forming method of the gate structure 102 and dummy gate 103 may include: to form grid over the substrate
Then pole material layer, such as polysilicon form patterned gate mask layer, such as photoresist in the gate material layers
Layer, then using the mask layer as gate material layers described in mask etch, to form the gate structure 102 and dummy gate knot
Structure 103.
As the embodiment of replaceability, it can also be respectively formed the gate structure 102 and dummy gate structure 103,
The gate structure 102 and dummy gate structure 103 can also select different materials, wherein the dummy gate 103 is only
It plays and the gate structure and the drain region is isolated, therefore the dummy gate structure 103 can also be selected other than grid material
Material, such as dielectric material etc..
In the eeprom memory part, the drain region is located at the side of the dummy gate structure, i.e., far from described
One end of gate structure 102, wherein the forming method in the drain region is referred to the common method of this field.
In this embodiment, wherein the drain region includes N-type lightly doped region 104 and source and drain depth injection zone (Deep
Drain Doping, DDD) 105, so that the depth of source-drain area intermediate ion injection is bigger, as shown in Figure 1, selecting in this process
Large energy carries out ion implanting, to form source and drain in the substrate bottom.
The biggish source and drain injection (Deep Drain Doping, DDD) of depth is wherein carried out in the present invention, wherein described
The ionic type of source and drain injection and the concentration of doping can select range commonly used in the art.The doping selected in the present invention
Energy is 1000ev-30kev, can also be 1000-10k ev, to guarantee that its doping concentration can reach 5E17~1E25 original
Son/cm3。
Doping defect is reduced in order to improve, annealing steps can also be carried out after source and drain injection, specifically, execute the heat
Annealing steps eliminate the damage on silicon wafer, and minority carrier lifetime and mobility can obtain different degrees of recovery, impurity
Also a certain proportion of activation can be obtained, therefore device efficiency can be improved.The annealing steps are usually to be placed in the substrate
Under the protection of high vacuum or high-purity gas, it is heated to certain temperature and is heat-treated, it is preferred in high-purity gas of the present invention
For nitrogen or inert gas, the temperature of the thermal anneal step is 800-1200 DEG C, and the thermal anneal step time is 1-200s.
Rapid thermal annealing can be selected in the present invention, specifically, can select one of following methods: pulse
Laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent width
Band light source (such as halogen lamp, arc lamp, graphite heating) short annealing.Those skilled in the art, which can according to need, to be selected,
Also examples cited are not limited to.
Wherein, deep leakage doped region is also formed in the substrate of the gate structure one or both sides.Such as the grid
Deep leakage doped region 106 is formed with below substrate between pole structure and the dummy gate structure, and/or in the grid knot
Deep leakage doped region 108 is formed with below the substrate of the side of the separate dummy gate structure of structure, wherein the deep leakage doped region
The forming method in domain can be formed simultaneously with the drain region, naturally it is also possible to individually control Implantation Energy and depth as needed.
Further, source and drain ion implanted regions 107 can also be further included in the deep leakage doped region 108.
Optionally, deep leakage doping is formed with below the substrate of the side of the separate dummy gate structure of the gate structure
N-type doping region is also formed in region, the n-type doping region is located in the deep leakage doped region.
Further, the self-aligned silicide 110 is not the top at the top and entire drain region that are formed in entire gate structure
Portion reduces the area of the self-aligned silicide to improve breakdown performance in this embodiment, such as is only forming mutually connection
The place of structure forms the self-aligned silicide.
In this embodiment, the self-aligned silicide is only formed in the central area in the drain region, while only in grid
Self-aligned silicide is formed in the partial region of pole structural top, such as at the top of the gate structure far from the drain region
Form the self-aligned silicide 110.
The forming method of the self-aligned silicide includes but is not limited to: above the dummy gate structure and described
Gate structure forms self-aligned silicide close to the side of the dummy gate structure, the top of drain region central area two sides
Barrier layer；It is formed in the top of side and the drain region central area of the gate structure far from the dummy gate structure
Self-alignment silicide layer.
Wherein, the self-aligned silicide barrier layer can select ability customary insulation material, such as in the present invention may be used
With preferred silica, the deposition method can be selection method commonly used in the art.
The forming method of the self-aligned silicide are as follows: then sputtered metal layer, such as nickel metal layer are rapidly heated
Annealing (RTA) technique, at metal silicide layer, it is voluntarily right to complete for the part reaction for contacting metal layer with grid and drain region
Metalloid silicide process (salicide).Then use erodable metal layer, but will not attack metal silication layer region erosion
Agent is carved, unreacted metal layer is removed.
Further, interconnection structure 109 is also formed with above the self-aligned silicide, the interconnection structure can wrap
Include the combination of several metal throuth holes, contact hole and metal layer.
Optionally, the interconnection structure 109 includes connecing positioned at the top of the self-aligned silicide in this embodiment
Contact hole.
In order to solve the problems in the existing technology the present invention, provides a kind of eeprom memory part and its preparation side
Method is inserted into dummy gate structure between gate structure end and drain terminal in the high-pressure MOS of eeprom memory part of the present invention,
The breakdown voltage of high-pressure MOS component can be improved by the change of the structure, while will not influence other property of high-pressure MOS
Can, further improve the performance and yield of eeprom memory part.
In addition, the preparation method of the structure, which only passes through, increases by two patterned mask layers, i.e., gate patterning exposure mask
Layer and from can be realized to silicide mask layer, processing step is simple, not will cause the increase of cost, while can greatly mention
High device performance.
Embodiment 2
It is provided below and Fig. 2 and Fig. 3 is combined to make further the preparation method of eeprom memory part of the present invention
It is bright.
Firstly, executing step 101, substrate is provided, is formed with gate structure and drain region over the substrate, in the grid
Dummy gate structure is also formed between structure and the drain region.
Wherein, the nonvolatile memory EEPROM can be separate gate structures.EEPROM with separate gate structures
Including control gate, the grid of floating gate and high voltage transistor, wherein control gate is set on floating gate, and both control gate and floating gate are sides
Side compensates (laterally offset).Wherein, high voltage transistor is high voltage field effect transistor of the present invention, below
The part will be described in detail, it should be noted that eeprom memory part can further include art technology
Other customary components, such as floating gate, control gate etc. that personnel know no longer do detailed explanation in order to avoid obscuring herein.
Wherein, the substrate can be following at least one of the material being previously mentioned: silicon, silicon-on-insulator (SOI), absolutely
Silicon (SSOI) is laminated on edge body, SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and absolutely are laminated on insulator
Germanium (GeOI) etc. on edge body.
In this embodiment, the substrate selects silicon or polysilicon, and further, the substrate selects P-type silicon substrate.
Wherein, the gate structure 102 and dummy gate structure 103 are disposed adjacent, the gate structure 102 and virtual grid
Pole structure 103 can be common gate structure in eeprom memory part, such as polysilicon gate, but be not limited to that should
Example.
The gate structure 102 and dummy gate structure 103 can be formed or are respectively formed by a step, not
It is confined to a certain kind.
Such as the forming method of the gate structure 102 and dummy gate structure 103 may include: shape over the substrate
At gate material layers, such as polysilicon, patterned gate mask layer, such as photoetching are then formed in the gate material layers
Glue-line, then using the mask layer as gate material layers described in mask etch, to form the gate structure 102 and dummy gate
Structure 103.
As the embodiment of replaceability, it can also be respectively formed the gate structure 102 and dummy gate structure 103,
The gate structure 102 and dummy gate structure 103 can also select different materials, wherein the dummy gate structure 103
It functions only as that the gate structure and the drain region is isolated, therefore the dummy gate structure 103 can also select grid material
Material in addition, such as dielectric material etc..
In the eeprom memory part, the drain region is located at the side of the dummy gate, i.e., far from the grid
One end of structure 102, wherein the forming method in the drain region is referred to the common method of this field.
In this embodiment, wherein successively execute N-type shallowly adulterate and source and drain depth inject (Deep DrainDoping,
DDD) step, to be respectively formed N-type lightly doped region 104 and source and drain depth injection zone (Deep Drain Doping, DDD)
105, so that the depth of source-drain area intermediate ion injection is bigger, as shown in Fig. 2, selecting large energy to carry out ion note in this process
Enter, to form source and drain in the substrate bottom.
The biggish source and drain injection (Deep Drain Doping, DDD) of depth is wherein carried out in the present invention, wherein described
The ionic type of source and drain injection and the concentration of doping can select range commonly used in the art.The doping selected in the present invention
Energy is 1000ev-30kev, can also be 1000-10k ev, to guarantee that its doping concentration can reach 5E17~1E25 original
Son/cm3。
Doping defect is reduced in order to improve, annealing steps can also be carried out after source and drain injection, specifically, execute the heat
After annealing steps, the damage on silicon wafer can be eliminated, minority carrier lifetime and mobility can obtain different degrees of extensive
Multiple, impurity can also obtain a certain proportion of activation, therefore device efficiency can be improved.The annealing steps are usually by the lining
Bottom is placed under the protection of high vacuum or high-purity gas, is heated to certain temperature and is heat-treated, in high-purity gas of the present invention
Body is preferably nitrogen or inert gas, and the temperature of the thermal anneal step is 800-1200 DEG C, and the thermal anneal step time is
1-200s。
Rapid thermal annealing can be selected in the present invention, specifically, can select one of following methods: pulse
Laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent width
Band light source (such as halogen lamp, arc lamp, graphite heating) short annealing.Those skilled in the art, which can according to need, to be selected,
Also examples cited are not limited to.
Wherein, deep leakage doped region is also formed in the substrate of the gate structure one or both sides.Such as the grid
Deep leakage doped region is formed with below substrate between pole structure and the dummy gate structure, and/or in the gate structure
Separate dummy gate structure side substrate below be formed with deep leakage doped region, wherein the deep leakage doped region
Forming method can be formed simultaneously with the drain region, naturally it is also possible to individually control Implantation Energy and depth as needed.
Optionally, deep leakage doping is formed with below the substrate of the side of the separate dummy gate structure of the gate structure
N-type doping region is also formed in region, the n-type doping region is located in the deep leakage doped region.
The step of forming clearance wall can also be further included before executing source and drain injection, wherein the shape of the clearance wall
It is referred to common method at method, such as deposits spacer material layer first, is then etched, wherein the clearance wall
The deposition method of material layer can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or atomic layer deposition
(ALD) one of the low-pressure chemical vapor deposition (LPCVD) of the formation such as method, laser ablation deposition (LAD) and epitaxial growth.
Further, the deposition method of the spacer material layer can be selected atomic layer deposition (ALD), and preferably low temperature is former
Sublayer deposits (ALD).
Step 102 is executed, above the dummy gate structure and the gate structure is close to the dummy gate knot
The side of structure, drain region central area two sides top formed self-aligned silicide barrier layer, then in the gate structure
The top of side and the drain region central area far from the dummy gate structure forms self-alignment silicide layer.
Specifically, as shown in Fig. 2, the self-aligned silicide is not the top for being formed in entire gate structure and entire leakage
The top in area reduces the area of the self-aligned silicide to improve breakdown performance in this embodiment, such as is only being formed
The place of interconnection structure forms the self-aligned silicide.
In this embodiment, the self-aligned silicide is only formed in the central area in the drain region, while only in grid
Self-aligned silicide is formed in the partial region of pole structural top, such as at the top of the gate structure far from the drain region
Form the self-aligned silicide 110.
The forming method of the self-aligned silicide includes but is not limited to: above the dummy gate structure and described
Gate structure forms self-aligned silicide barrier layer 111 close to a upper side of the dummy gate structure, while in the leakage
The top of district center region two sides forms self-aligned silicide barrier layer 112；In the gate structure far from the dummy gate
The top of the side of structure and the drain region central area forms self-alignment silicide layer.
Wherein, the self-aligned silicide barrier layer can select ability customary insulation material, such as in the present invention may be used
With preferred silica, the deposition method can be selection method commonly used in the art.
The forming method of the self-aligned silicide are as follows: then sputtered metal layer, such as nickel metal layer are rapidly heated
Annealing (RTA) technique, at metal silicide layer, it is voluntarily right to complete for the part reaction for contacting metal layer with grid and drain region
Metalloid silicide process (salicide).Then use erodable metal layer, but will not attack metal silication layer region erosion
Agent is carved, unreacted metal layer is removed.
Step 103 is executed, interconnection structure 109, the interconnection structure are also formed with above the self-aligned silicide
It may include the combination of several metal throuth holes, contact hole and metal layer.
Optionally, the interconnection structure 109 includes connecing positioned at the top of the self-aligned silicide in this embodiment
Contact hole.
So far, the introduction of the correlation step of the eeprom memory part preparation of the embodiment of the present invention is completed.In above-mentioned step
It can also include other correlation steps, details are not described herein again after rapid.Also, in addition to the foregoing steps, the system of the present embodiment
Preparation Method can also include other steps among above-mentioned each step or between different steps, these steps can pass through
Various techniques in the prior art realize that details are not described herein again.
Fig. 3 be the embodiment of the invention described in semiconductor devices preparation technology flow chart, specifically include with
Lower step:
Step S1: substrate is provided, is formed with gate structure over the substrate, the lining in the gate structure side
It is formed with drain region in bottom, is also formed with dummy gate structure on the substrate between the gate structure and the drain region；
Step S2: above the dummy gate structure, the gate structure is close to the side of the dummy gate structure
The top of top and drain region central area two sides forms self-aligned silicide barrier layer；
Step S3: in side of the gate structure far from the dummy gate structure and the drain region central area
Top forms self-alignment silicide layer.
Embodiment 3
The present invention also provides a kind of electronic devices, including eeprom memory part described in embodiment 1.Wherein,
Eeprom memory part is eeprom memory part described in embodiment 1, or obtained according to preparation method as described in example 2
Eeprom memory part.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the eeprom memory part.The electronic device of the embodiment of the present invention, it is above-mentioned due to having used
Eeprom memory part, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of eeprom memory part, including high voltage field effect transistor, wherein the high voltage field effect transistor includes:
Substrate；
Gate structure is located on the substrate；
Drain region, in the substrate of the gate structure side；
Dummy gate structure, on the substrate between the gate structure and the drain region；
Self-alignment silicide layer, far from the drain region above the central area in the drain region and on the gate structure
The top of side, the self-alignment silicide layer part cover the drain region and the gate structure.
2. eeprom memory part according to claim 1, which is characterized in that in the top of the self-alignment silicide layer
It is also formed with interconnection structure.
3. eeprom memory part according to claim 1, which is characterized in that the gate structure and the dummy gate
Clearance wall is also formed on the side wall of structure, between the clearance wall of the gate structure and the described of the dummy gate structure
The contact of gap wall or isolation.
4. eeprom memory part according to claim 1, which is characterized in that the gate structure and the dummy gate
Deep leakage doped region is formed between structure in the substrate of lower section.
5. eeprom memory part according to claim 1, which is characterized in that the drain region is also formed with deep leakage doped region
Domain.
6. a kind of preparation method based on eeprom memory part described in one of claim 1 to 5, comprising:
Step S1: substrate is provided, gate structure is formed with over the substrate, in the substrate of the gate structure side
It is formed with drain region, is also formed with dummy gate structure on the substrate between the gate structure and the drain region；
Step S2: above the dummy gate structure, the gate structure close to the dummy gate structure a upper side
Self-aligned silicide barrier layer is formed with the top of drain region central area two sides；
Step S3: in the top of side and the drain region central area of the gate structure far from the dummy gate structure
Form self-alignment silicide layer.
7. according to the method described in claim 6, it is characterized in that, may further include the grid knot in the step S1
The step of deep leakage doped region is formed between structure and the dummy gate structure in the substrate of lower section.
8. according to the method described in claim 6, it is characterized in that, the step S1 includes:
Step S11: gate material layers are formed over the substrate；
Step S12: forming patterned mask layer in the gate material layers, to define the gate structure and described virtual
The shape of gate structure；
Step S13: using the mask layer as gate material layers described in mask etch, to form the gate structure and described virtual
Gate structure.
9. according to the method described in claim 6, it is characterized in that, may further include after forming the drain region described
Drain region executes the step of deep leakage doping, to form deep leakage doped region.
10. a kind of electronic device, including eeprom memory part described in one of claim 1 to 5.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1124409A (en) * | 1994-07-18 | 1996-06-12 | 现代电子产业株式会社 | Eeprom and method for fabricating the same |
| CN101546772A (en) * | 2008-03-25 | 2009-09-30 | 恩益禧电子股份有限公司 | Semiconductor device including capacitor element and method of manufacturing the same |
| CN103178097A (en) * | 2011-12-23 | 2013-06-26 | 台湾积体电路制造股份有限公司 | Dummy gate for a high voltage transistor device |
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2015
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1124409A (en) * | 1994-07-18 | 1996-06-12 | 现代电子产业株式会社 | Eeprom and method for fabricating the same |
| CN101546772A (en) * | 2008-03-25 | 2009-09-30 | 恩益禧电子股份有限公司 | Semiconductor device including capacitor element and method of manufacturing the same |
| CN103178097A (en) * | 2011-12-23 | 2013-06-26 | 台湾积体电路制造股份有限公司 | Dummy gate for a high voltage transistor device |
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