CN106354592A - Computer automatic startup and shutdown testing device - Google Patents
Computer automatic startup and shutdown testing device Download PDFInfo
- Publication number
- CN106354592A CN106354592A CN201610677989.9A CN201610677989A CN106354592A CN 106354592 A CN106354592 A CN 106354592A CN 201610677989 A CN201610677989 A CN 201610677989A CN 106354592 A CN106354592 A CN 106354592A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- General Engineering & Computer Science (AREA)
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- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention relates to a computer automatic startup and shutdown testing device. The testing device comprises a LPC bus interface module connected with a to-be-tested computer main board LPC bus interface, an FPGA control module connected with the LPC bus interface module, a display module connected with the FPGA control module, a warning module connected with the FPGA control module, and an outage interface module connected with a PSON interface of an ATX power source, wherein the outage interface module is connected with the FPGA control module. Computer startup and shutdown testing work can be finished in the shortest time, and testing work efficiency is greatly improved; the number of times of startup and shutdown can be counted and displayed, testing staff can conveniently monitor the experiment process, startup failure states can be warned and prompted, and the testing staff can be conveniently informed in time.
Description
Technical field
The invention belongs to computer testing technology field is and in particular to a kind of computer automatic powering-on/powering-off test device.
Background technology
In Computer Design and field tests, for ensureing high reliability and the stability of computer product, in product can
Often require that mainboard is carried out with multiple switching machine test whether can after computer electrifying startup to detect by property test link
Normally enter operating system, the number of times of this kind of switching on and shutting down test is possible to reach thousands of or up to ten thousand times, this kind of a large amount of and repeated
Work a kind of highly desirable test device that can automatically execute.Existing computer on-off testing device employs electric timing
Mode, that is, on to computer electricity after start timing, design one fixation delay duration after again power-off is carried out to computer,
This delay duration is made to be more than computer normal boot-strap duration, to reach the purpose of repetition automatic switching, although such device can
Realize the automatic switch machine testing function of computer, but the start duration due to variety classes computer motherboard not knowing, should
Delay duration setting is too small, is not enough to complete Auto Power On, delay duration setting is excessive and can consume the longer testing time,
It is unfavorable for improving work efficiency.Therefore, such computer on-off testing device still suffers from certain disadvantage in practical engineering application
End.
During computer electrifying startup, enter bios(basic input output before operating system
System, basic input output system) can detect that each hardware module whether there is and normally it is possible to communicate to lpc first
Bus sends bios code, and this process is computer post(power on self test, power-on self-test) process, in post
During, all hardware module last code to entrance operating system after sequence detection is normal is 16 characters
" ff ", therefore, this code normally can indicate as computer self-test.In addition, all comprising in conventional computer atx power supply
Pson control signal, when this signal is low, power supply is exportable, and when this signal is high, power supply does not export.Therefore, using computer
The feature code of post process and atx power supply characteristic propose a kind of new computer automatic powering-on/powering-off test device, are possibly realized.
Content of the invention
It is an object of the invention to solving above-mentioned technical problem and providing a kind of possessing certainly based on fpga and lpc bus
The computer automatic switching of dynamic switching on and shutting down test function, switching on and shutting down number of times statistics and display function and boot failure warning function
Test device, this device can be using the feature code of computer post process and atx power supply characteristic and real by the control of fpga
The now test to computer automatic switching.
For achieving the above object, the present invention adopts the following technical scheme that
A kind of computer automatic powering-on/powering-off test device, comprising:
One lpc bus interface module, for being connected with the lpc EBI of tested mainboard, is received and is sent by tested mainboard
Post code data；
One display module, for the display of tested main-board on-off number of times；
One alarm module, for the prompting of tested mainboard boot failure alarm；
One power-off interface module, for being connected with the pson interface of atx power supply, disconnects tested after tested mainboard normal boot-strap
The atx power supply of mainboard, makes tested mainboard shutdown；
One fpga control module, respectively with described lpc bus interface module, display module, alarm module, power-off interface module
Electrical connection；For tested mainboard normal boot-strap infomation detection, post code data is read from lpc bus, by identifying post
Code data judges tested mainboard whether normal boot-strap；The number of times that normal boot-strap number of times counted and will start shooting is shown by display module
Show；Control described power-off interface module to disconnect the atx power supply of tested mainboard after tested mainboard normal boot-strap, so that tested mainboard is closed
Machine；Judge that tested mainboard cannot be reported to the police to control alarm module during normal boot-strap.
Described lpc bus interface module includes a lpc Bussing connector cn1.
Described display module comprises two led charactrons, and described alarm module comprises a buzzer.
Described power-off interface module includes the interface unit that a driver element is electrically connected with described driver element,
This driver element comprises the mosfet field effect transistor of a switch drive for realizing circuit, and described interface unit includes one
Realize and the connection of atx power supply and the two pins adapter cn2 to atx power supply electrifying and the control of power-off.
Described fpga control module include normal boot-strap information detecting unit, start number of times statistics and display control unit,
Alarm control unit and power-off control unit；The input of described normal boot-strap information detecting unit and described lpc EBI
Module connects, and the outfan of described normal boot-strap information detecting unit is counted and aobvious with described alarm control unit, start number of times
Show that control unit is connected, the outfan of described start number of times statistics and display control unit is connected with power-off control unit,
Described alarm control unit is connected with described alarm module, and described power-off control unit is connected with described power-off interface module
Connect, described start number of times statistics and display control unit are connected with described display module.
Apparatus of the present invention may be implemented in and complete computer on/off self-test work in the time the shortest, largely improve
Test job efficiency；Apparatus of the present invention can be counted to switching on and shutting down number of times and be shown, facilitate tester monitoring test into
Journey；Apparatus of the present invention can carry out alarm to boot failure situation, is easy to notify in time tester, and the present invention can be
Most accurately complete the switching on and shutting down self-test work of fixed number of times in time the shortest, in computer testing field, there is important meaning
Justice.
Brief description
Fig. 1 illustrates the principle schematic of the computer automatic powering-on/powering-off test device of the present invention；
Fig. 2 illustrates the structure principle chart of the another computer automatic powering-on/powering-off test device of the present invention.
Specific embodiment
Below, in conjunction with example, the substantive distinguishing features of the present invention and advantage are further described, but the present invention not office
It is limited to listed embodiment.
Referring to shown in Fig. 1-2, a kind of computer automatic powering-on/powering-off test device, comprising:
One lpc bus interface module, for being connected with the lpc EBI of tested mainboard, is received and is sent by tested mainboard
Post code data；
One display module, for the display of tested main-board on-off number of times；
One alarm module, in the prompting of tested mainboard boot failure alarm；
One power-off interface module, for being connected with the pson interface of atx power supply, disconnects tested after tested mainboard normal boot-strap
The atx power supply of mainboard, makes tested mainboard shutdown；
One fpga control module, respectively with described lpc bus interface module, display module, alarm module, power-off interface module
Whether electrical connection, for the reading of post code data in lpc bus, judge tested mainboard by identifying post code data
Normal boot-strap；Normal boot-strap number of times is counted, and number of times of starting shooting is shown by display module；Just normally opened in tested mainboard
After machine, control described power-off interface module to disconnect the atx power supply of tested mainboard, make tested mainboard shutdown；Judging cannot be normal
Send to control alarm module during start and report to the police.
Implement, described lpc bus interface module comprises a lpc Bussing connector cn1, by realize tested based on
Calculate mainboard to be connected with the lpc bus of this computer automatic powering-on/powering-off test device.
Specifically, the lpc Bussing connector cn1 in described lpc bus interface module passes through winding displacement and tested calculating owner
Plate is connected, for receiving the post code data being sent by tested mainboard.
As an embodiment, in the present invention, described display module comprises two led charactrons, to show normal boot-strap
Number of times.Described alarm module comprises a buzzer and its power supply circuits.
As an embodiment, in the present invention, described power-off interface module includes the driver element and being connected
Individual interface unit, this driver element comprises the mosfet field effect transistor of a switch drive for realizing circuit, described interface
Unit includes one and realizes and the connection of atx power supply and the two pins adapter to atx power supply electrifying and the control of power-off
cn2.
As an embodiment, in the present invention, described fpga control module includes normal boot-strap information detecting unit, start
Number of times statistics and display control unit, alarm control unit and power-off control unit；
The input of described normal boot-strap information detecting unit is connected with described lpc bus interface module, described normal boot-strap letter
Outfan and the described alarm control unit of breath detector unit, start number of times counts and display control unit is connected, and described opens
The outfan of machine number of times statistics and display control unit is connected with power-off control unit；
Described alarm control unit is connected with described alarm module, described power-off control unit and described power-off interface module phase
Connect, described start number of times statistics and display control unit are connected with described display module.
Wherein, described normal boot-strap information detecting unit, receives for completing the post code data in lpc bus, sentences
Whether this post code data of breaking is normal boot-strap feature code " ff ", if then to start number of times statistics and display control unit
Output high level signal, boots up number of times and counts and show start number of times by display module, and defeated to power-off control unit
Go out high level signal, control power-off interface module to disconnect atx power supply, if not then to alarm control unit output high level letter
Number, control alarm module to be reported to the police；
Wherein, described start number of times statistics and display control unit, for completing to align what normally opened machine information detector unit was sent
Digital quantity carries out cumulative statistics, and controls this data of numeral method；
Wherein, described alarm control unit comprises the control control circuit being connected with described buzzer, cannot normal boot-strap when
Execution fault alarm function；
Wherein, power-off control unit produces the power-off control letter of a high level after recognizing computer motherboard normal boot-strap
Number, open clocking capability simultaneously, after timing 2s, regenerate a low level signal, for starting the test of switching on and shutting down next time.
Wherein, the normal boot-strap information detecting unit in described fpga control module is by pcb cabling and lpc Bussing connector
Cn1 is connected, and completes the reading of post code data from lpc bus, judges tested mainboard by identifying post code data
Whether normal boot-strap；
Described normal boot-strap information detecting unit is connected with alarm control unit by pcb cabling, and judging cannot normal boot-strap
When to alarm control unit send alarm command.
Start number of times statistics in described fpga control module and display control unit are by pcb cabling and normal boot-strap information
Detector unit is connected, and normal boot-strap number of times is counted, and realizes start number of times is shown on led charactron；
Wherein, described start number of times statistics and display control unit are connected with power-off control unit by pcb cabling, when identifying master
Power-off control unit is given, controlling driver element to send power off command makes mainboard shut down after plate normal boot-strap.
Wherein, the alarm control unit in described fpga control module passes through the buzzer in pcb cabling and alarm module
It is connected, when boot failure situation is detected, control buzzer to send chimes of doom.
Power-off control unit in described fpga control module passes through the mosfet field effect of pcb cabling and power-off interface module
Pipe should be connected, control mosfet field effect transistor to disconnect after normal boot-strap is detected, make atx power outage.
Driver element in described power-off interface module passes through the two pins adapter cn2 in pcb cabling and interface unit
It is connected, two pins adapter cn2 is connected with the pson holding wire in atx power supply by wire, control the height of pson signal
Level.
During test, after this computer automatic powering-on/powering-off test device and atx power supply, tested mainboard are connected, to calculating
Electricity on machine automatic powering-on/powering-off test device, device exports low level to two pins adapter cn2 interface first, controls atx power supply
To electricity on tested mainboard, tested mainboard passes through lpc Bussing connector cn1 and sends post to computer automatic powering-on/powering-off test device
Code, computer automatic powering-on/powering-off test device is identified to code judging, after determining mainboard normal boot-strap, is currently opened
Machine number of times is shown on charactron, exports high level to two pins adapter cn2 interface simultaneously, controls atx power supply to stop to quilt
Survey electricity on mainboard, after computer automatic powering-on/powering-off test device timing 2s, again export low electricity to two pins adapter cn2 interface
Flat, start start test next time, such repetitive cycling, realize repeating automatic on/off test of computer.When computer automatic switching
Test device is identified to code judging, determines mainboard boot failure, then control buzzer to sound the alarm sound, realize test
Failure prompting function.
The above is only the preferred embodiment of the present invention it is noted that ordinary skill people for the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (5)
1. a kind of computer automatic powering-on/powering-off test device is it is characterised in that include:
One lpc bus interface module, for being connected with the lpc EBI of tested mainboard, is received and is sent by tested mainboard
Post code data；
One display module, for the display of tested main-board on-off number of times；
One alarm module, for the prompting of tested mainboard boot failure alarm；
One power-off interface module, for being connected with the pson interface of atx power supply, disconnects tested after tested mainboard normal boot-strap
The atx power supply of mainboard, makes tested mainboard shutdown；
One fpga control module, respectively with described lpc bus interface module, display module, alarm module, power-off interface module
Electrical connection；For tested mainboard normal boot-strap infomation detection, post code data is read from lpc bus, by identifying post
Code data judges tested mainboard whether normal boot-strap；The number of times that normal boot-strap number of times counted and will start shooting is shown by display module
Show；Control described power-off interface module to disconnect the atx power supply of tested mainboard after tested mainboard normal boot-strap, so that tested mainboard is closed
Machine；Judge that tested mainboard cannot be reported to the police to control alarm module during normal boot-strap.
2. according to claim 1 computer automatic powering-on/powering-off test device it is characterised in that described lpc EBI mould
Block includes a lpc Bussing connector cn1.
3. according to claim 1 computer automatic powering-on/powering-off test device it is characterised in that described display module comprises two
Individual led charactron, described alarm module comprises a buzzer.
4. according to claim 1 computer automatic powering-on/powering-off test device it is characterised in that described power-off interface module bag
Include the interface unit that a driver element is electrically connected with described driver element, this driver element comprises one and is used for realizing
The mosfet field effect transistor of the switch drive of circuit, described interface unit include one realize with the connection of atx power supply and
Two pins adapter cn2 to atx power supply electrifying and the control of power-off.
5. according to any one of claim 1-4 computer automatic powering-on/powering-off test device it is characterised in that described fpga control
Molding block includes normal boot-strap information detecting unit, start number of times statistics and display control unit, alarm control unit and power-off
Control unit；The input of described normal boot-strap information detecting unit is connected with described lpc bus interface module, described just normally opened
The outfan of machine information detector unit is connected with described alarm control unit, start number of times statistics and display control unit, institute
State start number of times statistics and the outfan of display control unit is connected with power-off control unit, described alarm control unit and institute
State alarm module to be connected, described power-off control unit is connected with described power-off interface module, described start number of times statistics and
Display control unit is connected with described display module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610677989.9A CN106354592A (en) | 2016-08-17 | 2016-08-17 | Computer automatic startup and shutdown testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610677989.9A CN106354592A (en) | 2016-08-17 | 2016-08-17 | Computer automatic startup and shutdown testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106354592A true CN106354592A (en) | 2017-01-25 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610677989.9A Withdrawn CN106354592A (en) | 2016-08-17 | 2016-08-17 | Computer automatic startup and shutdown testing device |
Country Status (1)
| Country | Link |
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| CN (1) | CN106354592A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109270473A (en) * | 2018-10-17 | 2019-01-25 | 郑州云海信息技术有限公司 | A kind of method and system for examining power supply function |
| CN111999590A (en) * | 2020-10-28 | 2020-11-27 | 湖南兴天电子科技有限公司 | Startup and shutdown test circuit and startup and shutdown test system |
| CN113569228A (en) * | 2021-07-27 | 2021-10-29 | 杭州信雅达科技有限公司 | Detection apparatus for automatic start-up of cipher machine is shut down |
| CN113704033A (en) * | 2021-08-24 | 2021-11-26 | 上海绿联智能科技股份有限公司 | Hardware testing device and method and electronic device |
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| CN101398776A (en) * | 2007-09-28 | 2009-04-01 | 佛山市顺德区顺达电脑厂有限公司 | Automatic powering-on/powering-off test device and method |
| US20090292911A1 (en) * | 2008-05-21 | 2009-11-26 | Yu-Feng Chien | Boot test system and method thereof |
| CN102375770A (en) * | 2010-08-23 | 2012-03-14 | 鸿富锦精密工业（深圳）有限公司 | Computer start-up testing device |
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2016
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| US20090292911A1 (en) * | 2008-05-21 | 2009-11-26 | Yu-Feng Chien | Boot test system and method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109270473A (en) * | 2018-10-17 | 2019-01-25 | 郑州云海信息技术有限公司 | A kind of method and system for examining power supply function |
| CN109270473B (en) * | 2018-10-17 | 2024-03-12 | 郑州云海信息技术有限公司 | Method and system for checking power supply function |
| CN111999590A (en) * | 2020-10-28 | 2020-11-27 | 湖南兴天电子科技有限公司 | Startup and shutdown test circuit and startup and shutdown test system |
| CN113569228A (en) * | 2021-07-27 | 2021-10-29 | 杭州信雅达科技有限公司 | Detection apparatus for automatic start-up of cipher machine is shut down |
| CN113704033A (en) * | 2021-08-24 | 2021-11-26 | 上海绿联智能科技股份有限公司 | Hardware testing device and method and electronic device |
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