CN106160684B - A kind of high linearity variable gain amplifier - Google Patents

Abstract

The invention discloses a high-linearity variable gain amplifier, including a variable gain amplifier for amplifying or attenuating signals. The variable gain amplifier adopts a closed-loop negative feedback structure, and also adopts an exponential gain control for generating a gain control voltage circuit, so that the gain of the variable gain amplifier changes linearly and continuously in dB; the variable gain amplifier is composed of a fully differential operational amplifier, two input PMOS transistors and two feedback PMOS transistors, and the fully differential operational amplifier adopts a two-stage structure. The bias circuit and the common-mode feedback circuit adopt cascode compensation technology to obtain sufficient phase margin and ensure the stability of the feedback loop. The invention realizes the continuous adjustable gain in exponential form while improving the linearity.

Description

A High Linearity Variable Gain Amplifier

technical field

The invention relates to the design of an integrated circuit, in particular to the design of a variable gain amplifier.

Background technique

In a wireless communication system, due to the channel fading phenomenon, the amplitude range of the receiver input signal varies greatly (up to dozens of dB). In order to reduce the bit error rate, the receiver is usually equipped with an automatic gain control circuit (Automatic Gain Control, AGC), and the variable gain amplifier is the main part of the AGC system. At present, the key points and difficulties of variable gain amplifier research are mainly reflected in: wide bandwidth, high gain dynamic range and high linearity. It is difficult for most designers to achieve high linearity in the range of wide bandwidth and high gain, and achieving high linearity may sacrifice bandwidth and gain.

In the prior art, variable gain amplifiers are divided into two types: open loop and closed loop. The open-loop variable gain amplifier can achieve continuously adjustable gain, but the stability is poor, the linearity is low, and the dynamic range of the signal is small; the closed-loop variable gain amplifier uses the form of negative feedback, and its performance is relatively stable. The gain depends on the ratio of the resistors, and the linearity is high, but it is difficult to realize the continuous adjustment of the gain.

Contents of the invention

Aiming at the problems existing in the prior art, the present invention provides a high linearity variable gain amplifier, which can improve the linearity of the amplifier and realize continuous adjustable gain.

In order to solve the above problems, the present invention proposes a high-linearity variable gain amplifier, including a variable gain amplifier for amplifying or attenuating signals. The variable gain amplifier adopts a closed-loop negative feedback structure, and simultaneously generates The exponential gain control circuit of the gain control voltage, so that the gain of the variable gain amplifier is continuously varied in dB; the variable gain amplifier is composed of a fully differential operational amplifier A and a first PMOS transistor M1, a second PMOS transistor M2, a third A PMOS transistor M3 and a fourth PMOS transistor M4 are formed, the first PMOS transistor M1 and the third PMOS transistor M3 are input PMOS transistors, the second PMOS transistor M2 and the fourth PMOS transistor M4 are feedback PMOS transistors; The source end of a PMOS transistor M1 is connected to the first input signal VIP, the drain end of the first PMOS transistor M1 is connected to the positive input end of the fully differential operational amplifier A; the source end of the second PMOS transistor M2 is connected to To the second input signal VIN, the drain end of the second PMOS transistor M2 is connected to the negative input end of the fully differential operational amplifier A; the drain end of the third PMOS transistor M3 is connected to the positive input end of the fully differential operational amplifier A terminal, the source terminal of the third PMOS transistor M3 is connected to the negative output terminal VON of the fully differential operational amplifier A; the drain terminal of the fourth PMOS M4 is connected to the negative input terminal of the fully differential operational amplifier A, and the first The source terminals of the four PMOS transistors M4 are connected to the positive output terminal VOP of the fully differential operational amplifier A; the gates of the first PMOS transistor M1 and the third PMOS transistor M3 are connected to the first gain control voltage V _c1 , and the gates of the first PMOS transistor M1 and the third PMOS transistor M3 are connected to each other. The gates of the second PMOS transistor M2 and the fourth PMOS transistor M4 are connected to the second gain control voltage _Vc2 ; the fully differential operational amplifier A includes a first-stage and a second-stage two-stage structure, a bias circuit, and a common-mode feedback Circuit, wherein, the first stage is a telescopic cascode structure, and the second stage is a common source stage; the first PMOS transistor M1, the third PMOS transistor M3, and the second PMOS transistor M2 in the variable gain amplifier , The fourth PMOS transistor M4 all work in the linear region, wherein the equivalent resistance of the first PMOS transistor M1 and the second PMOS transistor M2 is Rin:

In formula (1), μ _P is the hole mobility of PMOS, the unit is cm ² /Vs; C _ox is the capacitance of the gate oxide layer per unit area, the unit is F/cm ² ; is the width-to-length ratio of the PMOS; V _THP is the threshold voltage of the PMOS, and the unit is V; the equivalent resistance of the third PMOS transistor M3 and the fourth PMOS transistor M4 is Rf:

In formula (2), in formula (1), μ _P is the hole mobility of PMOS, the unit is cm ² /Vs; C _ox is the capacitance of the gate oxide layer per unit area, the unit is F/cm ² ; Be the aspect ratio of PMOS; V _THP is the threshold voltage of PMOS, unit is V; The gain of described variable gain amplifier A is A:

The exponential gain control circuit is used to generate two of the first gain control voltage V _c1 and the second V _c2 gain control voltage, the input of the exponential gain control circuit is an external control signal V _c , wherein the first PMOS The gates of the transistor M1 and the third PMOS transistor M3 are connected to the first gain control voltage _Vc1 , and the gates of the second PMOS transistor M2 and the fourth PMOS transistor M4 are connected to the second gain control voltage _Vc2 ; the exponential gain control The external reference current of the circuit is _I0 ; the exponential gain control circuit includes 17 MOS tubes and two resistors, and the 17 MOS tubes are respectively recorded as MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, and MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20 and MOS tube M21 , the two resistors are resistor R1 and resistor R2; the external control signal Vc is connected to the gates of the MOS transistor M5 and the MOS transistor M6; through the form of a current mirror, the MOS transistor M14 and the MOS transistor M15 transfer the external reference current I ₀ is mirrored to the MOS transistor M11 and the MOS transistor M12, then the current flowing through the MOS transistor M8 is the sum of the currents of the MOS transistor M5 and the MOS transistor M12, and then the leakage current through the MOS transistor M10 Mirror to the MOS transistor M9, and then mirror to the MOS transistor M21; at the same time, the MOS transistor M9 mirrors to obtain the sum of the external reference current _I0 and the current of the MOS transistor M6 to flow through the MOS transistor M7, and then, The mirror image is provided to the MOS transistor M20; one end of the resistor R1 is connected to the drain end of the MOS transistor M20, and the other end of the resistor R1 is grounded to Vss; one end of the resistor R2 is connected to the drain end of the M21, and the other end of the resistor R2 is grounded to Vss, Therefore, the current I _c1 flowing through the resistor R1 and the current I _c2 flowing through the resistor R2 are respectively:

In formula (4), μ _N is the hole mobility of NMOS, the unit is cm ² /Vs; is the width-to-length ratio of NMOS; V _THN is the threshold voltage of NMOS, in V;

In formula (5), The first gain control voltage V _c1 and the second gain control voltage V _c2 are respectively:

V _C1 = I _C1 R ₁ (6)

V _C2 =I _C2 ·R ₂ (7)

Make: the resistance values of resistor R1 and resistor R2 are equal, set K _N =K _P =K, V _THN =|V _THP |=V _TH , V _DD =-V _SS , then the first gain control voltage V _c1 and the second The ratio of the gain control voltage V _c2 is:

Compared with prior art, the beneficial effect of the present invention is:

The variable gain amplifier provided by the invention adopts a closed-loop negative feedback structure, and realizes continuous adjustable gain in exponential form while improving linearity.

Description of drawings

Fig. 1 is the overall architecture diagram of the high linearity variable gain amplifier of the present invention;

Fig. 2 is a structural diagram of an exponential gain control circuit in the present invention;

Fig. 3 is the relation figure of the control signal V _C of variable gain amplifier and input 1dB compression point (P1dB) among the present invention;

Fig. 4 is a graph showing the relationship between the control signal V _C of the variable gain amplifier and the dB value of the gain in the present invention.

Detailed ways

The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the described specific embodiments are only for explaining the present invention, and are not intended to limit the present invention.

As shown in Figure 1, a high-linearity variable gain amplifier of the present invention includes a variable gain amplifier for amplifying or attenuating signals, and is characterized in that: the variable gain amplifier adopts a closed-loop negative feedback structure, and at the same time An exponential gain control circuit that generates a gain control voltage is also used, so that the gain of the variable gain amplifier can change linearly and continuously in dB.

As shown in FIG. 1, the variable gain amplifier is composed of a fully differential operational amplifier A, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, and a fourth PMOS transistor M4. The first PMOS transistor M1 and the third PMOS transistor M3 are input PMOS transistors, the second PMOS transistor M2 and the fourth PMOS transistor M4 are feedback PMOS transistors; the source terminal of the first PMOS transistor M1 is connected to the first input signal VIP, and the The drain end of the first PMOS transistor M1 is connected to the positive input end of the fully differential operational amplifier A; the source end of the second PMOS transistor M2 is connected to the second input signal VIN, and the drain end of the second PMOS transistor M2 Connected to the negative input terminal of the fully differential operational amplifier A; the drain terminal of the third PMOS transistor M3 is connected to the positive input terminal of the fully differential operational amplifier A, and the source terminal of the third PMOS transistor M3 is connected to the fully differential operation The negative output terminal VON of the amplifier A is connected; the drain terminal of the fourth PMOS M4 is connected to the negative input terminal of the fully differential operational amplifier A, and the source terminal of the fourth PMOS transistor M4 is connected to the positive output terminal of the fully differential operational amplifier A VOP is connected; the gates of the first PMOS transistor M1 and the third PMOS transistor M3 are connected with the first gain control voltage V _c1 , and the gates of the second PMOS transistor M2 and the fourth PMOS transistor M4 are connected with the second PMOS transistor M4. The gain control voltage _Vc2 is connected.

The fully differential operational amplifier A includes a first-stage and a second-stage two-stage structure, a bias circuit and a common-mode feedback circuit, wherein the first stage is a telescopic cascode structure, and the second stage is a common-source stage ; A bias circuit and a common-mode feedback circuit are added, and cascode compensation technology is used to obtain sufficient phase margin and ensure the stability of the feedback loop.

The input PMOS in the variable gain amplifier is the first PMOS transistor M1 and the third PMOS transistor M3, and the feedback PMOS is the second PMOS transistor M2 and the fourth PMOS transistor M4 all work in the linear region, wherein the first PMOS transistor The equivalent resistance of M1 and the second PMOS transistor M2 is Rin:

In formula (1), μ _P is the hole mobility of PMOS, the unit is cm ² /Vs; C _ox is the capacitance of the gate oxide layer per unit area, the unit is F/cm ² ; is the width-to-length ratio of the PMOS; V _THP is the threshold voltage of the PMOS, in V;

The equivalent resistance of the third PMOS transistor M3 and the fourth PMOS transistor M4 is Rf:

In formula (2), in formula (1), μ _P is the hole mobility of PMOS, the unit is cm ² /Vs; C _ox is the capacitance of the gate oxide layer per unit area, the unit is F/cm ² ; is the width-to-length ratio of the PMOS; V _THP is the threshold voltage of the PMOS, in V;

The gain of the variable gain amplifier A is A:

As shown in Figure 2, the input of the exponential gain control circuit in the present invention is an external control signal _Vc , and two gain control voltages are generated by the exponential gain control circuit, namely the first gain control voltage V _c1 and the second gain control voltage V _c2 , wherein the gates of the first PMOS transistor M1 and the third PMOS transistor M3 are connected to the first gain control voltage V _c1 , the gates of the second PMOS transistor M2 and the fourth PMOS transistor M4 are connected to the second gain control voltage V c1 The voltage V _c2 is connected. The external reference current of the exponential gain control circuit is _I0 ; the exponential gain control circuit includes 17 MOS transistors and two resistors, wherein the 17 MOS transistors are respectively denoted as MOS transistor M5, MOS transistor M6, and MOS transistor M7 , MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20 and MOS tube M21, the two resistors are resistor R1 and resistor R2; the connection relationship of each device is shown in Figure 2, where MOS tube M5, MOS tube M7, MOS tube M9, MOS tube M11, MOS tube M14 , MOS tube M17, MOS tube M20, MOS tube M21 source terminal connected to the power supply voltage VDD; MOS tube M6, MOS tube M8, MOS tube M10, MOS tube M13, MOS tube M16, MOS tube M18, MOS tube M19 source terminal Ground Vss; the gate of the MOS transistor M5 is connected to the external control signal V _C , the drain of the MOS transistor M6 is connected to the gate drain of the MOS transistor M8 and the drain of the MOS transistor M12; the gate of the MOS transistor M6 is connected to the external control signal V _C , the drain end of the MOS transistor M6 is connected to the gate drain of the MOS transistor M7 and the drain end of the MOS transistor M13; The gate of the MOS transistor M8 is short-circuited to the drain of the MOS transistor M5, the gate of the MOS transistor M10, and the drain of the MOS transistor M12; the gate-drain of the MOS transistor M9 is short-circuited to the drain of the MOS transistor M10 The drain end is connected to the gate of the MOS transistor M21; the gate of the MOS transistor M10 is connected to the gate of the MOS transistor M8; the drain end of the MOS transistor M10 is connected to the drain end of the MOS transistor M9; the gate of the MOS transistor M11 is connected to the gate of the MOS transistor The gate of M14 is connected to the drain of MOS transistor M15, the drain of MOS transistor M11 is connected to the source of MOS transistor M12; the source of MOS transistor M12 is connected to the drain of MOS transistor M11, and the gate of MOS transistor M12 is connected to The gate of the MOS transistor M15 is connected to the gate-drain of the MOS transistor M17; the drain end of the MOS transistor M12 is connected to the drain end of the MOS transistor M5 and the drain end of the MOS transistor M8; the drain end of the MOS transistor M13 is connected to the drain end of the MOS transistor M6 , the drain end of the MOS transistor M7 is connected, the grid of the MOS transistor M13 is connected with the grid of the MOS transistor M16, the grid of the MOS transistor M18, and the grid of the MOS transistor M19; the grid of the MOS transistor M14 is connected with the grid of the MOS transistor M11 The drain end of the MOS transistor M15 is connected to the pole and the drain end of the MOS transistor M15, the drain end of the MOS transistor M14 is connected to the source end of the MOS transistor M15; the source end of the MOS transistor M15 is connected to the drain end of the MOS transistor M14, and the drain end of the MOS transistor M15 is connected to the MOS transistor M11 The gate of the MOS transistor M14, the drain of the MOS transistor M16 The gate of MOS transistor M15 is connected with the gate of MOS transistor M12 and the gate drain of MOS transistor M17; the drain end of MOS transistor M16 is connected with the drain end of MOS transistor M15, and the gate of MOS transistor M16 is connected with the drain of MOS transistor M13 The gate, the gate of the MOS transistor M18, and the gate of the MOS transistor M19 are connected; the gate-drain of the MOS transistor M17 is connected to the gate of the MOS transistor M12, the gate of the MOS transistor M15, and the drain of the MOS transistor M18; The drain end of the tube M18 is connected to the drain end of the MOS tube M17, the gate of the MOS tube M18 is connected to the gate of the MOS tube M13, the gate of the MOS tube M16, and the gate of the MOS tube M19; the gate drain of the MOS tube M19 is short connected to the external current reference source; the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M7, the drain of the MOS transistor M20 is connected to one end of the resistor R1, and connected to the output control voltage V _c1 ; the gate of the MOS transistor M21 The pole is connected to the gate of the MOS transistor M9, the drain of the MOS transistor M21 is connected to one end of the resistor R2, and connected to the output control voltage V _c2 ; the other end of the resistor R1 and the resistor R2 are grounded to Vss. The external control signal _Vc of the present invention is connected to the gates of the MOS transistor M5 and the MOS transistor M6; through the form of a current mirror, the MOS transistor M14 and the MOS transistor M15 mirror the external reference current _I0 to the MOS tube M11 and MOS tube M12, the current flowing through the MOS tube M8 is the sum of the currents of the MOS tube M5 and the MOS tube M12, and then the leakage current of the MOS tube M10 is mirrored to the MOS tube M9 , and then, the mirror image is given to the MOS transistor M21; at the same time, the MOS transistor M9 is mirrored to obtain the sum of the external reference current _I0 and the current of the MOS transistor M6 to flow through the MOS transistor M7, and then, the mirror image is given to the MOS transistor M20 ; Thus, the current _Ic1 flowing through the resistor R1 and the current _Ic2 flowing through the resistor R2 are:

In formula (4), μ _N is the hole mobility of NMOS, the unit is cm ² /Vs; is the width-to-length ratio of NMOS; V _THN is the threshold voltage of NMOS, in V;

In formula (5), The first gain control voltage V _c1 and the second gain control voltage V _c2 are respectively:

V _C1 = I _C1 R ₁ (6)

V _C2 =I _C2 ·R ₂ (7)

Make: the resistance values of resistor R1 and resistor R2 are equal, set K _N =K _P =K, V _THN =|V _THP |=V _TH , V _DD =-V _SS , then the first gain control voltage V _c1 and the second The ratio of the gain control voltage V _c2 is:

The formula (8) is an approximate expression of the exponential function, so the variable gain amplifier provided by the present invention can realize continuous adjustment of the gain in exponential form.

Fig. 3 shows the relationship between the external control signal V _C and the input 1dB compression point (P1dB) of the high linearity variable gain amplifier of the present invention, it can be seen that the variable gain amplifier achieves higher linearity.

Fig. 4 has shown the relationship figure between the external control signal V _C of the high linearity variable gain amplifier of the present invention and the dB value of gain, it can be seen that this variable gain amplifier has realized good dB linear relationship, and obtained 22dB continuous gain range.

Although the present invention has been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, rather than restrictive. Under the enlightenment of the present invention, many modifications can be made without departing from the gist of the present invention, and these all belong to the protection of the present invention.

Claims (1)

1. A high-linearity variable gain amplifier, comprising a variable gain amplifier for amplifying or attenuating signals, characterized in that: said variable gain amplifier adopts a closed-loop negative feedback structure, and simultaneously generates a gain control voltage The exponential gain control circuit realizes that the gain of the variable gain amplifier changes linearly and continuously in dB; The variable gain amplifier is composed of a fully differential operational amplifier A and a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3 and a fourth PMOS transistor M4, and the first PMOS transistor M1 and the third PMOS transistor M3 is an input PMOS transistor, the second PMOS transistor M2 and the fourth PMOS transistor M4 are feedback PMOS transistors; the source end of the first PMOS transistor M1 is connected to the first input signal VIP, and the source end of the first PMOS transistor M1 The drain terminal is connected to the positive input terminal of the fully differential operational amplifier A; the source terminal of the second PMOS transistor M2 is connected to the second input signal VIN, and the drain terminal of the second PMOS transistor M2 is connected to the fully differential operational amplifier A The negative input terminal of the amplifier A is connected; the drain terminal of the third PMOS transistor M3 is connected with the positive input terminal of the fully differential operational amplifier A, and the source terminal of the third PMOS transistor M3 is connected with the negative output terminal of the fully differential operational amplifier A VON is connected; the drain end of the fourth PMOS M4 is connected to the negative input end of the fully differential operational amplifier A, and the source end of the fourth PMOS transistor M4 is connected to the positive output end VOP of the fully differential operational amplifier A; The gates of the first PMOS transistor M1 and the third PMOS transistor M3 are connected to the first gain control voltage V _C1 , and the gates of the second PMOS transistor M2 and the fourth PMOS transistor M4 are connected to the second gain control voltage V _C2 ; The fully differential operational amplifier A includes a first-stage and a second-stage two-stage structure, a bias circuit and a common-mode feedback circuit, wherein the first stage is a telescopic cascode structure, and the second stage is a common-source stage ; The first PMOS transistor M1, the third PMOS transistor M3, the second PMOS transistor M2, and the fourth PMOS transistor M4 in the variable gain amplifier all work in the linear region, wherein the first PMOS transistor M1 and the second PMOS transistor M2 The equivalent resistance is Rin: In formula (1), μ _P is the hole mobility of PMOS, the unit is cm ² /Vs; C _ox is the capacitance of the gate oxide layer per unit area, the unit is F/cm ² ; is the width-to-length ratio of the PMOS; V _THP is the threshold voltage of the PMOS, in V; The equivalent resistance of the third PMOS transistor M3 and the fourth PMOS transistor M4 is Rf: In formula (2), μ _P is the hole mobility of PMOS, the unit is cm ² /Vs; C _ox is the capacitance of the gate oxide layer per unit area, the unit is F/cm ² ; is the width-to-length ratio of the PMOS; V _THP is the threshold voltage of the PMOS, in V; The gain of the variable gain amplifier is A: The exponential gain control circuit is used to generate two of the first gain control voltage V _C1 and the second gain control voltage V _C2 , the input of the exponential gain control circuit is an external control signal V _C , wherein the first PMOS The gates of the transistor M1 and the third PMOS transistor M3 are connected to the first gain control voltage V _C1 , and the gates of the second PMOS transistor M2 and the fourth PMOS transistor M4 are connected to the second gain control voltage V _C2 ; the exponential gain control The external reference current of the circuit is _I0 ; the exponential gain control circuit includes 17 MOS tubes and two resistors, and the 17 MOS tubes are respectively recorded as MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, and MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20 and MOS tube M21, The two resistors are resistor R1 and resistor R2; the external control signal V _C is connected to the gates of the MOS transistor M5 and the MOS transistor M6; through the form of a current mirror, the MOS transistor M14 and the MOS transistor M15 transfer the external reference current I ₀ is mirrored to the MOS transistor M11 and the MOS transistor M12, then the current flowing through the MOS transistor M8 is the sum of the currents of the MOS transistor M5 and the MOS transistor M12, and then the leakage current through the MOS transistor M10 Mirror to the MOS transistor M9, and then mirror to the MOS transistor M21; at the same time, the MOS transistor M9 mirrors to obtain the sum of the external reference current _I0 and the current of the MOS transistor M6 to flow through the MOS transistor M7, and then, The mirror image is provided to the MOS transistor M20; one end of the resistor R1 is connected to the drain end of the MOS transistor M20, and the other end of the resistor R1 is grounded to Vss; one end of the resistor R2 is connected to the drain end of the M21, and the other end of the resistor R2 is grounded to Vss, Therefore, the current I _C1 flowing through the resistor R1 and the current I _C2 flowing through the resistor R2 are respectively: In formula (4), μ _N is the hole mobility of NMOS, the unit is cm ² /Vs; is the width-to-length ratio of NMOS; V _THN is the threshold voltage of NMOS, in V; In formula (5), The first gain control voltage V _C1 and the second gain control voltage V _C2 are respectively: V _C1 = I _C1 R ₁ (6) V _C2 =I _C2 ·R ₂ (7) Make: the resistance values of resistor R1 and resistor R2 are equal, set K _N =K _P =K, V _THN =|V _THP |=V _TH , V _DD =-V _SS , then the first gain control voltage V _C1 and the second The ratio of the gain control voltage V _C2 is: