CN106158641B - FinFET device and preparation method thereof - Google Patents
FinFET device and preparation method thereof Download PDFInfo
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- CN106158641B CN106158641B CN201510158698.4A CN201510158698A CN106158641B CN 106158641 B CN106158641 B CN 106158641B CN 201510158698 A CN201510158698 A CN 201510158698A CN 106158641 B CN106158641 B CN 106158641B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 238000002347 injection Methods 0.000 claims abstract description 18
- 239000007924 injection Substances 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims description 141
- 238000000034 method Methods 0.000 claims description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 239000003989 dielectric material Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 7
- 239000007790 solid phase Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 4
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 24
- 238000010586 diagram Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
This application provides a kind of finFET devices and preparation method thereof.The production method includes: that fin and oxide layer are arranged on substrate, doped with the first foreign ion and is formed successively close to the first lightly doped district, heavy doping well region and the second lightly doped district of substrate setting in fin；Gate structure and side wall are set on fin；Using gate structure and side wall as exposure mask, fin is etched to form recessed portion on fin, the top surface of recessed portion is located in heavy doping well region；Second foreign ion injection is carried out to recessed portion and forms ion implanted region, the second foreign ion is the transoid ion of the first foreign ion；And source electrode and drain electrode is set in ion implanted region.Above-mentioned production method will not influence original effect for improving short-channel effect, and effectively reduce source electrode caused by the presence of heavy doping, leakage current between drain electrode and substrate.
Description
Technical field
This application involves technical field of manufacturing semiconductors, in particular to a kind of finFET device and preparation method thereof.
Background technique
Existing complementary metal oxide semiconductor (CMOS) transistor be it is two-dimensional, with the continuous contracting of channel dimensions
Small, the problem related with short-channel effect is increasingly difficult to overcome.Therefore, chip manufacturer is developing with more high effect
The transistor of three-dimensional, such as fin formula field effect transistor (FinFET), can better adapt to device size by than
The requirement that example reduces.
The existing method for forming FinFET generally includes following processing step: the formation of fin (Fin) → well region injection →
Formation → side wall formation of grid → expansion area injection → side wall formation → source/drain region selective growth → source/drain region note
Enter → formation of formation → contact hole and other front end processes of self-aligned silicide.In above-mentioned processing step, fin (Fin)
Formation have two methods.A kind of method is: being initially formed a silicon oxide layer on silicon substrate to form silicon-on-insulator (SOI)
Structure, then one silicon layer of the upper surface of silicon structure epitaxial growth on insulator, etches silicon layer to form fin；The disadvantages of this method
Be: manufacturing cost is very high, while the thermal diffusivity of silicon oxide layer is poor compared with silicon substrate, and will lead to the heat in channel cannot effectively dissipate
It loses, causes temperature to increase, influence mobility, have negative effect to device performance.
Another method is: fin is directly etched on silicon substrate, then on silicon substrate deposition oxide fin is isolated.
After the fins are formed, using process shown in FIG. 1 formed finFET device, wherein on silicon substrate formed fin after, to fin into
The injection of row well region, forms the first lightly doped district 111 ', heavy doping well region and the second lightly doped district 131 ' shown in Fig. 2 on fin,
To control the generation of short-channel effect, improves gate structure 103 ' to the control ability of channel, reduce grid voltage pinch off
The difficulty of (pinch off) channel avoids the generation of sub-threshold leakage (Subthreshold leakage) phenomenon；Then, exist
Gate structure 103 ' is set on fin surface shown in Fig. 2, which includes hard exposure mask 133 ' shown in Fig. 3, grid 132 '
With gate oxide 131 '；The two sides of gate structure 103 ' shown in Fig. 3 form side wall 104 ' shown in Fig. 4；With shown in Fig. 4
Gate structure and side wall are exposure mask, etch fin, form the device with cross-section structure shown in Fig. 5；Exposed fin shown in Fig. 5
Upper epitaxial growth forms source area 106 ' shown in fig. 6 and drain region 107 '；It is to cover with gate structure 103 ' and side wall 104 '
Film carries out ion implanting to source area 106 ' shown in fig. 6 and drain region 107 ', forms source electrode 108 ' shown in Fig. 7 and drain electrode
109’。
As seen from Figure 7, well region injection is formed by the presence of heavy doping well region, leads to source electrode, drain electrode and silicon substrate
Between leakage current increase, which is the main reason to form device open-circuit current.
Summary of the invention
The application is intended to provide a kind of finFET device and preparation method thereof, to solve heavy doping well region in the prior art
There are problems that causing the leakage current between source electrode, drain electrode and silicon substrate to increase.
To achieve the goals above, according to the one aspect of the application, a kind of production method of finFET device is provided,
The production method includes: that fin and oxide layer are arranged on substrate, is successively leaned in fin doped with the first foreign ion and being formed
The first lightly doped district, heavy doping well region and the second lightly doped district of nearly substrate setting；Gate structure and side wall are set on fin；
Using gate structure and side wall as exposure mask, fin is etched to form recessed portion on fin, the top surface of recessed portion is located at heavy doping trap
Qu Zhong；Second foreign ion injection is carried out to recessed portion and forms ion implanted region, the second foreign ion is the first foreign ion
Transoid ion；And source electrode and drain electrode is set in ion implanted region.
Further, the concentration of the first foreign ion is n in the first lightly doped district and the second lightly doped district1, heavy doping trap
The concentration of the first foreign ion is n in area2, and n1< n2, the concentration of the second foreign ion is n in ion implanted region3, and n3<
n2, wherein n2With n3Difference and n1Ratio be 0.9:1~1:1.1.
Further, n1For 1E13~1E14atoms/cm3, n2For 1E15~1E17atoms/cm3, n3For 5E14~
1E16atoms/cm3。
Further, in the step of the second foreign ion injection, Implantation Energy is 40~80KeV, implantation dosage 1E12
~1E14atoms/cm2。
Further, the first foreign ion is P-type ion, and the second foreign ion is N-type ion；Or first foreign ion
For N-type ion, the second foreign ion is P-type ion, and N-type ion is P or As, P-type ion B.
Further, be arranged source/drain process include: ion implanted region carry out epitaxial growth, formed source area and
Drain region；Ion implanting is carried out to source area and drain region and forms source electrode and drain electrode.
Further, epitaxial growth is that solid-phase epitaxial growth or laser epitaxial are grown.
Further, the setting up procedure of gate structure includes: that oxide is arranged on exposed fin and oxide layer；In oxygen
Deposit polycrystalline silicon in compound；Deposition of dielectric materials on the polysilicon, dielectric material are silica, hafnium oxide, aluminium oxide, silicon nitride
Or silicon oxynitride；It is sequentially etched dielectric material, polysilicon and oxide, forms gate structure, wherein shape after dielectric material etching
At the gate dielectric layer of gate structure, the grid of gate structure is formed after etching polysilicon, forms gate structure after oxide etching
Gate oxide.
Further, gate oxide is arranged using chemical vapour deposition technique, physical vaporous deposition or thermal oxidation method.
Further, the setting up procedure of side wall includes: the deposition side wall material in gate structure, exposed fin and oxide layer
Material, spacer material are composite material, silicon nitride or the silica of silicon nitride and silica；Spacer material is performed etching to form side
Wall.
Present invention also provides a kind of finFET device, which includes: substrate, the fin of setting on substrate
And oxide layer, it is provided in fin and successively close to substrate and adulterates the first lightly doped district of the first foreign ion, heavy doping well region
With the second lightly doped district, fin has center knob and peripheral recesses portion, and the surface of the separate substrate in peripheral recesses portion is located at
In heavy doping well region, finFET device further includes the gate structure and side wall on center knob, and is located at peripheral recessed
The source electrode and drain electrode of concave portion, doped with the second foreign ion, the second foreign ion in the heavy doping well region in peripheral recesses portion
For the transoid ion of the first foreign ion.
Using the technical solution of the application, the application passes through etching fin to form recessed portion on fin, and to recess
Portion carries out the second foreign ion injection and forms ion implanted region, and the second foreign ion is the transoid ion of the first foreign ion, from
And reduce the effective concentration of the first foreign ion in the heavy doping well region below source electrode and drain electrode, and it is located at grid knot
The first foreign ion still maintains high effective concentration doping in heavy doping well region below structure, therefore, will not influence original change
The effect of kind short-channel effect, and effectively reduce source electrode caused by the presence of heavy doping, leakage current between drain electrode and substrate.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 shows the production process schematic diagram of finFET device in the prior art；
Fig. 2 to Fig. 7 shows the device profile structural schematic diagram for implementing to obtain after each process shown in Fig. 1, wherein
The schematic diagram of the section structure after forming fin and oxide layer on silicon substrate, after carrying out well region injection；
Fig. 3 shows the schematic diagram of the section structure being arranged after gate structure on fin surface shown in Fig. 2, and Fig. 3 is along Fig. 2
Line A-A the schematic diagram of the section structure；
The two sides that Fig. 4 shows gate structure shown in Fig. 3 form the schematic diagram of the section structure after side wall；
Fig. 5 shows the schematic diagram of the section structure using gate structure shown in Fig. 4 and side wall as exposure mask, after etching fin；
Fig. 6 shows epitaxial growth on exposed fin shown in Fig. 5, and the cross-section structure after forming source area and drain region shows
It is intended to；
Fig. 7 is shown using gate structure shown in fig. 6 and side wall as exposure mask, carries out ion note to source area and drain region
Enter, the schematic diagram of the section structure after forming source electrode and drain electrode；
Fig. 8 shows the production process schematic diagram of finFET device provided by the present application；
Fig. 9 to Figure 15 shows the device profile structural schematic diagram for implementing to obtain after each process shown in Fig. 8, wherein
Fig. 9, which is shown, is arranged fin and oxide layer on substrate, and carries out the cross-section structure after well region injection to fin and illustrate
Figure；
Figure 10 shows the schematic diagram of the section structure being arranged after gate structure on fin shown in Fig. 9, and Figure 11 is Figure 10's
Along the schematic diagram of the section structure of line A-A；
The side that Figure 11 shows gate structure forms the schematic diagram of the section structure after side wall；
Figure 12 is shown using gate structure shown in Figure 11 and side wall as exposure mask, etches fin to form recess on fin
The schematic diagram of the section structure behind portion；
Figure 13, which is shown, carries out the section after the second foreign ion injection forms ion implanted region to the recessed portion in Figure 12
Structural schematic diagram；
Figure 14 shows ion implanted region shown in Figure 13 and carries out being epitaxially-formed the section behind source area and drain region
Structural schematic diagram；And
Figure 15 is shown to cuing open after source area shown in Figure 14 and drain region progress ion implanting formation source electrode and drain electrode
Face structural schematic diagram.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
For ease of description, spatially relative term can be used herein, as " ... on ", " ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, being described as if the device in attached drawing is squeezed " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also be positioned with other different modes and (is rotated by 90 ° or in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As background technique is introduced, the foreign ion in the fin of existing finFET device between the source and drain
Concentration is larger, and the leakage current between source electrode, drain electrode and silicon substrate is easy to cause to increase, and the leakage current is to form device open circuit electricity
The main reason of stream, in order to avoid the generation of above-mentioned leakage current, present applicant proposes a kind of finFET devices and preparation method thereof.
As shown in figure 8, the production method of the finFET device includes: that fin 101 and oxide layer are arranged on substrate 100
102, doped with the first foreign ion and the first lightly doped district 111 being successively arranged close to substrate 100, again is formed in fin 101
Doped well region 121 and the second lightly doped district 131；Gate structure 103 and side wall 104 are set on fin 101；With gate structure
103 and side wall 104 be mask etching fin 101 to form recessed portion on fin 101, the top surface of recessed portion is located at heavy doping trap
In area 121；Second foreign ion injection is carried out to recessed portion and forms ion implanted region 105, the second foreign ion is the first impurity
The transoid ion of ion；And source electrode 108 and drain electrode 109 are set in ion implanted region 105.
Above-mentioned production method forms recessed portion by etching fin on fin 101, and it is miscellaneous to carry out second to recessed portion
Matter ion implanting forms ion implanted region 105, and the second foreign ion is the transoid ion of the first foreign ion, to reduce position
The effective concentration of the first foreign ion in the heavy doping well region 105 of 109 lower section of source electrode 108 and drain electrode, and it is located at grid knot
Therefore the doping that the first foreign ion still maintains high effective concentration in the heavy doping well region 121 of 103 lower section of structure will not influence
It is original improve short-channel effect effect, and effectively reduce source electrode caused by the presence of heavy doping, drain electrode and substrate it
Between leakage current.
It should be appreciated by the person skilled in the art that above-mentioned transoid ion refers to the ion for being capable of providing hole and can mention
For the ion of free electron, the application according to the structure design characteristic of common finFET device, preferably above-mentioned first impurity from
Son is P-type ion, and the second foreign ion is N-type ion；Or first foreign ion be N-type ion, the second foreign ion be p-type
Ion.Preferably, N-type ion is P or As, and the P-type ion is B.
Now, the illustrative embodiments according to the application are more fully described with reference to the accompanying drawings.However, these are exemplary
Embodiment can be implemented by many different forms, and should not be construed to be limited solely to embodiment party set forth herein
Formula.It should be understood that it is thoroughly and complete to these embodiments are provided so that disclosure herein, and these are shown
The design of example property embodiment is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer
With the thickness in region, and make that identical device is presented with like reference characters, thus description of them will be omitted.
Firstly, fin 101 and oxide layer 102 are arranged on substrate 100, and well region is carried out to fin 101 and is infused in fin
The first foreign ion is adulterated in 101 and forms successively the first lightly doped district 111 close to substrate setting, 121 and of heavy doping well region
Second lightly doped district 131 forms the device with cross-section structure shown in Fig. 9.
Above-mentioned substrate 100 can be any semiconductor material commonly used in the art, such as IV race's semiconductor, such as silicon or
- V compound semiconductor of germanium or III race, such as GaAs, indium phosphide, gallium nitride or silicon carbide, the application preferably uses body
Silicon is as substrate 100.
Above-mentioned substrate 100 is performed etching to form fin 101, then on substrate 100 after etching deposition oxide with
Fin 101 is isolated；Then oxide is performed etching, keeps the partial sidewall of fin 101 exposed, form oxide layer 102；To fin
101 carry out well region injection, form the first lightly doped district 111, heavy doping well region 121 and the second lightly doped district 131, above-mentioned each doping
The formation in area can be same as the prior art, is realized by adjusting angle, energy and the dosage of ion implanting, no longer superfluous herein
It states.
After forming above-mentioned first lightly doped district 111, heavy doping well region 121 and the second lightly doped district 131 on fin 101,
Gate structure 103 shown in Fig. 10 is set on fin 101 shown in Fig. 10.Wherein, Figure 10 is the section along line A-A of Fig. 9
Structural schematic diagram.The forming process of the gate structure 103 can according to formed gate structure 103 type it is different and become
Change, will illustrate the forming process of gate structure 103 respectively below.
When the grid 132 of gate structure 103 is polysilicon gate, the forming process of the gate structure 103 includes: naked
Oxide is set on the fin 101 and oxide layer 102 of dew；Deposit polycrystalline silicon on oxides；Deposit dielectric material on the polysilicon
Material, is arranged photoresist, and exposure development is graphical on the dielectric material, is sequentially etched dielectric material, more by exposure mask of photoresist
Crystal silicon and oxide form gate dielectric layer 133, grid 132 and the gate oxide 131 of gate structure 103.Wherein above-mentioned formation grid
The oxide of oxide layer 131 is arranged using chemical vapour deposition technique, physical vaporous deposition or thermal oxidation method, above-mentioned polycrystalline
Silicon and dielectric material can be used chemical vapour deposition technique or physical vaporous deposition deposition, above-mentioned dielectric material be silica,
Hafnium oxide, alumina layer, silicon nitride or silicon oxynitride.
When the grid 131 of gate structure 103 is dummy grid, the forming process of the gate structure 103 includes: exposed
Polysilicon is set in fin 101 and oxide layer 102；Photoresist is set on the polysilicon, and exposure development is graphical, with photoresist
Dummy grid is formed for mask etching polysilicon.
After forming gate structure 103 shown in Fig. 10, side wall shown in Figure 11 is formed in the side of gate structure 103
104, the forming process of preferably above-mentioned side wall 104 includes: to sink in gate structure 103, exposed fin 101 and oxide layer 102
Product spacer material；Spacer material is performed etching to form side wall 104.Above-mentioned spacer material is preferably answering for silicon nitride and silica
Condensation material, silicon nitride or silica, and above-mentioned side wall material is preferably deposited using chemical vapour deposition technique or physical vaporous deposition
Material.
Complete side wall 104 production after, using gate structure shown in Figure 11 and side wall as exposure mask, etch fin 101 with
Recessed portion shown in Figure 12 is formed on fin 101, the top surface of the recessed portion as shown in figure 12 is located in heavy doping well region 121.
After forming recessed portion, in Figure 12 recessed portion carry out the second foreign ion injection formed shown in Figure 13 from
Sub- injection region 105, the second foreign ion are the transoid ion of the first foreign ion.As described above, second injected is miscellaneous
Matter ion is the transoid ion of the first foreign ion, to reduce the in the heavy doping well region below source electrode and drain electrode
The effective concentration of one foreign ion, and be located at the first foreign ion in the heavy doping well region 121 below gate structure and still maintain
Therefore high effective concentration doping will not influence original effect for improving short-channel effect, and effectively reduce heavy doping
There are leakage currents between caused source electrode, drain electrode and substrate.
Those skilled in the art, can be according to being formed by setting for finFET device when carrying out ion implanting to recessed portion
Meter requires to select the implementation condition of corresponding ion implanting.It is preferred that in above-mentioned first lightly doped district 111 and the second lightly doped district 131
The concentration of first foreign ion is n1, the concentration of the first foreign ion is n in heavy doping well region 1212, and n1< n2, ion implanting
The concentration of second foreign ion is n in area 1053, and n3< n2, wherein n2With n3Difference and n1Ratio be 0.9:1~1:
1.1.For the performance of finFET device commonly used in the art, preferably above-mentioned n1For 1E13~1E14atoms/cm3, n2For 1E15
~1E17atoms/cm3, n3For 5E14~1E16atoms/cm3。
It is formed after above-mentioned ion implanted region 105, the ion implanted region 105 shown in Figure 13 carries out epitaxial growth, is formed
Source area 106 and drain region 107 shown in Figure 14.It is brilliant using the surface for the source area 106 and drain region 107 being epitaxially-formed
Trellis state is complete, internal and gap is not present between ion implanted region 105, effectively improves the property of finFET device
Energy；And the height for being formed by source area 106 and drain region 107 can be controlled, meet the finFET of different performance design requirement
The demand of device.
The preferred solid-phase epitaxial growth of above-mentioned epitaxial growth or laser epitaxial growth.Wherein, in solid-phase epitaxial growth, high temperature is moved back
The temperature of fire is 500~900 DEG C, and the time is 0.5~30h.In annealing process, ion implanted region 105 and exposed first
Growth source of the side wall of shape structure 11 as solid-phase epitaxial growth, using the surface of ion implanted region 105 as seed crystal, from top to bottom
Growth, to form above-mentioned source area 106 and drain region 107.
In addition, being to be carried out with laser to ion implanted region 105 well known to a person skilled in the art laser epitaxial growth technique
Heating, makes semiconductor material upward epitaxial growth since the surface of ion implanted region 105, in order to obtain good lattice-like
In the growth of state, preferably above-mentioned laser epitaxial, epitaxial growth temperature is 300~1400 DEG C, and the time is 1min~10h.Laser epitaxial
The epitaxial growth speed of growth method is faster than the speed of growth of solid phase epitaxial growth, is conducive to the quantization production of device.
After forming above-mentioned source area 106 and drain region 107, to source area 106 shown in Figure 14 and drain region 107 into
Row ion implanting forms source electrode 108 shown in figure 15 and drain electrode 109.Above-mentioned ion implantation process forms finFET using this field
The common process of device source-drain electrode is implemented, and details are not described herein.
Gate structure 103 is described above, if the grid in above-mentioned gate structure 103 is dummy grid,
After the production for completing source electrode 108 and drain electrode 109, the production method of the application further include: be arranged in dummy grid and side wall periphery
Protective layer；Etching removal dummy grid forms opening；Deposited oxide zirconium or hafnium oxide in being open, form gate dielectric layer；It is situated between in grid
Copper, tungsten, aluminium, titanium, titanium nitride, nitridation thallium or tantalum nitride are deposited on matter layer, form grid；And removal protective layer.The above process
It can carry out, therefore be not shown in the figure with reference to the prior art.
Present invention also provides a kind of finFET devices, can refer to Figure 15, which includes: substrate 100, setting
Fin 101 and oxide layer 102 on substrate 100 are provided in fin 101 successively close to substrate 100 and the first impurity of doping
The first lightly doped district 111, heavy doping well region 121 and the second lightly doped district 131 of ion, fin 101 have center knob and
The surface in peripheral recesses portion, the separate substrate 100 in peripheral recesses portion is located in heavy doping well region 121, which also wraps
The gate structure 103 (mark that can refer to Figure 11) and side wall 104 being located on center knob are included, and is located at peripheral recesses portion
Source electrode 108 and drain electrode 109, doped with the second foreign ion, the second impurity in the heavy doping well region 121 in peripheral recesses portion
Ion is the transoid ion of the first foreign ion.
Be located at peripheral recesses portion heavy doping well region 121 in simultaneously adulterate promising transoid ion the second foreign ion and
First foreign ion, thus reduce positioned at source electrode 108 and drain electrode 109 lower section heavy doping well region 105 in the first impurity from
The effective concentration of son, and be located at the first foreign ion in the heavy doping well region 105 of 103 lower section of gate structure and still maintain high effectively
Therefore the doping of concentration will not influence original effect for improving short-channel effect, and effectively reduce the presence of heavy doping
Leakage current between caused source electrode, drain electrode and substrate.
It can be seen from the above description that the application the above embodiments realize following technical effect:
1), the application forms recessed portion by etching fin on fin, and carries out the second foreign ion to recessed portion
Injection forms ion implanted region, and the second foreign ion is the transoid ion of the first foreign ion, thus reduce positioned at source electrode and
The ion concentration in heavy doping well region below draining, and the heavy doping well region being located at below gate structure still maintains high concentration
Therefore doping will not influence original effect for improving short-channel effect, and effectively reduce caused by the presence of heavy doping
Leakage current between source electrode, drain electrode and substrate；
2), the production method relative to current production finFET device increases only a step process, and will not be to existing
Technique adversely affects, therefore suitable for the popularization and application prior art.
3) finFET device of the application, be located at peripheral recesses portion heavy doping well region in simultaneously adulterate promising transoid from
The second foreign ion and the first foreign ion of son, to reduce the in the heavy doping well region below source electrode and drain electrode
The effective concentration of one foreign ion, and be located at the first foreign ion in the heavy doping well region below gate structure and still maintain height and have
The doping of concentration is imitated, therefore, will not influence original effect for improving short-channel effect, and effectively reduce depositing for heavy doping
The leakage current between caused source electrode, drain electrode and substrate.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (11)
1. a kind of production method of finFET device, which is characterized in that the production method includes:
Fin and oxide layer be set on substrate, doped with the first foreign ion and is formed successively close to the lining in the fin
The first lightly doped district, heavy doping well region and the second lightly doped district of bottom setting；
Gate structure and side wall are set on the fin；
Using the gate structure and side wall as exposure mask, the fin is etched to form recessed portion, the recess on the fin
The top surface in portion is located in the heavy doping well region；
Second foreign ion injection is carried out to the recessed portion and forms ion implanted region, second foreign ion is described first
The transoid ion of foreign ion；And
In the ion implanted region, source electrode and drain electrode is set.
2. manufacturing method according to claim 1, which is characterized in that in first lightly doped district and the second lightly doped district
The concentration of first foreign ion is n1, the concentration of the first foreign ion described in the heavy doping well region is n2, and n1< n2, institute
The concentration for stating the second foreign ion in ion implanted region is n3, and n3< n2, wherein n2With n3Difference and n1Ratio be 0.9:
1~1:1.1.
3. production method according to claim 2, which is characterized in that the n1For 1E13~1E14atoms/cm3, described
n2For 1E15~1E17atoms/cm3, the n3For 5E14~1E16atoms/cm3。
4. manufacturing method according to claim 1, which is characterized in that in the step of second foreign ion injection, note
Entering energy is 40~80KeV, and implantation dosage is 1E12~1E14atoms/cm2。
5. production method according to any one of claim 1 to 4, which is characterized in that first foreign ion is p-type
Ion, second foreign ion are N-type ion；Or first foreign ion be N-type ion, the second foreign ion be p-type from
Son, the N-type ion are P or As, and the P-type ion is B.
6. manufacturing method according to claim 1, which is characterized in that it is described setting source/drain process include:
Epitaxial growth is carried out in the ion implanted region, forms source area and drain region；
Ion implanting is carried out to the source area and the drain region and forms source electrode and drain electrode.
7. production method according to claim 6, which is characterized in that the epitaxial growth is solid-phase epitaxial growth or laser
Epitaxial growth.
8. manufacturing method according to claim 1, which is characterized in that the setting up procedure of the gate structure includes:
Oxide is set on the exposed fin and the oxide layer；
The deposit polycrystalline silicon on the oxide；
The deposition of dielectric materials on the polysilicon, the dielectric material are silica, hafnium oxide, aluminium oxide, silicon nitride or nitrogen
Silica；
It is sequentially etched the dielectric material, polysilicon and oxide, forms the gate structure, wherein the dielectric material is carved
The gate dielectric layer of the gate structure is formed after erosion, and the grid of the gate structure, the oxygen are formed after the etching polysilicon
The gate oxide of the gate structure is formed after compound etching.
9. production method according to claim 8, which is characterized in that the gate oxide using chemical vapour deposition technique,
Physical vaporous deposition or thermal oxidation method are arranged.
10. manufacturing method according to claim 1, which is characterized in that the setting up procedure of the side wall includes:
Spacer material is deposited in the gate structure, the exposed fin and the oxide layer, the spacer material is nitrogen
The composite material of SiClx and silica, silicon nitride or silica；
The spacer material is performed etching to form the side wall.
11. a kind of finFET device, the finFET device includes: substrate, setting fin over the substrate and oxide layer,
Be provided in the fin successively close to the substrate and adulterate the first lightly doped district of the first foreign ion, heavy doping well region and
Second lightly doped district, the fin have center knob and peripheral recesses portion, the separate substrate in the peripheral recesses portion
Surface be located in the heavy doping well region, the finFET device further includes the gate structure on the center knob
And side wall, and the source electrode and drain electrode positioned at the peripheral recesses portion, which is characterized in that described in the peripheral recesses portion
Doped with the second foreign ion in heavy doping well region, second foreign ion is the transoid ion of first foreign ion.
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| CN108573869B (en) * | 2017-03-07 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and forming method thereof |
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| CN102074476A (en) * | 2009-11-20 | 2011-05-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of N-channel metal oxide semiconductor (NMOS) transistor |
| TW201318073A (en) * | 2011-10-26 | 2013-05-01 | United Microelectronics Corp | Structure of field effect transistor with fin structure and fabricating method thereof |
| CN103531477A (en) * | 2012-07-05 | 2014-01-22 | 台湾积体电路制造股份有限公司 | FinFET method and structure with embedded underlying anti-punch through layer |
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| CN102074476A (en) * | 2009-11-20 | 2011-05-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of N-channel metal oxide semiconductor (NMOS) transistor |
| TW201318073A (en) * | 2011-10-26 | 2013-05-01 | United Microelectronics Corp | Structure of field effect transistor with fin structure and fabricating method thereof |
| CN103531477A (en) * | 2012-07-05 | 2014-01-22 | 台湾积体电路制造股份有限公司 | FinFET method and structure with embedded underlying anti-punch through layer |
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