CN106155973B - The digital low control processor of energy flexible configuration clock frequency - Google Patents
The digital low control processor of energy flexible configuration clock frequency Download PDFInfo
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- CN106155973B CN106155973B CN201610594207.5A CN201610594207A CN106155973B CN 106155973 B CN106155973 B CN 106155973B CN 201610594207 A CN201610594207 A CN 201610594207A CN 106155973 B CN106155973 B CN 106155973B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The present invention provides a kind of digital low control processor of energy flexible configuration clock frequency, comprising: multipath high-speed Analog-digital Converter channel, multipath high-speed digital-to-analogue conversion channel, multi-path digital output port, digital signal processing chip and interconnection system.Interconnection system is used to provide clock signal to digital signal processing chip, and interconnection system includes: clock distribution chip, for according to the configuration parameter of input reference signal and clock distribution chip register to digital signal processing chip tranmitting data register signal；With CPLD chip, for configuration parameter and storage configuration parameter to be arranged.A kind of integrated register parameters of digital low control processor of energy flexible configuration clock frequency of the invention automatically reply function and multichannel is fanned out to the clock distribution unit of function, integrated multipath High Speed Analog digital conversion channel, two-way high-speed figure analog-converted channel and multi-path digital output port, have the advantages that size is small, reliable and stable, economic and maintenance is convenient.
Description
Technical field
The present invention relates to a kind of digital low control processor more particularly to a kind of numbers of energy flexible configuration clock frequency
Word low level control processor.
Background technique
With the development of China's science and technology and the promotion of overall national strength, the electron accelerator of high-energy and high stability is
The research in multidisciplinary field provides experiment condition, some medical accelerators, as proton or heavy particle therapy device also have widely
Demand.Therefore the low level controller of high-precision, high stability and high integration is come into being.Accelerator high frequency low level control
Technology experienced full simulation control, digital added analogue control and all-digitized demodulator three phases.The sixties in last century and 90
The accelerator high frequency low level control in latter stage in age is full simulation control, and core element is analog feedback amplifier；Simulate addend
Word technology as a transition, exist the time is relatively short, using also not extensively.To this century, because large-scale integrated is electric
The development of road technique, FPGA (Field Programmable Gate Array, field programmable gate array) have obtained making extensively
With so that the high frequency low level controller of total digitalization becomes a reality.The logic that digital low controller utilizes FPGA to integrate
Door and programmable feature realize the low level feedback algorithm of high frequency, while there are also enough resources to provide more convenient people
Machine interactive interface and system diagnostics mode.Digitize research of the low level controller through more laboratory science workers, at
It is ripe and be widely applied to high-quality, i.e., more insertion pieces, Gao Liuqiang, low-energy-spread, Low emittance charged particle accelerator in, but it
To the particular/special requirement of the functions such as High Speed Analog digital conversion channel quantity, motor driving, communication modes, at present market still without
Method finds while integrating the clock distribution of automatic download function, four road High Speed Analog digital conversion channels, two-way high-speed figure mould
At quasi- ALT-CH alternate channel, the digital signal with CPCI (Compact PCI, compact PCI) communication and eight railway digital output ports
Manage device；It is single with function solidification, by coaxial cable connection structure challenge between board, improve high frequency signal amplitude and phase
The disadvantages of precision and stability control of position is to be improved, and hardware resource is inadequate, expensive, and exploitation maintenance is inconvenient.
Summary of the invention
In view of the deficiency of the prior art, the present invention provides a kind of digital low of energy flexible configuration clock frequency
Control processor, is integrated with automatic download function and multichannel is fanned out to the clock distribution unit of function, integrated four road High Speed Analog numbers
Word ALT-CH alternate channel, integrated two-way high-speed figure analog-converted channel and eight railway digital optical isolation output ports, have size small, steady
Fixed advantage reliable, economic and maintenance is convenient.
To achieve the goals above, the present invention provides a kind of digital low control processing of energy flexible configuration clock frequency
Device, comprising:
Multipath high-speed Analog-digital Converter channel；
Multipath high-speed digital-to-analogue conversion channel；
Multi-path digital output port；
One digital signal processing chip comes from the High Speed Analog for handling according to preset low level feedback algorithm
First digital signal of digital conversion channel forms the second digital signal and driving signal, and to the high-speed figure analog-converted
Channel exports second digital signal, Xiang Suoshu digital output port output drive signal；And
One interconnection system, the interconnection system include:
One clock distribution chip, for according to the one of an input reference signal and a register of the clock distribution chip
Configuration parameter sends a clock signal to the digital signal processing chip；With
One CPLD chip, for the configuration parameter to be arranged and stores the configuration parameter.
Preferably, the interconnection system further includes one being fanned out to chip, and the chip that is fanned out to is connected to the clock point
The clock signal described all the way between distribution chip and the digital signal processing chip, for issuing the clock distribution chip
Multichannel is fanned out to by same frequency.
Preferably, the High Speed Analog digital conversion channel includes connected a single-ended transfer difference unit and an analog-to-digital conversion
Device, the analog-digital converter and the digital signal processing chip communicate to connect.
Preferably, the single-ended transfer difference unit uses radio frequency transmission line transformer.
Preferably, the High Speed Analog digital conversion channel further includes an exclusion, and the exclusion is connected to the modulus and turns
Between parallel operation and the digital signal processing chip.
Preferably, high-speed figure analog-converted channel includes that connected a digital analog converter and a difference turn single-ended list
Member, the digital analog converter and the digital signal processing chip communicate to connect.
Preferably, the digital output port includes an output matched interfaces and a multi-channel digital logic optical isolation core
Piece, the multi-channel digital logic optical isolation chip be connected to the output matched interfaces and the digital signal processing chip it
Between.
It preferably, further include a CPCI communication interface, the CPCI communication interface connects the digital signal processing chip.
Preferably, the CPCI communication interface includes connected a PCI chip and a pci bus, at the digital signal
Chip is managed to connect the PCI chip and communicate to connect by the PCI chip and the pci bus and a host computer.
Preferably, the digital signal processing chip uses fpga chip.
The present invention due to use above technical scheme, make it have it is following the utility model has the advantages that
Digital signal processing chip is used to handle the first digital signal of No. four high-speed AD converters generation, realizes low electricity
Flat feedback algorithm exports the second digital signal and driving signal, realizes CPCI communication and realizes the functions such as interlock protection.
Four road High Speed Analog digital conversion channels meet the needs of present invention is to Analog-digital Converter number of channels.CPLD chip be used for
The signal that signal source provides is reference, and the configuration of clock distribution chip is carried out according to different demands, and configuration parameter is saved, i.e.,
Make board after a power failure, the parameter being stored in CPLD chip will not lose, can be to clock distribution core after re-powering
Register in piece is reconfigured.The effect of exclusion is the design of simplified PCB, installation, reduces the space of pcb board card, is protected
Demonstrate,prove welding quality.The effect of single-ended transfer difference unit is to improve voltage gain and signal transmission quality.Multichannel be fanned out to chip be by
The clock signal all the way of clock distribution chip is fanned out to multichannel by same frequency, meets the needs of present invention is to clock.Multi-channel digital
Logic optical isolation chip is for improving jamproof ability when digital data transmission.
Detailed description of the invention
Fig. 1 is the structural representation of the digital low control processor of the energy flexible configuration clock frequency of the embodiment of the present invention
Figure；
Fig. 2 is the structural schematic diagram of the High Speed Analog digital conversion channel of the embodiment of the present invention；
Fig. 3 is the sectional view in the high-speed figure analog-converted channel of the embodiment of the present invention；
Fig. 4 is the structural schematic diagram of the digital output port of the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of the interconnection system of the embodiment of the present invention；
Fig. 6 is the structural schematic diagram of the CPCI communication interface of the embodiment of the present invention；
Before digital low control processor and a radio frequency of the Fig. 7 for the energy flexible configuration clock frequency of the embodiment of the present invention
Hold the attachment structure schematic diagram of processor.
Specific embodiment
Below according to attached drawing 1-7, presently preferred embodiments of the present invention is provided, and is described in detail, makes to be better understood when
Function of the invention, feature.
Referring to Fig. 1, a kind of digital low control processor of energy flexible configuration clock frequency of the invention, including four
Road High Speed Analog digital conversion channel 1, two-way high-speed figure analog-converted channel 2, eight railway digital output ports 3, digital signal
Chip 4, an interconnection system 5 and a CPCI communication interface 6 are handled, wherein digital signal processing chip 4 is used for according to default
A low level feedback algorithm handle the first digital signal from High Speed Analog digital conversion channel 1 and form the second digital signal
And driving signal, and the second digital signal is exported to high-speed figure analog-converted channel 2, to 3 output driving of digital output port
Signal；Interconnection system 5 is used to simulate to digital signal processing chip 4, High Speed Analog digital conversion channel 1 and high-speed figure
ALT-CH alternate channel 2 provides clock signal.Digital signal processing chip 4 passes through CPCI communication interface 6 and an external host computer (in figure not
Show) communication connection.
In the present embodiment, digital signal processing chip 4 uses fpga chip, model EP2S60F1020I4, in other realities
Apply the fpga chip that can also select other models in example as needed.Digital signal processing chip 4 has 719 available I/
O stitch is realized low level feedback algorithm, is exported for handling the first digital signal of No. four high-speed AD converters generation
Second digital signal and driving signal realize CPCI communication and realize the functions such as interlock protection.Four road High Speed Analog numbers turn
It changes channel 1 and meets the needs of present invention is to Analog-digital Converter number of channels.Eight railway digital output ports 3 are mainly in the present invention
External motor provides driving signal, and can be realized simultaneously the synchronously control to two motors, can be used for adjusting external particle and adds
The field flatness of the resonance frequency of fast device high frequency cavity and more cell cavitys.
Referring to Fig. 2, High Speed Analog digital conversion channel 1 includes a single-ended transfer difference unit 11, the mould being sequentially connected
Number converter 12 and an exclusion 13, exclusion 13 are connected between analog-digital converter 12 and digital signal processing chip 4.The present embodiment
In, single-ended transfer difference unit 11 uses radio frequency transmission line transformer, in the present embodiment, using the radio frequency transmission line transformer of 1:1,
Its model ETC1-1T can also select the radio frequency transmission line transformer of other models as needed in other embodiments.
The radiofrequency signal of each High Speed Analog digital conversion channel 1 passes through single-ended transfer difference unit 11 and carries out single-ended slip
It is input to analog-digital converter 12 after dividing processing, which is 14, and highest sampling rate is 125Msps, type
Number be LTC2255, in other embodiments, can also as needed use other models analog-digital converter 12.Through analog-to-digital conversion
The first digital signal that device 12 exports is admitted in digital signal processing chip 4 again through exclusion 13 does corresponding algorithm.Exclusion 13
Effect be simplified PCB design, installation, reduce pcb board card space, guarantee welding quality.Single-ended transfer difference unit 11
Effect is to improve voltage gain and signal transmission quality.
Referring to Fig. 3, high-speed figure analog-converted channel 2 includes that connected a digital analog converter 21 and a difference turn single-ended
Unit 22, difference turn single-ended cell 22 using the radio frequency transmission line transformer of 1:1, model ETC1-1T.Digital analog converter 21 with
Digital signal processing chip 4 communicates to connect.
In the present embodiment, the second digital signal is output to the digital analog converter 21 that the binary channels that digit is 14 is converted, warp
After digital analog converter 21, it is converted into differential analog signal, is sent out after difference turns single-ended cell 22.The model of digital analog converter 21
The digital analog converter 21 of other models can also be selected as needed in other embodiments for ISL5927.
Referring to Fig. 4, digital output port 3 includes an output matched interfaces 31 and a multi-channel digital logic optical isolation core
Piece 32, multi-channel digital logic optical isolation chip 32 are connected between output matched interfaces 31 and digital signal processing chip 4.
In the present embodiment, the model AV02-6400 of multi-channel digital logic optical isolation chip 32, for improving digital letter
Jamproof ability can select the multi-channel digital logic light of other models in other embodiments as needed when number transmission
Isolating chip 32.Driving signal is exported through digital output port 3, the input terminal of this multi-channel digital logic optical isolation chip 32 and
Output end for electrically independent.
Referring to Fig. 5, interconnection system 5 includes the 51 (Complex Programmable Logic Devices of a CPLD chip being sequentially connected
Chip), a clock distribution chip 52 and one be fanned out to chip 53, be fanned out to chip 53 and digital signal processing chip 4 and communicate to connect.Its
In, clock distribution chip 52 is used for the configuration parameter according to an input reference signal and a register of clock distribution chip 52
To 4 tranmitting data register signal of digital signal processing chip.CPLD chip 51, for configuration parameter and storage configuration parameter to be arranged.
In the present embodiment, clock distribution chip 52 uses AD9510 clock chip, can receive the radio frequency lower than 1.2GHz
Signal, output frequency value can be changed by changing the different value of internal register, in this way can be according to real work frequency
The needs of rate, working frequency needed for design is connected to each component of clock distribution chip 52.It in other embodiments, can basis
Need to select the clock distribution chip 52 of other models.
CPLD chip 51 uses EPM3128ATC100-10 chip, is reference with the signal that signal source provides, according to different
Demand carries out the configuration of clock distribution chip 52, and configuration parameter is saved, even if board after a power failure, is stored in CPLD chip
Parameter in 51 will not lose, and after re-powering, can reconfigure to the register in clock distribution chip 52.
And CPLD chip 51 has 4 radical word line set signals to be connected with a JTAG program download port of digital signal processing chip 4, as that must change
Become the configuration parameter of 52 register of clock distribution chip, CPLD chip 51 can be carried out again by JTAG program download port
Configuration, increases the flexibility of system.In other embodiments, the CPLD chip 51 of other models can be selected as needed.
Input reference signal CLK1 input clock after single-ended transfer difference distributes chip 52, right in clock distribution chip 52
Register carries out parameter setting, obtains required output clock；CPLD chip 51 passes through the interface to clock distribution chip 52
STATUS, SCLK, SDIO, SDO and CSB are written and read, so that clock distribution chip 52 requires to be configured.CPLD chip
51 automatically will configure clock distribution chip 52 after the present invention powers on every time, because CPLD chip 51 is based primarily upon EEPROM
The programming of (Electrically Erasable Programmable Read-Only Memory) or FLASH reservoir, when CPLD chip 51 powers off, internal programming information will not
It loses.Register parameters setting in clock distribution chip 52 is saved in CPLD chip 51, digital low control is solved
The problem without memory of clock distribution chip 52 after device power down.Multichannel be fanned out to chip 53 be by clock distribution chip 52 all the way when
Clock signal is fanned out to multichannel by same frequency, meets the needs of present invention is to clock.
Referring to Fig. 6, CPCI communication interface 6 includes connected a PCI chip 61 and a pci bus 62, at digital signal
Chip 4 is managed to connect PCI chip 61 and communicate to connect by PCI chip 61 and pci bus 62 and a host computer, realization and host computer
Information exchange, the data that digital signal processing chip 4 is acquired and generated can be sent to host computer and be monitored, meanwhile, can also
The control command of host computer is sent into digital signal processing chip 4, interferes the operational process of control loop.
In the present embodiment, the model PCI9054 of PCI chip 61 can also select it as needed in other embodiments
The PCI chip 61 of his model.
Referring to Fig. 1, the invention has the following advantages that
(1), interconnection system 5 is integrated with the function that automatic download function and multichannel are fanned out to.Automatic download function guarantee
Clock configuration is not lost after processor power down.Multichannel, which is fanned out to, meets High Speed Analog digital conversion channel 1, high-speed figure analog-converted
The clock request in channel 2 and digital signal processing chip 4.Integrated level of the invention is improved, many external cablings are reduced, is increased
The hardware stability of strong digital low control system.
(2), four road High Speed Analog digital conversion channels 1 and two-way high-speed figure analog-converted channel 2, can preferably expire
The hardware requirement of sufficient charged particle accelerator medium-high frequency low level control.
(3), the present invention is based on CPCI communications improves the interactive speed of data using CPCI communication interface 6.
(4), the integrated eight railway digital output ports 3 of the present invention, it is low can to better meet charged particle accelerator medium-high frequency
Level controls the frequency of combination die group and the field flatness of more cell cavity mold groups.
(5), at application the size for entirely digitizing low level controller can reduce the present invention, and stability is reliable,
It is economical and practical, maintenance convenience.
Referring to Fig. 7, being the present invention in a digital low control when the present invention is connected to a radio-frequency front-end processing board 7
Systematic difference processed.
Radio-frequency front-end processing board 7 mainly realizes local oscillation signal generation, down coversion and up-conversion；The present invention realizes clock point
Match, the conversion of High Speed Analog number, high-speed figure analog-converted, numeral output, CPCI are communicated and the functions such as Digital Signal Processing.From
The signal (500MHz) that signal source is sent out is after power divider 71, wherein the benchmark all the way as clock distribution chip 52 is defeated
Enter, division register is used in clock distribution chip 52, obtains required 21 work clock f of digital analog converterDACDivided by 5, mould
12 work clock f of number converterADCDivided by 20 and intermediate-freuqncy signal clock fIFDivided by 16, this three timing relationships are as follows:
It may insure quadrature sampling in this way.
Because radio frequency signal frequency is relatively high (500MHz or higher), it is unpractical for directly carrying out sampling, and needs to carry out
Down coversion.And down coversion is then that the controlled signal (500MHz) of particle accelerator medium-high frequency system and local oscillation signal are mixed through first
Gained after frequency device 72 and first filter 73.The intermediate-freuqncy signal that local oscillation signal is then exported by reference signal and clock distribution chip 52
(468.75MHz) is generated after the second frequency mixer 74 and second filter 75.
Every road radiofrequency signal obtains orthogonal signalling amount each other through the sampling of analog-digital converter 12, in digital signal processing chip 4
Algorithm is done, if the amplitude and phase of radiofrequency signal control, frequency is adjusted, and the field flatness control of more cell chambers turns via digital-to-analogue
500MHz radiofrequency signal is restored to export after 77 up-conversion of parallel operation 21, third frequency mixer 76 and third filter.Wherein in frequency
When adjusting with the control of the field flatness of more cell chambers, needs to control the motor on chamber, mainly be exported by eight railway digitals
Port 3 exports the driving signal that pulse signal, enable signal and direction signal control to motor 8 after logical process.
Banding test is carried out in SSRF storage ring high frequency using the present invention, there is good control precision and stablize fortune
Row unfailing performance, specific number low level performance parameter are as follows.
It is above, only presently preferred embodiments of the present invention, the range being not intended to limit the invention, above-mentioned reality of the invention
Applying example can also make a variety of changes.Letter made by i.e. all claims applied according to the present invention and description
Single, equivalent changes and modifications, fall within the claims of the invention patent.
Claims (6)
1. a kind of digital low control processor of energy flexible configuration clock frequency characterized by comprising
Multipath high-speed Analog-digital Converter channel；
Multipath high-speed digital-to-analogue conversion channel；
Multi-path digital output port；
One digital signal processing chip, for being handled according to preset low level feedback algorithm from the High Speed Analog number
First digital signal of ALT-CH alternate channel forms the second digital signal and driving signal, and to high-speed figure analog-converted channel
Export second digital signal, Xiang Suoshu digital output port output drive signal；And
One interconnection system, the interconnection system include:
One clock distribution chip, for the configuration according to an input reference signal and a register of the clock distribution chip
Parameter sends a clock signal to the digital signal processing chip；
One CPLD chip, for the configuration parameter to be arranged and stores the configuration parameter, the CPLD chip and the number are believed
Number processing chip a JTAG program download port have 4 radical word line set signals be connected；With
One is fanned out to chip, and the chip that is fanned out to is connected between the clock distribution chip and the digital signal processing chip,
The clock signal described all the way for issuing the clock distribution chip is fanned out to multichannel by same frequency；
Wherein, the High Speed Analog digital conversion channel includes connected a single-ended transfer difference unit and an analog-digital converter, institute
It states analog-digital converter and the digital signal processing chip communicates to connect；The High Speed Analog digital conversion channel further includes a row
Resistance, the exclusion are connected between the analog-digital converter and the digital signal processing chip；
The digital output port includes an output matched interfaces and a multi-channel digital logic optical isolation chip, the multichannel
Digital Logic optical isolation chip is connected between the output matched interfaces and the digital signal processing chip.
2. the digital low control processor of energy flexible configuration clock frequency according to claim 1, which is characterized in that
The single-ended transfer difference unit uses radio frequency transmission line transformer.
3. the digital low control processor of energy flexible configuration clock frequency according to claim 1, which is characterized in that
High-speed figure analog-converted channel includes that connected a digital analog converter and a difference turn single-ended cell, the digital-to-analogue conversion
Device and the digital signal processing chip communicate to connect.
4. the digital low control processor of energy flexible configuration clock frequency according to claim 1, which is characterized in that
It further include a CPCI communication interface, the CPCI communication interface connects the digital signal processing chip.
5. the digital low control processor of energy flexible configuration clock frequency according to claim 4, which is characterized in that
The CPCI communication interface includes connected a PCI chip and a pci bus, described in the digital signal processing chip connection
PCI chip is simultaneously communicated to connect by the PCI chip and the pci bus and a host computer.
6. the digital low control processor of energy flexible configuration clock frequency according to claim 1-5,
It is characterized in that, the digital signal processing chip uses fpga chip.
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| US10523500B2 (en) * | 2017-09-26 | 2019-12-31 | Quanta Computer Inc. | Method and system for automatically configuring fanout mode of a network switch port in an interconnected network |
| CN108684133B (en) * | 2018-06-22 | 2020-07-17 | 中国科学院上海应用物理研究所 | Synchrotron high-frequency system and frequency and cavity pressure regulation and control method thereof |
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