CN106125033B - A kind of voltage and current synchronism classification error testing system - Google Patents
A kind of voltage and current synchronism classification error testing system Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a kind of voltage and current synchronisms to be classified error testing system, the system comprises：Main processor modules, FPGA module, voltage conversion acquisition circuit module, synchronization module, fiber optic serial sending module, fiber optic Ethernet receiving module, solve exist in the prior art can not to power-factor angle carry out precise and high efficiency test the technical issues of, system reasonable design is realized, the technique effect of precise and high efficiency tested power-factor angle is capable of.
Description
Technical field
The present invention relates to intelligent substation electronic mutual inductor accuracy technical field of measurement and test, and in particular, to Yi Zhong electricity
Current voltage synchronism is classified error testing system.
Background technology
Currently, signal is sent to a voltage combining unit (PT by the voltage in intelligent station by electronic type voltage transformer
MU), then voltage signal is sent to multiple interval MU by PT MU to cascade, is spaced MU by the electricity of the voltage of PT MU and this interval
Type current transformer (CT) synchronizes merging and exports again, and multiple interval MU carry out Network Transmitting by interchanger again and reach
Bay level IED equipment is shown in PT MU shown in attached drawing and interval MU.
The amplitude accuracy of the electronic mutual inductor of intelligent station is relatively stable, whether passes through cascade or network,
It can be always maintained at higher stability in amplitude, do not influenced by transmission mode.And the opposite phase between voltage and current signal
Position relationship, i.e. power-factor angle, but suffer from cascade and the influence of networking model, the whether accurate direct relation of power-factor angle
To the accuracy of electrical energy measurement.The digital electric energy metered system and tradition electrical energy measurement based on electronic mutual inductor often occurred
Slowly there is increasing electric energy difference with the time in system, also tends to that there are errors is related with power-factor angle that MU is exported
System.
At present in the debugging and detection of intelligent station, it is only directed to electronic current mutual inductor and electronic type voltage transformer
Independent accuracy test, lacks the special testing scheme and means to power-factor angle, can not while a side boosting
The adjustable controllable high current in current transformer primary side injecting power factor angle, leaves hidden to the safe and stable operation of system
Suffer from.
In conclusion present inventor is during inventive technique scheme in realizing the embodiment of the present application, in discovery
Technology is stated at least to have the following technical problems：
There is technical issues that precise and high efficiency can not be carried out to power-factor angle in the prior art.
Invention content
The present invention provides a kind of voltage and current synchronisms to be classified error testing system, solves and nothing exists in the prior art
The technical issues of method carries out precise and high efficiency test to power-factor angle, realizes system reasonable design, is capable of pair of precise and high efficiency
The technique effect that power-factor angle is tested.
In order to solve the above technical problems, the embodiment of the present application provides a kind of voltage and current synchronism classification error testing system
System, the system comprises：
On the one hand main processor modules, the main processor modules are used for：Run (SuSE) Linux OS, man-machine to system
Interface is managed, collector data frame group packet, tested combining unit frame receives and parsing；Described main processor modules another party
Face is used for：Markers processing, consecutive frame sending value calculate, consecutive frame delivery time calculates, power factor error calculates；
FPGA module, the FPGA module output and input control for system data；
Voltage converts acquisition circuit module, and the voltage conversion acquisition circuit module will be converted for carrying out voltage conversion
Voltage afterwards carries out AD samplings after low-pass filtering improves circuit；
Synchronization module, the synchronization module be used for for main processor modules, FPGA module, analog-digital converter provide it is various not
The operation work pace of same frequency demand, while 1PPS and IRIG-B codes are exported to tested combining unit；
Fiber optic serial sending module, the fiber optic serial sending module are used to complete the serial data frame of FPGA module control
Electricity to light convert, realize Multi-path electricity type current transformer ontology collector analogue data frame send；
Fiber optic Ethernet receiving module, the fiber optic Ethernet receiving module are used to complete the light that multichannel is tested combining unit
Fine ethernet data acceptance.
Wherein, voltage conversion acquisition circuit module is all connected with FPGA module, synchronization module, FPGA module and optical fiber ether
Net receiving module is all connected with main processor modules, and FPGA module is connect with fiber optic serial sending module.
Wherein, the main processor modules specifically include：ARM modules and DSP module, the ARM modules and the DSP moulds
Block connects, and the ARM modules are for running (SuSE) Linux OS, being managed to system man-machine interface, collector data frame group
Packet, tested combining unit frame receives and parsing；The DSP module is calculated for markers processing, consecutive frame sending value, consecutive frame is sent out
Calculating constantly, power factor error is sent to calculate.
Wherein, the FPGA module is specifically used for：The data frame for completing multi-channel optical fibre serial ports is sent, and realizes that multichannel electric current is mutual
The collector of sensor is simulated, and the sampled value of each ADC is demarcated current time index by the reading sequential of control analog-digital converter ADC, will
When each band primary processor is given in target sampled value.
Wherein, the voltage conversion acquisition circuit module is specifically used for：Voltage standard mutual inductor converts primary side high pressure
At the voltage of specified 100V/ √ 3, which enters voltage conversion acquisition circuit module, first by 0.01 grade of voltage transformer
The conversion that 100V/ √ 3 arrive 5V voltages is completed, 5V voltages improve circuit by low-pass filtering, into AD sampling elements, the work of sampling
Come from clock synchronization module as clock.
Wherein, AD samplings carry out under the timing control of synchronization module, and sample Du1, the T2 moment is obtained at moment T1
Du2 is obtained, and so on, occur from primary side high-voltage signal to the sampling for completing the voltage signal, is consumed during whole
Absolute delay time is set as Td_u, and Td_u is less than 50us.
Wherein, power factor error is：
E=(cos (θ t)-cos (θ)) * 100/cos (θ) (1), wherein θ t are voltage and current angle, and cos (θ t) is tested
The power factor of MU, θ are power-factor angle.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages：
1, true electronic type voltage transformer test can be carried out from the boosting of busbar, reach with real working conditions without
Difference is tested.
2, Multi-path electricity type current transformer is locked with voltage-phase with based on acquisition by the transformation of primary voltage high-precision
The sequential of simulation data achievees the effect that once to be flowed up while a side boosting, and solving current intelligent station can not be same
When boost and up-flow restriction, solve the test blindspot that can not carry out power factor angular accuracy.
3, the current sampling data of simulation data is accurately controlled with the delay time parameter of practical electronic current mutual inductor
Output time, test result are consistent with the actual running results.
4, by adjusting the size of current simulations output delay, reach the comprehensive mistake under a different power-factor angles
Difference test.
5, it is the angle of phase test from power-factor angle essence, avoids the amplitude test in mutual inductor codomain, specially
It notes in phase test so that this programme is feasible and efficient.
6, test method can be adapted for the work(under different mutual inductor principles, different mutual inductors producer, different networking models
Rate factor error testing；
7, MU at different levels are exported while is linked into test system, can show that power factors at different levels are missed in primary experiment
Difference, the power factor error convenient for analysis intelligent station are specifically to be generated in which link, are convenient for fault location and solution.
Description of the drawings
Attached drawing described herein is used for providing further understanding the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention；
Fig. 1 is the composition schematic diagram of voltage and current synchronism classification error testing system in the embodiment of the present application one.
Specific implementation mode
The present invention provides a kind of voltage and current synchronisms to be classified error testing system, solves and nothing exists in the prior art
The technical issues of method carries out precise and high efficiency test to power-factor angle, realizes system reasonable design, is capable of pair of precise and high efficiency
The technique effect that power-factor angle is tested.
In order to better understand the above technical scheme, in conjunction with appended figures and specific embodiments to upper
Technical solution is stated to be described in detail.
With reference to specific embodiment and attached drawing, detailed description further, but the implementation of the present invention are made to the present invention
Mode is without being limited thereto.
Embodiment one：
Referring to FIG. 1, this application provides a kind of voltage and current synchronisms to be classified error testing system, this test system master
It to be made of following main function module：
ARM+DSP main processor modules：
The primary processor of system use TI companies DM3730, it by 1GHz ARM Cortex-A8Core and 800MHz
TMS320C64x+DSP Core two parts composition, the ends ARM be mainly responsible for (SuSE) Linux OS, device man-machine interface management,
Collector data frame group packet, tested combining unit frame are received with parsing etc., DSP be substantially carried out the larger markers processing of workload,
Consecutive frame sending value calculates, consecutive frame delivery time calculates, power factor error calculates etc..Application layer (the application journey of the sides ARM
Sequence) it is connected by Codec Engine software modules between signal processing layer (operation of the sides DSP), it can be held at the ends compiling DSP
When line code and the ends ARM application program, it is all based on Codec Engine and carries out.
FPGA module：
FPGA has good timing control performance using xilinx companies Spartan6 series of X C6SLC150, FPGA, main
That is responsible for system bottom data outputs and inputs control.The data frame that FPGA completes multi-channel optical fibre serial ports is sent, and realizes multichannel
The collector of current transformer is simulated, and the occurrence and frame format of data frame are all precalculated by primary processor and organized to complete.
FPGA needs to control the reading sequential of analog-digital converter ADC simultaneously, will by the sampled value Accurate Calibration current time index of each ADC
When each band primary processor is given in target sampled value.
Voltage converts acquisition circuit module：
For voltage standard mutual inductor by primary side high pressure accurate transformation at the voltage of specified 100V/ √ 3, which enters " electricity
Pressure conversion acquisition circuit " module.The module is completed 100V/ √ 3 by 0.01 grade of voltage transformer first and is turned to 5V small voltages
It changes, 5V small voltages improve circuit by low-pass filtering, into AD sampling elements.A/D acquisition chips use 24 of TI companies
ADS1271, this ADC are the Delta-Sigma ADC of high s/n ratio, and the work clock of sampling comes from clock synchronization module.
Synchronization module：
Synchronization module is the operation work pace that system primary processor, FPGA, ADC etc. provide various different frequency demands,
1PPS and IRIG-B codes are exported simultaneously to tested combining unit, and high-precision clock synchronization module ensure that whole system sequence control
Accuracy and long-term stability.Crystal oscillator select OCXO50 constant-temperature crystal oscillators, -40 to 85 degree of operating temperature,
Temperature drift characteristic less than 1ppb, the low phase noise of -160dBc/1KHz, the low aging of maximum 10ppb/year.
Fiber optic serial sending module：
" electricity " of the serial data frame of fiber optic serial sending module completion FPGA controls arrives the conversion of " light ", realizes Multi-path electricity
The analogue data frame of type current transformer ontology collector is sent.Using the HFBR-1414 optical transmitters of Avago companies, symbol
802.5 Token Ring standard High Performance transmitters of IEEE 802.3 Ethernet are closed, include low noise across resistance prime amplifier,
The maximum data rate is up to 175MBd, and longest transmission range reaches 4km.
Fiber optic Ethernet receiving module：
The fiber optic Ethernet data receiver that multichannel is tested combining unit is completed, transceiver uses the AFBR5803 of Agilent,
Guarantee has enough bandwidth and response speed, typical rising and falling time to reach 2ns.PHY chip uses Intel Company
LXT971, it is the quick ether controller of 10/100M double speeds, compatible IEEE802.3；Support 10Base5,10Base2,
10BaseT, 100BASE-X, 100BASE-TX, 100BASE-FX, and connected medium can be detected automatically.
The function and connection relation and test philosophy of each module are as follows：
A side bus boosting first：Alternating current 220V voltage is accessed into pressure regulator, realizes that power-frequency voltage is adjusted, pressure regulator is defeated
Go out to access booster system.Booster system according to tested electronic type PT voltage class, by testing transformer or resonator system come
Realize that boosting, High voltage output access busbar.
By the high-precision voltage standard mutual inductor of 0.01 grade of accuracy class by primary side high pressure accurate transformation at 100V/
The voltage-measurable of √ 3, the voltage enter " voltage conversion acquisition circuit " module of test system.Test system passes through inside 0.01
The voltage transformer of grade completes the conversion that 100V/ √ 3 arrive 5V, into AD sampling modules.It is missed according to the angular difference of 0.01 grade of mutual inductor
Poor limit value is it is found that the control errors of the voltage signal progress of disease add 0.3 point at 0.3 point after Two Stages, i.e., maximum phase error is 0.6
Within point, which can be ignored.
5V signals enter AD behind signal condition circuit and acquire, and AD samplings carry out under the timing control of synchronization module,
Du2 is obtained at acquirement sample Du1, the T2 moment at moment T1, and so on.Occur from primary side high-voltage signal to the completion electricity
The sampling of signal, the time (absolute delay time) consumed during whole is pressed to be set as Td_u, which can determine tool
Body value can accomplish to be not more than 50us and stabilization.The value is less than the delay of domestic all electronic current mutual inductor ontologies at present
Time, the simulation data for control electronic current mutual inductor below provide feasible precondition.Pass through voltage sample value meter
Calculate the real-time frequency value f of current voltage signal.
This test system emulation output is electronic current mutual inductor ontology digital signal, between being accessed in Practical Project
Every the absolute delay time of the electronic type CT acquiring product parameters CT ontologies of MU1 and interval MU2, it is set as Td_ct1 and Td_ct2,
Foundation as emulation.
It while a side boosting, is exported, is realized while boosting by emulating practical electronic current mutual inductor
The true effect flowed up.For this purpose, controlling the simulation data of electronic current mutual inductor on the basis of voltage sample value.It is first
Amplitude transformation first is carried out to voltage sample value, as the instantaneous sampling value of current simulations output, then according to the reality to be emulated
Electronic current mutual inductor absolute delay time parameter controls the sequential of simulation data.
By taking the output of the electronic current mutual inductor of dummy spacings MU1 as an example, the sampled value at T1 moment is transformed to Di 1=ka*
Du1, T2 instance sample value are transformed to Di2=ka*Du2, and so on.Pass through electronic current mutual inductor and voltage signal acquisition
Absolute delay difference Δ T1=Td_ct1-Td_u control the output time of each sampled point, each sampled point is equal
The Δ T1 that is delayed is sent, i.e. Di 1 is sent in T1+ Δs T1, and Di2 is sent in T2+ Δs T1.
The electronic current mutual inductor simulation data instantaneous value for being spaced MU2 is Di 1=kb*Du1, Di2=kb*
Du2 ..., each sampled point delay Δ T2=Td_ct2-Td_u are sent.
Emulation is sent realizes serial communication based on " FPGA module " control " fiber optic serial sending module ", agreement follow by
Prevent the output protocol of true electronic current mutual inductor.
The case where above-mentioned experiment may be implemented primary voltage and current in phase position, i.e. power-factor angle θ=0, cos θ=1,
In order to simulate θ not be 0 the case where, the delay time Δ T1 and Δ T2 that above-mentioned electric current exports need to be adjusted, i.e. Δ T1'=Δs
The π f of T1+ θ/2, the Δ T2'=Δ T2+ π of θ/2 f, f are the above-mentioned frequency values calculated, and what is tested at this time is exactly system power factor
For cos θ the case where.
It is the particular content and realization principle of technique effect 2,3,4 herein.
Measured signal is divided into three-level, i.e. PT combining units output stage, is spaced combining unit output stage and network output
Grade, is shown in attached drawing " optic fiber transceiver module " received signal." synchronization module " sends 1PPS IRIG-B codes to MU at different levels,
Fiber optic Ethernet module receives tested three-level IEC61850-9-2 sampling value messages, and " ARM+DSP main processor modules " are from every
Its voltage and current angle theta t is calculated in the sampled value output of a MU, then the power factor for being tested MU is cos (θ t), final work(
Rate factor error is：
E=(cos (θ t)-cos (θ)) * 100/cos (θ)
It is the particular content and realization principle of technique effect 7 herein.
The parts selection of each function module is as follows：
Test system primary processor use TI companies DM3730 microprocessors, it by 1GHz ARM Cortex-
TMS320C64x+DSP Core two parts of A8Core and 800MHz form, and are integrated with 3D graphics processors, video accelerator
(IVA), MMC/SD cards, serial ports etc. are supported in 2.0 USB.
FPGA uses the XC6SLC150 of xilinx companies, belongs to Spartan6 series, has 147,443 logic units,
Compared with previous generation Spartan series, the series power consumption be only its 50%, and speed faster, linkage function it is more rich comprehensively.Energy
Completely new and more efficient pair register 6 is enough provided and inputs look-up table (LUT) logic and a series of abundant built-in system grade modules.
ARM mainly runs at end (SuSE) Linux OS, and DSP is substantially carried out Digital Signal Processing.
Ethernet controller is Intel Company LXT971.LXT971 is the quick ether control of single port 10/100M double speeds
Device, it is compatible with IEEE802.3；Support 10Base5,10Base2,10BaseT, 100BASE-X, 100BASE-TX, 100BASE-
FX, and connected medium can be detected automatically, select Agilent AFBR5803 as fiber optic network transceiver.
A/D acquisition chips are acquired signal as analog-digital converter using the ADS1271 of TI companies, this ADC is
24,50KHz bandwidth, the Delta-Sigma ADC of high s/n ratio.
The crystal oscillator of synchronization module selects OCXO50 constant-temperature crystal oscillators, -40 to 85 degree of operating temperature, less than 1ppb's
Temperature drift characteristic, the low phase noise of -160dBc/1KHz, the low aging of maximum 10ppb/year, High Precision Crystal Oscillator is primary processor
Timeticks are provided with FPGA, ensure that the accuracy of timing control and long-term stability.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages：
1, true electronic type voltage transformer test can be carried out from the boosting of busbar, reach with real working conditions without
Difference is tested.
2, Multi-path electricity type current transformer is locked with voltage-phase with based on acquisition by the transformation of primary voltage high-precision
The sequential of simulation data achievees the effect that once to be flowed up while a side boosting, and solving current intelligent station can not be same
When boost and up-flow restriction, solve the test blindspot that can not carry out power factor angular accuracy.
3, the current sampling data of simulation data is accurately controlled with the delay time parameter of practical electronic current mutual inductor
Output time, test result are consistent with the actual running results.
4, by adjusting the size of current simulations output delay, reach the comprehensive mistake under a different power-factor angles
Difference test.
5, it is the angle of phase test from power-factor angle essence, avoids the amplitude test in mutual inductor codomain, specially
It notes in phase test so that this programme is feasible and efficient.
6, test method can be adapted for the work(under different mutual inductor principles, different mutual inductors producer, different networking models
Rate factor error testing；
7, MU at different levels are exported while is linked into test system, can show that power factors at different levels are missed in primary experiment
Difference, the power factor error convenient for analysis intelligent station are specifically to be generated in which link, are convenient for fault location and solution.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (4)
1. a kind of voltage and current synchronism is classified error testing system, which is characterized in that the system comprises：
On the one hand main processor modules, the main processor modules are used for：Run (SuSE) Linux OS, to system man-machine interface
It is managed, collector data frame group packet, tested combining unit frame receives and parsing；On the other hand the main processor modules are used
In：Markers processing, consecutive frame sending value calculate, consecutive frame delivery time calculates, power factor error calculates；
FPGA module, the FPGA module output and input control for system data；
Voltage converts acquisition circuit module, and the voltage conversion acquisition circuit module, will be transformed for carrying out voltage conversion
Voltage carries out AD samplings after low-pass filtering improves circuit；
Synchronization module, the synchronization module are used to provide various different frequencies for main processor modules, FPGA module, analog-digital converter
The operation work pace of rate demand, while 1PPS and IRIG-B codes are exported to tested combining unit；
Fiber optic serial sending module, the fiber optic serial sending module are used to complete the electricity of the serial data frame of FPGA module control
It is converted to light, realizes that the analogue data frame of Multi-path electricity type current transformer ontology collector is sent；
Fiber optic Ethernet receiving module, the fiber optic Ethernet receiving module be used for complete multichannel be tested combining unit optical fiber with
Too network data receives；
Main processor modules are connect with FPGA module, and main processor modules are connect with fiber optic Ethernet receiving module, voltage conversion
Acquisition circuit module is connect with synchronization module, and voltage conversion acquisition circuit module is connect with FPGA module, FPGA module and optical fiber
Serial sending module connection；
The voltage conversion acquisition circuit module is specifically used for：Primary side high pressure is converted into specified by voltage standard mutual inductorVoltage, the voltage enter voltage conversion acquisition circuit module, first by 0.01 grade voltage transformer completeTo the conversion of 5V voltages, 5V voltages improve circuit by low-pass filtering, into AD sampling elements, when the work of sampling
Clock comes from clock synchronization module；
AD samplings carry out under the timing control of synchronization module, and Du2 is obtained at acquirement sample Du1, the T2 moment at moment T1, with
This analogizes, from primary side high-voltage signal occur to complete the voltage signal sampling, it is whole during consume absolute delay when
Between be set as Td_u, Td_u is less than 50us, and the real-time frequency value f of current voltage signal is calculated by voltage sample value；Primary
While side boosting, is exported by emulating practical electronic current mutual inductor, electronic type is controlled on the basis of voltage sample value
The simulation data of current transformer carries out amplitude transformation to voltage sample value first, the instantaneous sampling as current simulations output
Value, the absolute delay time parameter of practical electronic current mutual inductor then emulated as needed come control simulation data when
Sequence.
2. voltage and current synchronism according to claim 1 is classified error testing system, which is characterized in that the main process task
Device module specifically includes：ARM modules and DSP module, the ARM modules are connect with the DSP module, and the ARM modules are used for
Operation (SuSE) Linux OS is managed system man-machine interface, collector data frame group packet, is tested combining unit frame reception
With parsing；The DSP module is calculated for markers processing, consecutive frame sending value, consecutive frame delivery time calculates, power factor is missed
Difference calculates.
3. voltage and current synchronism according to claim 1 is classified error testing system, which is characterized in that the FPGA moulds
Block is specifically used for：The data frame for completing multi-channel optical fibre serial ports is sent, and is realized the collector simulation of multichannel current transformer, is controlled mould
The sampled value of each ADC is demarcated current time index, will be sent in target sampled value when each band by the reading sequential of number converter ADC
To primary processor.
4. voltage and current synchronism according to claim 1 is classified error testing system, which is characterized in that MU at different levels are defeated
Going out while being linked into test system, main processor modules calculate its voltage and current angle theta t from MU sampled values at different levels output,
The power factor for being then tested MU outputs is cos (θ t), and power factor error is：
E=(cos (θ t)-cos (θ)) * 100/cos (θ), wherein θ is system power factor angle.
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| CN201886095U (en) * | 2010-11-11 | 2011-06-29 | 中国电力科学研究院 | Test device of merging unit |
| CN103487695A (en) * | 2013-09-26 | 2014-01-01 | 国家电网公司 | Detection device for merging unit based on analog input |
| CN104198977A (en) * | 2014-08-06 | 2014-12-10 | 国家电网公司 | Accuracy detection method based on average power error for analog input combining unit |
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| US20080122422A1 (en) * | 2004-06-04 | 2008-05-29 | Iwatt Inc. | Parallel Current Mode Control Using a Direct Duty Cycle Algorithm with Low Computational Requirements to Perform Power Factor Correction |
| CN201886095U (en) * | 2010-11-11 | 2011-06-29 | 中国电力科学研究院 | Test device of merging unit |
| CN103487695A (en) * | 2013-09-26 | 2014-01-01 | 国家电网公司 | Detection device for merging unit based on analog input |
| CN104198977A (en) * | 2014-08-06 | 2014-12-10 | 国家电网公司 | Accuracy detection method based on average power error for analog input combining unit |
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