CN106095722A - A kind of Virtual Channel low consumption circuit being applied to network-on-chip - Google Patents
A kind of Virtual Channel low consumption circuit being applied to network-on-chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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Abstract
The invention discloses a kind of Virtual Channel low consumption circuit being applied to network-on-chip；It is characterized in that including: the clock anticipation ON/OFF module being made up of clock enable generation module and gated clock generation module；The caching segmentation gating module being made up of read-write control module and segmentation Clock gating module.The present invention can improve the utilization rate of single Virtual Channel caching, it is to avoid depended software monitoring and the nervous problem of sequential, thus reduces the power consumption of input-buffer in network-on-chip, and then reduces whole NoC power consumption, and ensures the correct transmission of data.
Description
Technical field
The invention belongs to the communication technical field of integrated circuit network-on-chip, particularly relate to a kind of network-on-chip that is applied to
Virtual Channel low power dissipation design circuit.
Background technology
Along with integrated circuit feature size reduction, clock frequency increases, and number of transistors integrated on one single chip exceedes
1000000000 orders of magnitude, interconnection line density improves constantly, and the proportion that interconnection architecture accounts for chip overall power is increasing, therefore reduces logical
The power consumption of communication network seems most important；The power consumption of network-on-chip is essentially from the transmission power consumption of packet, and storage power consumption；Grind
The persons of studying carefully have been observed that the energy that the energy that one packet of storage is consumed consumes much larger than one packet of transmission；When greatly
Amount data when node stores, then cause the biggest storage power consumption, and the caching power consumption therefore reducing input channel becomes particularly to weigh
Want.
Xian Electronics Science and Technology University the Jiang Xu rising sun master thesis of 2012 " NoC router and low power loss communication network
Design " in propose the mode using gated clock to close idle Virtual Channel and reduce power consumption；It is disadvantageous in that FIFO reading and writing
When enable is 1, open clock；In this case clock can lag behind read-write enable, and sequential can be caused nervous；Nanjing boat in 2009
Empty space flight university Zhai Liang is published in Nanjing Normal University's journal, and " network-on-chip routing unit low-power consumption based on gated clock sets
Meter " mode with module level gating technology that proposes in a literary composition closes idle Virtual Channel and reduces power consumption；It is disadvantageous in that not
Can automatically switch the clock of Virtual Channel, and need software support, depend on software and go the monitoring of network to close clock；Described two
The common weak point of article: network congested bigger in the case of, by the number of increase Virtual Channel and close in good time
The method falling idle Virtual Channel reduces power consumption, but this algorithm that can be greatly increased Virtual Channel input moderator and output president's device is multiple
Miscellaneous degree and resource overhead.
Summary of the invention
The present invention is higher for overcoming at network data injection rate, and buffer size is bigger, each nodal cache distribution inequality
In the case of even, it is proposed that a kind of Virtual Channel low consumption circuit being applied to network-on-chip, delay to single Virtual Channel can be improved
The utilization rate deposited, it is to avoid depended software monitoring and the nervous problem of sequential, thus reduce the merit of input-buffer in network-on-chip
Consumption, and then reduce whole NoC power consumption, and ensure the correct transmission of data.
The present invention be the technical scheme is that by reaching above-mentioned purpose
A kind of Virtual Channel low consumption circuit being applied to network-on-chip of the present invention, described network-on-chip is the two-dimensional mesh of M × N
Network, and be made up of several routing nodes；Each routing node has several passages, each routing node to include input state
Machine, decoder, moderator and cross bar switch；Described input state machine has several Virtual Channels and is carried out by Virtual Channel management circuit
Controlling, a Virtual Channel is made up of synchronization fifo；M and N is the integer more than or equal to 2；
Current routing node receives packet by described input state machine, and after utilizing described decoder to decode,
Carrying out requests for arbitration to described moderator, if obtaining arbitration license, then by described cross bar switch, described packet being transmitted extremely
Next routing node, otherwise, is saved in described packet in the Virtual Channel of current routing node；It is characterized in:
In described input state machine, be provided with described Virtual Channel low consumption circuit, and for control described Virtual Channel time
Clock switch and the access of described packet；
Described Virtual Channel low consumption circuit includes: clock anticipation ON/OFF module, caching segmentation gating module；
Described clock anticipation ON/OFF module includes: clock enables generation module, gated clock generation module；
Described caching segmentation module includes: read-write control module, segmentation Clock gating module；
Caching in all Virtual Channels is divided into the first caching FIFO_1 and second and delays by described read-write control module
Deposit FIFO_2；
Described clock enables generation module and receives the clock unlatching request signal of upper routing node decoder transmission also
Process, obtain Virtual Channel clock and enable signal and be sent to described gated clock generation module；
The described gated clock generation module Virtual Channel clock to being received enables signal and processes, when obtaining Virtual Channel
Clock signal is as the clock signal of described first caching FIFO_1；
Described Virtual Channel clock signal is also sent to described segmentation Clock gating module by described gated clock generation module
Described segmentation Clock gating module accepts described Virtual Channel clock signal and described second caching FIFO_2 sends
Spacing wave empty_2 and the first caching FIFO_1 send by full signal alm_full_1 and process, obtain described second
Clock signal clk_2 of caching FIFO_2；
Described read-write control module accepts spacing wave empty_1 of described first caching FIFO_1 transmission, by full letter
Number alm_full_1 and full signal full_1, and described second caching FIFO_2 send spacing wave empty_2, will full signal
Alm_full_2 and full signal full_2 also processes, and the reading obtaining described first caching FIFO_1 enables signal rd_en_1
With write enable signal wr_en_1, and described second caching FIFO_2 reading enable signal rd_en_2 and write enable signal wr_
en_2；Thus control described packet and cache the write in FIFO_1 and second caching FIFO_2 described first and read behaviour
Make.
The feature of the Virtual Channel low consumption circuit being applied to network-on-chip of the present invention lies also in:
Described clock enables generation module and comprises n or door, n MUX；
Request opened by the i-th clock that i-th or door receive on the four direction that a upper routing node decoder sends
Signal also carries out inclusive-OR operation, obtains i-th operation result and is sent to i-th MUX；1≤i≤n；
Described i-th MUX is according to described spacing wave empty_1 and spacing wave empty_2 and described i-th
Operation result, obtains i-th Virtual Channel clock and enables signal.
When described i-th Virtual Channel clock enable signal is " 0 ", if described i-th operation result is " 1 ", then i-th
Virtual Channel clock enables signal and is set to " 1 ", if described i-th operation result is " 0 ", the most described i-th Virtual Channel clock enables
Signal is set to " 0 "；
When described i-th Virtual Channel clock enable signal is " 1 ", if described i-th operation result is " 0 " and described
When the AND-operation result of spacing wave empty_1 and spacing wave empty_2 is " 1 ", the most described i-th Virtual Channel clock enables letter
Number it is set to " 0 "；If described i-th operation result is " 0 ", and the "AND" behaviour of described spacing wave empty_1 and spacing wave empty_2
When making result for " 0 ", the most described i-th Virtual Channel clock enables signal and is set to " 1 "；If described i-th operation result is " 1 ",
Then i-th Virtual Channel clock enables signal and is set to " 1 ".
Described gated clock generation module includes: n latch, n and door；
I-th latch receives i-th Virtual Channel clock and enables signal, and obtains according to the clock signal of described network-on-chip
To i-th latch signal and be sent to i-th and door；
The clock signal of described i-th latch signal and described network-on-chip is processed by described i-th with door, obtains
I-th Virtual Channel clock signal.
Described segmentation Clock gating module includes: MUX, latch, one and a door；
Described MUX receives spacing wave empty_2 and described first caching that described second caching FIFO_2 sends
FIFO_1 send by full signal alm_full_1 and process, obtain described second caching FIFO_2 clock enable signal
And it is sent to described latch；
Described latch enables signal, i-th Virtual Channel clock signal according to the clock of described second caching FIFO_2,
Latch signal to i-th Virtual Channel；
"AND" is carried out by described with door with i-th Virtual Channel clock signal by the latch signal of described i-th Virtual Channel
Operation, obtains clock signal clk_2 of described second caching FIFO_2.
When the described second clock enable signal caching FIFO_2 is " 0 ", if described first caching FIFO_1's will be full
Signal alm_full_1 is " 0 ", and the clock of the most described second caching FIFO_2 enables signal and is set to " 0 "；If described first caching
Full signal alm_full_1 is " 1 " by FIFO_1, and the clock of the most described second caching FIFO_2 enables signal and is set to " 1 "；
When the described second clock enable signal caching FIFO_2 is " 1 ", if described first caching FIFO_1's will be full
Signal alm_full_1 is " 0 ", and when described spacing wave empty_2 is " 1 ", the clock of the most described second caching FIFO_2 enables
Signal is set to " 0 "；If full signal alm_full_1 is " 0 " by described first caching FIFO_1, and described spacing wave empty_2
During for " 0 ", the clock of the most described second caching FIFO_2 enables signal and is set to " 1 "；If described first caching FIFO_1's will be full
Signal alm_full_1 is " 1 ", and the clock of the most described second caching FIFO_2 enables signal and is set to " 1 ".
Described read-write control module includes: three MUX, two depositors, read states select module, write
Condition selecting module, enumerator；
Described read states select module according to described first caching FIFO_1 send spacing wave empty_1, described second
Spacing wave empty_2 of caching FIFO_2 transmission, the carry signal of described enumerator, the read states letter of the first depositor output
Number, obtain the status signals of the first depositor input and be sent to described first depositor and store；
First MUX according to described first caching FIFO_1 send will full signal alm_full_1, described second
The status signals full signal alm_full_2, described first depositor exported that caching FIFO_2 sends, obtains described meter
Count enabling signal and being sent to described enumerator for obtaining the carry signal of described enumerator of device；
Second MUX enables according to status signals, the reading of i-th Virtual Channel of described first depositor output
Signal and low level, the reading reading to enable signal and described second caching FIFO_2 obtaining described first caching FIFO_1 enables letter
Number；
Described write state select module according to described first caching FIFO_1 send will full signal alm_full_1 and full
Signal full_1, described second caching FIFO_2 send will full signal alm_full_2 and full signal full_2, described first
The status signals of depositor output, the write state signal of described second depositor output, obtain writing of the second depositor input
Status signal is also sent to described second depositor and stores；
3rd MUX according to described second depositor output write state signal, i-th Virtual Channel write enable
Signal and level, the enable of writing of the write enable signal and described second caching FIFO_2 that obtain described first caching FIFO_1 is believed
Number；
If the write state signal that the write state signal of described second depositor output is described first caching FIFO_1, then will
The write enable signal of i-th Virtual Channel passes to the write enable signal of described first caching FIFO_1；And by described second caching
The write enable signal of FIFO_2 is set to " 0 "；
If the write state signal that the write state signal of described second depositor output is described second caching FIFO_2, then will
The write enable signal of i-th Virtual Channel passes to the write enable signal of described second caching FIFO_2；And by described first caching
The write enable signal of FIFO_1 is set to " 0 ".
When the status signals that status signals is the first caching FIFO_1 of the first depositor output；If the first caching
What FIFO_1 sent is " 1 " by full signal alm_full_1, then the enable signal of enumerator is set to " 1 "；Until described enumerator
Counting size equal to described first caching FIFO_1 the degree of depth, the enable signal of described enumerator is set to " 0 "；If described first
Full signal alm_full_1 is " 0 " by caching FIFO_1, and the enable signal of the most described enumerator is set to " 0 "；Until described the
Full signal alm_full_1 is " 1 " by one caching FIFO_1, and the enable signal of enumerator is set to " 1 "；
When the status signals that status signals is the second caching FIFO_2 of the first depositor output；If the second caching
What FIFO_2 sent is " 1 " by full signal alm_full_2, then the enable signal of enumerator is set to " 1 "；Until described enumerator
Counting size equal to described second caching FIFO_2 the degree of depth, the enable signal of enumerator is set to " 0 "；If described second caching
Full signal alm_full_2 is " 0 " by FIFO_2, then the enable signal of enumerator is set to " 0 "；Until described second caching
Full signal alm_full_2 is " 1 " by FIFO_2, and the enable signal of described enumerator is set to " 1 "；
If the status signals that the status signals of described first depositor output is described first caching FIFO_1, then will
The enable signal of reading of i-th Virtual Channel passes to the reading enable signal of described first caching FIFO_1；And by described second caching
The reading of FIFO_2 enables signal and is set to " 0 "；
If the status signals that the status signals of described first depositor output is described second caching FIFO_2, then will
The enable signal of reading of i-th Virtual Channel passes to the reading enable signal of described second caching FIFO_2；And by described first caching
The reading of FIFO_1 enables signal and is set to " 0 ".
In described read states selects module, when the status signals of the first depositor output is described first caching
During the status signals of FIFO_1, if the carry signal of described enumerator is " 1 ", and the sky that described second caching FIFO_2 sends
When signal empty_2 is " 0 ", the status signals of the most described first depositor input is the reading shape of described second caching FIFO_2
State signal；If the carry signal of described enumerator is " 0 ", the status signals of the most described first depositor input is described first
The status signals of caching FIFO_1；
When the status signals that the status signals of the second depositor output is described second caching FIFO_2, if described
The carry signal of enumerator is " 1 ", and spacing wave empty_1 that described first caching FIFO_1 sends is when being " 0 ", the most described the
The status signals of one depositor input is the status signals of described first caching FIFO_1；If the carry letter of described enumerator
Number being " 0 ", the status signals of the most described first depositor input is the status signals of described second caching FIFO_2；
In described write state selects module, when the write state signal of the second depositor output is described first caching
During the write state signal of FIFO_1, if what described first caching FIFO_1 sent is " 1 " by full signal alm_full_1 and described
When the full signal full_2 that second caching FIFO_2 sends is " 0 ", the write state signal of the most described second depositor input is institute
State the write state signal of the second caching FIFO_2；If the full signal full_2 that described second caching FIFO_2 sends is " 1 " or institute
State the first caching FIFO_1 transmission is " 0 " by full signal alm_full_1, and the write state of the most described second depositor input is believed
It number it is the write state signal of described first caching FIFO_1；
When the write state signal that the write state signal of the second depositor output is described second caching FIFO_2, if described
What the second caching FIFO_2 sent is " 1 " by full signal alm_full_2, and the full signal that described first caching FIFO_1 sends
When full_1 is " 0 ", the write state signal of the most described second depositor input is the write state letter of described first caching FIFO_1
Number；Will completely if the full signal full_1 that described first caching FIFO_1 sends be " 1 " or described second caching FIFO_2 sends
Signal alm_full_2 is " 0 ", and the write state signal of the most described second depositor input is writing of described second caching FIFO_2
Status signal.
Compared with prior art, the Advantageous Effects of the present invention is embodied in:
1, the Virtual Channel low consumption circuit being applied to network-on-chip that the present invention proposes, by using clock anticipation ON/OFF
Module and caching sectional door control module, efficiently solve caching maldistribution, the relatively big unfavorable shadow to power consumption of network congestion
Ring, do not increasing Virtual Channel number, and significantly reduce the overall power of NoC in the case of not affecting network performance.
2, the present invention is by using clock anticipation opening module, utilizes Method at Register Transfer Level gating technology to gate, logical
Cross the switch of the method control Virtual Channel clock being opened request signal by a upper routing node decoder tranmitting data register, lead to than void
The enable of writing in road opens clock in advance, overcomes the nervous problem with depended software of sequential, thus is not affecting network performance
In the case of reduce the power consumption of NoC.
3, the present invention is by using segmentation Clock gating module, and Virtual Channel is divided into two sections.Utilization is turned off in Virtual Channel
The method of idle caching section clock, decreases caching maldistribution, the highest impact on power consumption of Buffer Utilization, thus reduces
Power consumption in Virtual Channel.
4, the present invention is by using read-write control module, it is proposed that a kind of Read-write Catrol side for two sections of cachings
Method, only used a read counter and carries out reading control, and the resource that Read-write Catrol module uses is less, overcomes and additionally controls electricity
The problem that road resource overhead is the biggest, thus decrease the extra control circuit adverse effect to lower power consumption.
Accompanying drawing explanation
Fig. 1 is the overall structure figure that network-on-chip of the present invention single routing node Virtual Channel is arranged；
Fig. 2 is low power dissipation design circuit overall structure figure of the present invention；
Fig. 3 is that the clock of the clock anticipation ON/OFF module of Virtual Channel of the present invention enables signal generation figure；
Fig. 4 is segmentation Clock gating module circuit diagram of the present invention；
Fig. 5 is to cache the circuit diagram of Read-write Catrol in segmentation in one Virtual Channel of the present invention；
Fig. 6 is the power consumption comparison diagram of Virtual Channel under the conditions of segmentation FIFO of the present invention；
Fig. 7 is that the present invention closes multi-case data non-north transmission Virtual Channel and the power consumption comparison diagram opening three Virtual Channels；
Fig. 8 is that the present invention only opens multi-case data north transmission Virtual Channel and the power consumption comparison diagram opening three Virtual Channels.
Detailed description of the invention
In the present embodiment, network-on-chip is a kind of two-dimensional network of 6 × 6 based on stratification, is mainly used in mixing many
Broadcast route, be divided into upper level router and bottom router, be made up of 40 routing nodes；This network-on-chip with 3 × 3 sub-network
It is divided into four multicast area for unit；The intermediate router in each region passes through an additional port and upper level router phase
Even；Each routing node has several passages, each routing node to include that input state machine, decoder, moderator and intersection are opened
Close；Input state machine has three Virtual Channels and is controlled, as it is shown in figure 1, these three Virtual Channel is by Virtual Channel management circuit
Clean culture Virtual Channel, named Virtual Channel 1, prevailing transmission unicast packet；Multi-case data north transmission Virtual Channel, named Virtual Channel
2, the data transfer direction of prevailing transmission upper level router is the packet in transmission direction, north；Multi-case data non-north transmission void is logical
Road, named Virtual Channel 3, the data transfer direction of prevailing transmission upper level router is the packet in transmission direction, north；Virtual Channel
Management circuit includes input arbitration, output arbitration；Input arbitration is the channel number of the head microplate of input packet, by writing of input
Enable passes to corresponding Virtual Channel；Output arbitration is for using round-robin arbitration algorithm；One Virtual Channel is made up of synchronization fifo；
Current routing node receives packet by input state machine, and after utilizing decoder to decode, to moderator
Carry out requests for arbitration, if obtaining arbitration license, then by cross bar switch by the most next for packet transmission routing node, otherwise,
Packet is saved in the Virtual Channel of current routing node；
A kind of Virtual Channel low consumption circuit being applied to network-on-chip, is to be provided with the low merit of Virtual Channel in input state machine
Power consumption road, and for controlling the clock switch of Virtual Channel and the access of packet；
As it is shown in figure 1, Virtual Channel low consumption circuit includes: clock anticipation ON/OFF module, caching segmentation gating module；Its
In, clock anticipation ON/OFF module carries out the on-off control of clock to Virtual Channel idle in three Virtual Channels.Caching segmentation gate
The caching that module is left unused in reading Virtual Channel carries out the on-off control of clock.The gate control method combined by two modules can be not
In the case of changing Virtual Channel management circuit, such as when three Virtual Channels are opened, if only using clock anticipation ON/OFF module, then
The clock of three Virtual Channels is all turned on, then do not have lower power consumption.But now in the case of three Virtual Channels use inequality,
The clock that caching segmentation gating module can be used to turn off the second idle caching FIFO_2, can be effectively reduced the merit of Virtual Channel
Consumption.
Clock anticipation ON/OFF module includes: clock enables generation module, gated clock generation module；
Caching segmentation module includes: read-write control module, segmentation Clock gating module；
As in figure 2 it is shown, read-write control module the caching in all Virtual Channels is divided into the first caching FIFO_1 and
Second caching FIFO_2；The depth-set assuming a Virtual Channel is 8, then the first caching FIFO_1 and the second caching FIFO_2 is equal
It is 4.
Clock enables generation module and receives the clock unlatching request signal of upper routing node decoder transmission and carry out
Process, obtain Virtual Channel clock and enable signal and be sent to gated clock generation module；
The gated clock generation module Virtual Channel clock to being received enables signal and processes, and obtains Virtual Channel clock letter
Number as first caching FIFO_1 clock signal；
Virtual Channel clock signal is also sent to segmentation Clock gating module by gated clock generation module
Segmentation Clock gating module accepts Virtual Channel clock signal and the spacing wave of the second caching FIFO_2 transmission
Empty_2 and first caching FIFO_1 sends full signal alm_full_1 and processes, and obtains the second caching FIFO_2's
Clock signal clk_2；
Read-write control module accepts spacing wave empty_1 of the first caching FIFO_1 transmission, by full signal alm_
Full_1 and full signal full_1, and the second caching FIFO_2 send spacing wave empty_2, will full signal alm_full_2
With full signal full_2 processing, the reading obtaining the first caching FIFO_1 enables signal rd_en_1 and write enable signal wr_
En_1, and the reading enable signal rd_en_2 and write enable signal wr_en_2 of the second caching FIFO_2；Thus control packet
Write in the first caching FIFO_1 and the second caching FIFO_2 and read operation.Read-write control module primarily to
Ensure the data input and output in an orderly manner in Virtual Channel.It mainly comprises is a reading controlled state machine, writes controlled state for one
Machine, an enumerator, read controlled state owner and to control to select current time to read the first caching under the auxiliary of enumerator
FIFO_1 still reads the second caching FIFO_2.
Specifically, clock enable generation module comprises n or door, n MUX；
Request opened by the i-th clock that i-th or door receive on the four direction that a upper routing node decoder sends
Signal is also carried out or computing, obtains i-th operation result and is sent to i-th MUX；1≤i≤n；With present node
As a example by western passage, as it is shown on figure 3, that represent three four of western passage inputs of present node or door must receive a node time
Request signal opened by clock, and it is empty logical that the above node of institute has north passageway, Nan Tongdao, western passage, local channel to carry out present node
Road is asked.
I-th MUX, according to spacing wave empty_1 and spacing wave empty_2 and i-th operation result, obtains
I-th Virtual Channel clock enables signal；
When i-th Virtual Channel clock enable signal is " 0 ", if i-th operation result is " 1 ", then during i-th Virtual Channel
Clock enables signal and is set to " 1 ", if i-th operation result is " 0 ", then i-th Virtual Channel clock enables signal and is set to " 0 "；
When i-th Virtual Channel clock enable signal is " 1 ", if i-th operation result is " 0 ", and spacing wave empty_1
When being " 1 " with the AND-operation result of spacing wave empty_2, then i-th Virtual Channel clock enables signal and is set to " 0 "；If i-th
Operation result is " 0 ", and when the AND-operation result of spacing wave empty_1 and spacing wave empty_2 is " 0 ", then i-th void is led to
Road clock enables signal and is set to " 1 "；If i-th operation result is " 1 ", then i-th Virtual Channel clock enables signal and is set to " 1 "；
As it is shown on figure 3, v1_wr_req_n represents that a node north passageway is sent out 1 to the Virtual Channel of the western passage of present node and gone out
Write request, v2_wr_req_n represents that a node north passageway sends write request, v3_ to the Virtual Channel 2 of the western passage of present node
Wr_req_n represents that a node north passageway sends write request to the Virtual Channel 3 of the western passage of present node, and v1_wr_req_s represents
A upper road, node Nantong sends write request to the Virtual Channel 1 of the western passage of present node, and v2_wr_req_s represents a node Nantong
Road sends write request to the Virtual Channel 2 of the western passage of present node, and v3_wr_req_s represents that a road, node Nantong is to present node
The Virtual Channel 3 of western passage sends write request；V1_wr_req_w represents that a western passage of node leads to the void of the western passage of present node
Road 1 sends write request, and v2_wr_req_w represents that a western passage of node sends to the Virtual Channel 2 of the western passage of present node to write to be asked
Asking, v3_wr_req_w represents that a western passage of node sends write request, v1_wr_ to the Virtual Channel 3 of the western passage of present node
Req_l represents that a node local channel sends write request to the Virtual Channel 1 of the western passage of present node, and v2_wr_req_l represents
A upper node local channel sends write request to the Virtual Channel 2 of the western passage of present node, and v3_wr_req_l represents that a node is originally
Ground passage sends write request to the Virtual Channel 3 of the western passage of present node；As v1_wr_req_n, v1_wr_req_s, v1_wr_
When req_w, v1_wr_req_l have signal to be " 1 ", by v1_wr_req set, represent that Virtual Channel 1 obtains clock and opens request,
Virtual Channel clock enables signal en_clk_1 set；It is otherwise " 0 " as v1_wr_req, and when empty_v1 is " 1 ", Virtual Channel
Clock enables signal en_clk_1 reset；When v2_wr_req_n, v2_wr_req_s, v2_wr_req_w, v2_wr_req_l have
When signal is 1, by v2_wr_req set, representing that Virtual Channel 2 obtains clock and opens request, Virtual Channel clock enables signal en_
Clk_2 set；It is otherwise " 0 " as v2_wr_req, and when empty_v2 is " 1 ", Virtual Channel clock enables signal en_clk_2
Reset；When v3_wr_req_n, v3_wr_req_s, v3_wr_req_w, v3_wr_req_l have signal to be " 1 ", by v3_wr_
Req set, represents that Virtual Channel 1 obtains clock and opens request, and Virtual Channel clock enables signal en_clk_3 set；Otherwise when
V3_wr_req is " 0 ", and when empty_v3 is 1, Virtual Channel clock enables signal en_clk_3 reset；
In being embodied as, gated clock generation module includes: n latch, n and door；
I-th latch receives i-th Virtual Channel clock and enables signal, and obtains the according to the clock signal of network-on-chip
I latch signal is also sent to i-th and door；
The clock signal of i-th latch signal and network-on-chip is processed by i-th with door, obtains i-th Virtual Channel
Clock signal.
As it is shown on figure 3, owing to devising three Virtual Channels, it is therefore desirable to three latch, clock is enabled by three with door
Signal carries out synchronization process, to avoid the burr of clock signal.Such as, the clock that first latch can receive Virtual Channel 1 makes
Energy signal, when the clock of network-on-chip is low level, exports the input signal of latch, otherwise keeps initial value.
As shown in Figure 4, segmentation Clock gating module includes: MUX, latch, one and a door；
MUX receives spacing wave empty_2 and first of the second caching FIFO_2 transmission and caches what FIFO_1 sent
By full signal alm_full_1 and process, the clock obtaining the second caching FIFO_2 enables signal and is sent to latch；
When the clock enable signal of the second caching FIFO_2 is " 0 ", if the first caching FIFO_1's will full signal alm_
Full_1 is " 0 ", then the clock of the second caching FIFO_2 enables signal and is set to " 0 "；If the first caching FIFO_1's will full signal
Alm_full_1 is " 1 ", then the clock of the second caching FIFO_2 enables signal and is set to " 1 "；
When the clock enable signal of the second caching FIFO_2 is " 1 ", if the first caching FIFO_1's will full signal alm_
Full_1 is " 0 ", and when spacing wave empty_2 is " 1 ", then the clock of the second caching FIFO_2 enables signal and is set to " 0 "；If the
Full signal alm_full_1 is " 0 " by one caching FIFO_1, and when spacing wave empty_2 is " 0 ", then the second caching FIFO_2
Clock enable signal be set to " 1 "；If full signal alm_full_1 is " 1 " by the first caching FIFO_1, then the second caching
The clock of FIFO_2 enables signal and is set to " 1 "；
Latch enables signal, i-th Virtual Channel clock signal according to the clock of the second caching FIFO_2, obtains i-th
The latch signal of Virtual Channel；
Carried out AND-operation by the latch signal of i-th Virtual Channel and i-th Virtual Channel clock signal, obtain the second caching
Clock signal clk_2 of FIFO_2.
As it is shown in figure 5, read-write control module includes: three MUX, two depositors, read states select mould
Block, write state select module, enumerator；
Read states selects module to send out according to spacing wave empty_1, the second caching FIFO_2 of the first caching FIFO_1 transmission
Spacing wave empty_2 sent, the carry signal of enumerator, the status signals of the first depositor output, obtain the first depositor
The status signals of input is also sent to the first depositor and stores；
First MUX according to the first caching FIFO_1 send will full signal alm_full_1, the second caching
The status signals full signal alm_full_2, the first depositor exported that FIFO_2 sends, obtains the enable letter of enumerator
Number and be sent to enumerator for obtaining the carry signal of enumerator；As it is shown in figure 5, the first depositor is corresponding to depositor in figure
1, the first MUX is corresponding to MUX 1 in figure.The Main Function of enumerator is to count the data read,
Making data to export in an orderly manner, the size of enumerator is equal to the degree of depth of each section of caching.
When the status signals that status signals is the first caching FIFO_1 of the first depositor output；If the first caching
What FIFO_1 sent is " 1 " by full signal alm_full_1, then the enable signal of enumerator is set to " 1 "；Until the meter of enumerator
Number size is equal to the degree of depth of first paragraph caching, and the enable signal of enumerator is set to " 0 "；If the first caching FIFO_1's will full signal
Alm_full_1 is " 0 ", then the enable signal of enumerator is set to " 0 "；Until the first caching FIFO_1's will full signal alm_
Full_1 is " 1 ", and the enable signal of enumerator is set to " 0 "；
When the status signals that status signals is the second caching FIFO_2 of the first depositor output；If the second caching
What FIFO_2 sent is " 1 " by full signal alm_full_2, then the enable signal of enumerator is set to " 1 "；Until the meter of enumerator
Number size is equal to the degree of depth of second segment caching, and the enable signal of enumerator is set to " 0 "；If the second caching FIFO_2's will full signal
Alm_full_2 is " 0 ", then the enable signal of enumerator is set to " 0 "；Until the second caching FIFO_2's will full signal alm_
Full_2 is " 1 ", and the enable signal of enumerator is set to " 0 "；
Status signals, the reading of i-th Virtual Channel that second MUX exports according to the first depositor enable signal
And low level, the reading reading to enable signal and the second caching FIFO_2 obtaining the first caching FIFO_1 enables signal；Such as Fig. 5 institute
Showing, the second MUX is corresponding to MUX 2 in figure.
If the status signals that status signals is the first caching FIFO_1 of the first depositor output, then i-th is empty
The enable signal of reading of passage passes to the reading enable signal of the first caching FIFO_1；And the reading of the second caching FIFO_2 is enabled letter
Number it is set to " 0 "；
If the status signals that status signals is the second caching FIFO_2 of the first depositor output, then i-th is empty
The enable signal of reading of passage passes to the reading enable signal of the second caching FIFO_2；And the reading of the first caching FIFO_1 is enabled letter
Number it is set to " 0 "；
Write state select module according to the first caching FIFO_1 send will full signal alm_full_1 and full signal full_
The read states that full signal alm_full_2 and full signal full_2, the first depositor are exported that 1, the second caching FIFO_2 send
Signal, the write state signal of the second depositor output, obtain the write state signal of the second depositor input and be sent to second and post
Storage stores；
Write state signal that 3rd MUX exports according to the second depositor, the write enable signal of i-th Virtual Channel
And low level, obtain write enable signal and the write enable signal of the second caching FIFO_2 of the first caching FIFO_1；Such as Fig. 5 institute
Showing, the second depositor is corresponding to depositor 2 in figure, and the 3rd MUX is corresponding to MUX 3 in figure.
If the write state signal that write state signal is the first caching FIFO_1 of the second depositor output, then i-th is empty
The write enable signal of passage passes to the write enable signal of the first caching FIFO_1；And the enable of writing of the second caching FIFO_2 is believed
Number it is set to " 0 "；
If the write state signal that write state signal is the second caching FIFO_2 of the second depositor output, then i-th is empty
The write enable signal of passage passes to the write enable signal of the second caching FIFO_2；And the enable of writing of the first caching FIFO_1 is believed
Number it is set to " 0 ".
When being embodied as, in read states selects module, when the status signals of the first depositor output is the first caching
During the status signals of FIFO_1, if the carry signal of enumerator is " 1 ", and the spacing wave that the second caching FIFO_2 sends
When empty_2 is " 0 ", then the status signals that status signals is the second caching FIFO_2 of the first depositor input；If meter
The carry signal of number device is " 0 ", then the status signals that status signals is the first caching FIFO_1 of the first depositor input；
When the status signals that status signals is the second caching FIFO_2 of the second depositor output, if enumerator
Carry signal is " 1 ", and when spacing wave empty_1 of the first caching FIFO_1 transmission is " 0 ", then the reading of the first depositor input
Status signal is the status signals of the first caching FIFO_1；If the carry signal of enumerator is " 0 ", then the first depositor input
The status signals that status signals is the second caching FIFO_2；
Select in module in write state, when the write state signal of the second depositor output be the first caching FIFO_1 write shape
During state signal, if full signal alm_full_1 is " 1 " by the first caching FIFO_1 transmission, and second caches what FIFO_2 sent
When full signal full_2 is " 0 ", then the write state signal that write state signal is the second caching FIFO_2 of the second depositor input；
Will completely signal alm_ if the full signal full_2 that the second caching FIFO_2 sends be " 1 " or the first caching FIFO_1 sends
Full_1 is " 0 ", then the write state signal that write state signal is the first caching FIFO_1 of the second depositor input；
When the write state signal that write state signal is the second caching FIFO_2 of the second depositor output, if the second caching
What FIFO_2 sent is " 1 " by full signal alm_full_2, and the full signal full_1 that the first caching FIFO_1 sends is " 0 "
Time, then the write state signal that write state signal is the first caching FIFO_1 of the second depositor input；If the first caching FIFO_1
The full signal full_1 sent be " 1 " or the second caching FIFO_2 sends will signal alm_full_2 be completely " 0 ", then second post
The write state signal that write state signal is the second caching FIFO_2 of storage input.
As shown in Figure 6, a Virtual Channel, in caching segmentation gate, is divided into two sections, closes idle one by the present invention
FIFO is to reduce power consumption for section, respectively with the power consumption that Virtual Channel FIFO depth is 8,16,24,32 test input channels, works as FIFO_2
In the case of Xian Zhi, carrying out comprehensively based on synosys EDA platform Design Compiler, PT is carrying out power consumption test, surveying
Test result and lower power consumption about 40% when not adding caching segmentation gate.
As it is shown in fig. 7, the present invention only ought transmit measurement of power consumption in the case of Virtual Channel leaves unused, respectively with void in the non-north of multi-case data
Passage FIFO depth is the power consumption of 4,8,16,24 test input channels, based on synosys EDA platform Design Compiler
Carrying out comprehensive, carry out power consumption test on PT, test result is with lower power consumption when not adding Virtual Channel low power dissipation design circuit about
16%.
As shown in Figure 8, the present invention, when measurement of power consumption under multi-case data only north transmission Virtual Channel working condition, is led to void respectively
Road FIFO depth is the power consumption of 4,8,16,24 test input channels, based on synosys EDA platform Design Compiler
Carrying out comprehensive, carry out power consumption test on PT, test result is with lower power consumption when not adding Virtual Channel low power dissipation design circuit about
51%.
Claims (10)
1. being applied to a Virtual Channel low consumption circuit for network-on-chip, described network-on-chip is the two-dimensional network of M × N, and by
Several routing nodes are constituted；Each routing node has several passages, each routing node to include input state machine, decoding
Device, moderator and cross bar switch；Described input state machine has several Virtual Channels and is controlled by Virtual Channel management circuit, one
Individual Virtual Channel is made up of synchronization fifo；M and N is the integer more than or equal to 2；
Current routing node receives packet by described input state machine, and after utilizing described decoder to decode, to institute
Stating moderator and carry out requests for arbitration, if obtaining arbitration license, then by described cross bar switch, described packet being transmitted to next
Individual routing node, otherwise, is saved in described packet in the Virtual Channel of current routing node；It is characterized in that:
In described input state machine, it is provided with described Virtual Channel low consumption circuit, and opens for controlling the clock of described Virtual Channel
Close and the access of described packet；
Described Virtual Channel low consumption circuit includes: clock anticipation ON/OFF module, caching segmentation gating module；
Described clock anticipation ON/OFF module includes: clock enables generation module, gated clock generation module；
Described caching segmentation module includes: read-write control module, segmentation Clock gating module；
Caching in all Virtual Channels is divided into the first caching FIFO_1 and second caching by described read-write control module
FIFO_2；
Described clock enables generation module and receives the clock unlatching request signal of upper routing node decoder transmission and carry out
Process, obtain Virtual Channel clock and enable signal and be sent to described gated clock generation module；
The described gated clock generation module Virtual Channel clock to being received enables signal and processes, and obtains Virtual Channel clock letter
Number as described first caching FIFO_1 clock signal；
Described Virtual Channel clock signal is also sent to described segmentation Clock gating module by described gated clock generation module
Described segmentation Clock gating module accepts described Virtual Channel clock signal and the sky of described second caching FIFO_2 transmission
Signal empty_2 and first caching FIFO_1 sends full signal alm_full_1 and processes, and obtains described second caching
Clock signal clk_2 of FIFO_2；
Described read-write control module accepts spacing wave empty_1 of described first caching FIFO_1 transmission, by full signal
Alm_full_1 and full signal full_1, and described second caching FIFO_2 send spacing wave empty_2, will full signal
Alm_full_2 and full signal full_2 also processes, and the reading obtaining described first caching FIFO_1 enables signal rd_en_1
With write enable signal wr_en_1, and described second caching FIFO_2 reading enable signal rd_en_2 and write enable signal wr_
en_2；Thus control described packet and cache the write in FIFO_1 and second caching FIFO_2 described first and read behaviour
Make.
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 1, is characterized in that, described clock makes
N or door, n MUX can be comprised by generation module；
Request signal opened by the i-th clock that i-th or door receive on the four direction that a upper routing node decoder sends
And carry out inclusive-OR operation, obtain i-th operation result and be sent to i-th MUX；1≤i≤n；
Described i-th MUX is according to described spacing wave empty_1 and spacing wave empty_2 and described i-th computing
As a result, obtain i-th Virtual Channel clock and enable signal.
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 2, is characterized in that:
When described i-th Virtual Channel clock enable signal is " 0 ", if described i-th operation result is " 1 ", then i-th void is led to
Road clock enables signal and is set to " 1 ", if described i-th operation result is " 0 ", the most described i-th Virtual Channel clock enables signal
It is set to " 0 "；
When described i-th Virtual Channel clock enable signal is " 1 ", if described i-th operation result is " 0 ", and described empty letter
When the AND-operation result of number empty_1 and spacing wave empty_2 is " 1 ", the most described i-th Virtual Channel clock enables signal and puts
For " 0 "；If described i-th operation result is " 0 ", and the AND-operation knot of described spacing wave empty_1 and spacing wave empty_2
When fruit is " 0 ", the most described i-th Virtual Channel clock enables signal and is set to " 1 "；If described i-th operation result is " 1 ", then i-th
Individual Virtual Channel clock enables signal and is set to " 1 ".
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 1, is characterized in that, during described gate
Clock generation module includes: n latch, n and door；
I-th latch receives i-th Virtual Channel clock and enables signal, and obtains the according to the clock signal of described network-on-chip
I latch signal is also sent to i-th and door；
The clock signal of described i-th latch signal and described network-on-chip is processed by described i-th with door, obtains i-th
Individual Virtual Channel clock signal.
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 1, is characterized in that, during described segmentation
Clock gating module includes: MUX, latch, one and a door；
Described MUX receives spacing wave empty_2 and described first caching that described second caching FIFO_2 sends
FIFO_1 send by full signal alm_full_1 and process, obtain described second caching FIFO_2 clock enable signal
And it is sent to described latch；
Described latch enables signal, i-th Virtual Channel clock signal according to the clock of described second caching FIFO_2, obtains the
The latch signal of i Virtual Channel；
AND-operation is carried out by described with door with i-th Virtual Channel clock signal by the latch signal of described i-th Virtual Channel,
Obtain clock signal clk_2 of described second caching FIFO_2.
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 5, is characterized in that,
When the described second clock enable signal caching FIFO_2 is " 0 ", if described first caching FIFO_1's will full signal
Alm_full_1 is " 0 ", and the clock of the most described second caching FIFO_2 enables signal and is set to " 0 "；If described first caching FIFO_
The full signal alm_full_1 that incites somebody to action of 1 is " 1 ", and the clock of the most described second caching FIFO_2 enables signal and is set to " 1 "；
When the described second clock enable signal caching FIFO_2 is " 1 ", if described first caching FIFO_1's will full signal
Alm_full_1 is " 0 ", and when described spacing wave empty_2 is " 1 ", the clock of the most described second caching FIFO_2 enables signal
It is set to " 0 "；If full signal alm_full_1 is " 0 " by described first caching FIFO_1, and described spacing wave empty_2 is
Time " 0 ", the clock of the most described second caching FIFO_2 enables signal and is set to " 1 "；If described first caching FIFO_1's will full letter
Number alm_full_1 is " 1 ", and the clock of the most described second caching FIFO_2 enables signal and is set to " 1 ".
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 1, is characterized in that, described read-write letter
Number control module includes: three MUX, two depositors, read states select module, write state to select module, countings
Device；
Described read states selects module according to spacing wave empty_1 of described first caching FIFO_1 transmission, described second caching
Spacing wave empty_2 of FIFO_2 transmission, the carry signal of described enumerator, the status signals of the first depositor output,
To the status signals of the first depositor input and be sent to described first depositor and store；
First MUX according to described first caching FIFO_1 send will full signal alm_full_1, described second caching
The status signals full signal alm_full_2, described first depositor exported that FIFO_2 sends, obtains described enumerator
Enable signal be sent to described enumerator for obtaining the carry signal of described enumerator；
Second MUX enables signal according to status signals, the reading of i-th Virtual Channel of described first depositor output
And low level, the reading reading to enable signal and described second caching FIFO_2 obtaining described first caching FIFO_1 enables signal；
Described write state selection module will full signal alm_full_1 and full signal according to described first caching FIFO_1 transmission
Full_1, described second caching FIFO_2 send by full signal alm_full_2 and full signal full_2, described first deposit
The status signals of device output, the write state signal of described second depositor output, obtain the write state of the second depositor input
Signal is also sent to described second depositor and stores；
3rd MUX according to described second depositor output write state signal, the write enable signal of i-th Virtual Channel
And level, obtain write enable signal and the write enable signal of described second caching FIFO_2 of described first caching FIFO_1；
If the write state signal that the write state signal of described second depositor output is described first caching FIFO_1, then by i-th
The write enable signal of individual Virtual Channel passes to the write enable signal of described first caching FIFO_1；And by described second caching
The write enable signal of FIFO_2 is set to " 0 "；
If the write state signal that the write state signal of described second depositor output is described second caching FIFO_2, then by i-th
The write enable signal of individual Virtual Channel passes to the write enable signal of described second caching FIFO_2；And by described first caching
The write enable signal of FIFO_1 is set to " 0 ".
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 7, is characterized in that,
When the status signals that status signals is the first caching FIFO_1 of the first depositor output；If the first caching
What FIFO_1 sent is " 1 " by full signal alm_full_1, then the enable signal of enumerator is set to " 1 "；Until described enumerator
Counting size equal to described first caching FIFO_1 the degree of depth, the enable signal of described enumerator is set to " 0 "；If described first
Full signal alm_full_1 is " 0 " by caching FIFO_1, and the enable signal of the most described enumerator is set to " 0 "；Until described the
Full signal alm_full_1 is " 1 " by one caching FIFO_1, and the enable signal of enumerator is set to " 1 "；
When the status signals that status signals is the second caching FIFO_2 of the first depositor output；If the second caching
What FIFO_2 sent is " 1 " by full signal alm_full_2, then the enable signal of enumerator is set to " 1 "；Until described enumerator
Counting size equal to described second caching FIFO_2 the degree of depth, the enable signal of enumerator is set to " 0 "；If described second caching
Full signal alm_full_2 is " 0 " by FIFO_2, then the enable signal of enumerator is set to " 0 "；Until described second caching
Full signal alm_full_2 is " 1 " by FIFO_2, and the enable signal of described enumerator is set to " 1 ".
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 7, is characterized in that,
If the status signals that the status signals of described first depositor output is described first caching FIFO_1, then by i-th
The enable signal of reading of individual Virtual Channel passes to the reading enable signal of described first caching FIFO_1；And by described second caching
The reading of FIFO_2 enables signal and is set to " 0 "；
If the status signals that the status signals of described first depositor output is described second caching FIFO_2, then by i-th
The enable signal of reading of individual Virtual Channel passes to the reading enable signal of described second caching FIFO_2；And by described first caching
The reading of FIFO_1 enables signal and is set to " 0 ".
The Virtual Channel low consumption circuit being applied to network-on-chip the most according to claim 7, is characterized in that,
In described read states selects module, when the status signals of the first depositor output is described first caching FIFO_1
During status signals, if the carry signal of described enumerator is " 1 ", and the spacing wave that described second caching FIFO_2 sends
When empty_2 is " 0 ", the status signals of the most described first depositor input is the read states letter of described second caching FIFO_2
Number；If the carry signal of described enumerator is " 0 ", the status signals of the most described first depositor input is described first caching
The status signals of FIFO_1；
When the status signals that the status signals of the second depositor output is described second caching FIFO_2, if described counting
The carry signal of device is " 1 ", and when spacing wave empty_1 of described first caching FIFO_1 transmission is " 0 ", the most described first posts
The status signals of storage input is the status signals of described first caching FIFO_1；If the carry signal of described enumerator is
" 0 ", the status signals of the most described first depositor input is the status signals of described second caching FIFO_2；
In described write state selects module, when the write state signal of the second depositor output is described first caching FIFO_1
During write state signal, if described first caching FIFO_1 transmission is " 1 " by full signal alm_full_1, and described second caching
The full signal full_2 that FIFO_2 sends is when be " 0 ", and the write state signal of the most described second depositor input is described second slow
Deposit the write state signal of FIFO_2；If the full signal full_2 that described second caching FIFO_2 sends is that " 1 " or described first delays
Deposit FIFO_1 transmission is " 0 " by full signal alm_full_1, and the write state signal of the most described second depositor input is described
The write state signal of the first caching FIFO_1；
When the write state signal that the write state signal of the second depositor output is described second caching FIFO_2, if described second
What caching FIFO_2 sent is " 1 " by full signal alm_full_2, and the full signal full_ that described first caching FIFO_1 sends
1 when being " 0 ", and the write state signal of the most described second depositor input is the write state signal of described first caching FIFO_1；If
The full signal full_1 that described first caching FIFO_1 sends be " 1 " or described second caching FIFO_2 sends will full signal
Alm_full_2 is " 0 ", and the write state signal of the most described second depositor input is the write state of described second caching FIFO_2
Signal.
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