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CN106062960B - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN106062960B
CN106062960B CN201580011602.XA CN201580011602A CN106062960B CN 106062960 B CN106062960 B CN 106062960B CN 201580011602 A CN201580011602 A CN 201580011602A CN 106062960 B CN106062960 B CN 106062960B
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impurity region
semiconductor substrate
surface side
carrier concentration
front surface
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CN106062960A (zh
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小野泽勇一
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Fuji Motor Co Ltd
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Fuji Motor Co Ltd
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Abstract

从半导体基板的背面侧注入质子，除了使半导体基板内部的缺陷恢复，还使半导体基板的正面侧中的沟道形成区的缺陷恢复。由此，减少栅极阈值电压的偏差，减少施加反向电压时的漏电流。提供一种半导体装置，具备：在背面侧具有包含质子的n型杂质区的半导体基板；和在半导体基板的正面侧对质子具有阻挡效果的阻挡金属部。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
以往，作为绝缘栅双极型晶体管(以下简称为IGBT)的发射极，已知在阻挡金属层上形成铝电极(例如，专利文献1的第0027段)。另外，已知通过向半导体基板注入质子之后进行退火，从而缓和结晶缺陷(例如，专利文献2)。除此之外，还已知通过向半导体基板注入质子之后进行退火，从而由空穴(V)、氧(O)以及氢(H)形成VOH缺陷，该VOH缺陷变成供给电子的施主(例如，专利文献2)。
现有技术文献
专利文献
专利文献1：日本特开2006-080110号公报
专利文献2：日本国际公开2013/100155号公报
发明内容
技术问题
发射极所使用的阻挡金属部具有阻挡质子向半导体基板注入的效果。因此，隔着阻挡金属部对半导体基板进行质子注入和热处理，缺陷也不会充分恢复。因此，还考虑在形成阻挡金属部之前从设置发射极的半导体基板的正面侧向半导体基板内注入质子，然后通过热处理使缺陷恢复，之后从设置集电极的半导体基板的背面向半导体基板内注入质子，然后通过热处理使缺陷恢复。然而，若增加质子注入后的热处理工序，则制造成本会上升。
技术方案
在本发明的第一实施方式中，提供具备半导体基板和阻挡金属部的半导体装置。半导体基板可以在其背面侧具有包含质子的n型杂质区。阻挡金属部可以在半导体基板的正面侧对质子具有阻挡效果。从n型杂质区扩散的质子可以恢复残留于半导体基板内部的缺陷。另外，从n型杂质区扩散的质子可以终结栅极绝缘膜与半导体基板之间的界面的悬挂键。即，在栅极绝缘膜与半导体基板之间的界面可以存在氢原子。
n型杂质区可以在半导体基板的背面侧与正面侧之间的不同的深度位置具有载流子浓度的多个峰。另外，n型杂质区可以具有第一杂质区和第二杂质区。第一杂质区可以具有含预先决定的载流子浓度的杂质区。第二杂质区的载流子浓度可以比预先决定的载流子浓度低。第二杂质区可以设置于比第一杂质区更靠近半导体基板的背面侧的位置。另外，从半导体基板的正面侧朝向背面侧，n型杂质区可以具有第一杂质区～第四杂质区。第一杂质区的载流子浓度比第二杂质区的载流子浓度大，第一杂质区的载流子浓度和第三杂质区的载流子浓度大致相等，第四杂质区的载流子浓度可以比第一杂质区的载流子浓度大。
可以在半导体基板的正面侧进一步具备栅电极。另外，还可以具备设置在栅电极与半导体基板之间的栅极绝缘膜。在栅极绝缘膜与半导体基板之间的界面可以存在氢原子。
在本发明的第二实施方式中，提供半导体装置的制造方法，其具备：形成阻挡金属部的阶段、形成杂质区的阶段以及进行热处理的阶段。形成阻挡金属部的阶段可以在半导体基板的正面侧对质子具有阻挡效果。在形成杂质区的阶段中，可以从半导体基板的背面侧注入质子。在进行热处理的阶段中，可以对已注入了质子的半导体基板进行热处理。
形成杂质区的阶段可以包括改变包含加速电压和每单位面积的注入量的注入条件，多次向不同深度的位置注入质子的阶段。另外，形成杂质区的阶段可以具有进行第一次质子注入的阶段和进行第二次质子注入的阶段。在进行第一次质子注入的阶段中，可以形成含预先决定的载流子浓度的杂质区。在进行第二次质子注入的阶段中，可以为了使载流子浓度比预先决定的载流子浓度低而改变注入条件，之后相比第一次质子注入的阶段在更靠近半导体基板的背面侧的位置形成杂质区。
形成杂质区的阶段可以进一步具有进行第三次质子注入的阶段和进行第四次质子注入的阶段。在进行第三次质子注入的阶段中，可以相比第二次质子注入的阶段在更靠近半导体基板的背面侧的位置形成杂质区。在进行第四次质子注入的阶段中，可以相比第三次质子注入的阶段在更靠近半导体基板的背面侧的位置形成杂质区。若将第一次、第二次、第三次以及第四次质子注入中的每单位面积的注入量分别设为N1、N2、N3以及N4，则可以满足N2＜N1～N3＜N4的关系。
应予说明，上述的发明的内容没有例举出本发明的全部必要特征。并且，这些特征组的子组合也可属于本发明。
附图说明
图1是表示半导体装置100的构成例的图。
图2中(a)～(d)是依次形成FS层50中的第一杂质区～第四杂质区的工序的图。
图3是表示在对注入了质子的半导体基板90进行热处理之后的第一杂质区～第四杂质区中的载流子浓度分布的图。
图4是表示与FS层50的有无对应的漏电流的比较结果的图。
图5a是表示在半导体基板90的正面侧形成MOS栅结构30的阶段的图。
图5b是表示对半导体基板90的背面侧进行研磨的阶段的图。
图5c是表示从半导体基板90的背面侧注入质子的阶段的图。
图5d是表示对半导体基板90进行热处理的阶段的图。
图5e是示意地表示半导体基板90的缺陷得到恢复的情况的图。
图5f是表示在半导体基板90的背面侧形成集电极层60和集电极70的阶段的图。
图6a是表示从半导体基板90的背面侧注入质子的阶段的图。
图6b是表示对半导体基板90进行热处理的阶段的图。
图6c是表示在半导体基板90的缺陷得到恢复之后，在半导体基板90的背面侧形成集电极层60和集电极70的阶段的图。
图7是表示半导体基板90的氢的分布的图。
符号说明
20：第一金属层
21：层间绝缘膜
22：第一金属的氮化物层
24：第二金属层
26：发射极
28：插件
30：MOS栅结构
32：第一导电型区
34：第二导电型区
36：栅电极
38：栅极绝缘膜
40：基区层
50：FS层
51：杂质区
60：集电极层
70：集电极
90：半导体基板
95：氢扩散区nn
100：半导体装置
200：半导体装置
具体实施方式
以下，通过本发明的实施方式说明本发明，但以下的实施方式并不限定权利要求中的发明。另外，在实施方式中说明的特征的组合未必全部都是解决本发明的技术问题的必要技术特征。另外，在本申请说明书的说明中，1E+15中的E的记载是以10为幂的底数，例如1E+15是指1×1015。
图1是表示半导体装置100的构成例的图。图1表示沿横切栅电极36的方向切割的半导体装置100的截面。应予说明，半导体装置100虽然具有多个IGBT元件和其他的元件，但在图1中仅表示一个IGBT。
半导体装置100在半导体基板90的正面侧具有MOS栅结构30，在半导体基板90的背面侧具有pn结。在本说明书中，半导体基板90的表(正)面是指形成发射极26的一面，半导体基板90的背面是指形成集电极70的一面。另外，正面侧是指靠近半导体基板90的表面的一面，背面侧是指靠近半导体基板90的背面的一面。例如，第二导电型区34的正面侧是指第二导电型区34与第一金属的氮化物层22之间的界面，第二导电型区34的背面侧是指第二导电型区34与基区层40之间的界面。
半导体装置100具备半导体基板90、设置于半导体基板90的正面侧的发射极26和层间绝缘膜21、设置于半导体基板90的背面侧的集电极70。半导体基板90具有第一导电型区32、第二导电型区34、栅电极36、栅极绝缘膜38、基区层40、FS层50以及集电极层60。
MOS栅结构30具有发射极26、层间绝缘膜21、第一导电型区32、第二导电型区34、栅电极36以及栅极绝缘膜38。在第二导电型区34的与栅极绝缘膜38之间的界面，即隔着栅极绝缘膜38与栅电极36对置的界面是沟道形成区。沟道形成区是在栅电极36施加MOS栅极的阈值以上的电压时形成n型的反型层的区域。发射极26具有第一金属层20、第一金属的氮化物层22以及第二金属层24。第一金属层20和第一金属的氮化物层22构成相对于第二金属层24的阻挡金属部。作为阻挡金属部的第一金属层20和第一金属的氮化物层22用于减少第二金属层24和第一导电型区32之间的接触电阻。另外，阻挡金属部改善发射极26的覆盖。
在本例中，第一金属层20为钛层，第一金属的氮化物层22为氮化钛层，第二金属层24为铝层。在其他的例子中，第一金属层20可以为钽层，第一金属的氮化物层22可以为氮化钽层。
阻挡金属部还具有防止金属材料向半导体基板90扩散的功能。另外，阻挡金属部在设置于半导体基板90的正面侧的情况下，具有阻挡从正面侧注入到半导体基板90的质子(H+离子)的效果。
本例的MOS栅结构30具有所谓的沟槽栅结构。在本例中第一导电型区32为形成于基区层40的正面侧的n+型区。另外，第二导电型区34是包围第一导电型区32，并以分离第一导电型区32和基区层40的方式形成的p型区。若向栅电极36施加规定的电压，则在栅极绝缘膜38和第二导电型区34形成沟道，第一导电型区32和基区层40导通。由此，MOS栅结构30作为MOSFET动作。
基区层40为第一导电型的半导体层。本例的基区层40为n型硅层。在MOS栅结构30作为MOSFET动作时，基区层40作为漂移层起作用。
FS层50具有第一导电型的杂质，形成于基区层40的背面侧。FS层50形成在半导体基板90的背面侧的附近。FS层50是终止施加反向电压时的耗尽层的扩散的场终止(FieldStop)层。
FS层50具有包含质子的n型杂质区。n型杂质区是通过注入质子并进行热处理而形成的n+型的区域。n型杂质区在半导体基板90的背面侧与正面侧之间的不同深度的位置具有载流子浓度的多个峰。通过多次以不同的加速电压从半导体基板90的背面侧注入质子，能够调节质子的注入位置。另外，通过改变每单位面积的注入量并多次在不同深度的位置注入质子，能够根据质子的注入位置调节杂质浓度。应予说明，质子注入阶段在集电极层60和集电极70的形成阶段之前进行。
在半导体基板90为硅晶圆的情况下，半导体基板90具有某种程度的氧。例如，FZ晶圆具有1E+15cm-3～1E+16cm-3的程度的氧。另外例如，CZ晶圆具有1E+16cm-3～1E+17cm-3的程度的氧。应予说明，半导体基板90因质子注入或者电子束照射等而导致在内部具有空穴(V)。通过对具有空穴(V)、氧(O)以及氢(H)的半导体基板90进行热处理(退火)，从而在FS层50形成VOH缺陷。VOH缺陷是供给电子的施主。
因此，FS层50的n型杂质区作为场终止层起作用。因此，能够防止在施加反向电压时耗尽层扩散至超越FS层50。由此，能够减少施加反向电压时的漏电流。
应予说明，注入到半导体基板90的质子不是全部都有助于VOH缺陷的形成。即，注入到半导体基板90的质子的一部分在半导体基板90的内部扩散。例如，被注入的质子的一部分会扩散到半导体基板90的正面侧。
扩散到半导体基板90的正面侧的质子使半导体基板90内部的缺陷恢复。例如，从半导体基板90的背面侧扩散到正面侧的质子能够使在栅极绝缘膜38附近的第二导电型区34的结晶缺陷恢复。即，能够使在IGBT的沟道形成区中的结晶缺陷恢复。另外，还能够恢复在形成设置栅电极36的沟槽时产生的第二导电型区34和基区层40的缺陷(蚀刻损伤)。由此，能够减少各IGBT的栅极阈值电压(Vth)的偏差。
集电极层60设置于半导体基板90的背面侧的端部。集电极层60具有第二导电型的杂质。本例的集电极层60为p+型硅层。应予说明，第一导电型区32、第二导电型区34、基区层40、FS层50以及集电极层60由相同的材料(本例中为硅)形成。
集电极70形成于集电极层60的背面侧。集电极70通过将例如铝蒸镀或者溅射到集电极层60的背面侧而形成。
图2中(a)～(d)是表示形成FS层50中的第一杂质区～第四杂质区的工序的图。本例的FS层50中的n型杂质区具有第一杂质区51a～第四杂质区51d。应予说明，第一杂质区51a～第四杂质区51d为例示，n型杂质区还可以具有五个以上的杂质区。第一杂质区51a位于n型杂质区中的最正面侧。第二杂质区51b设置于比第一杂质区51a更靠近半导体基板90的背面侧的位置。第三杂质区51c设置于比第二杂质区51b更靠近半导体基板90的背面侧的位置，第四杂质区51d设置于比第三杂质区51c更靠近半导体基板90的背面侧的位置。
在本例中，在形成了MOS栅结构30之后，从半导体基板90的背面注入质子。首先，在加速电压是1.45MeV、每单位面积的注入量是1E+13/cm2的条件下，进行第一次质子注入。接下来，将注入条件改变为加速电压是1.10MeV、每单位面积的注入量是7E+12/cm2，相比第一次质子注入的阶段在更靠近半导体基板90的背面侧的位置，进行第二次质子注入。通过使第一次的注入量比第二次的注入量多，能够在热处理时使质子扩散到靠近半导体基板90的正面侧的位置。由此，正面侧的缺陷也能够得到恢复。
在本例中，由于使质子扩散到靠近半导体基板90的正面侧的位置而使缺陷恢复，所以优选尽可能地将第一次的质子注入到靠近半导体基板90的正面侧的位置。然而，若将质子注入到靠近正面侧的位置，则必须以相应大的加速电压进行质子的注入。随着加速电压的变大，由质子的注入带来的半导体基板90的缺陷也增加。另外，随着加速电压的变大，由于注入量在深度方向存在不均，所以难以在一定深度控制注入量。因此，靠近半导体基板90的最正面侧的第一次注入的质子，例如位于从沟道形成区朝向背面侧距离20μm～70μm的适当的位置即可。
接着，将注入条件改变为加速电压达0.82MeV、每单位面积的注入量达1E+13/cm2，相比第二次质子注入的阶段在更靠近半导体基板90的背面侧的位置，进行第三次质子注入。最后，将注入条件改变为加速电压达0.40MeV、每单位面积的注入量达3E+14/cm2，相比第三次质子注入的阶段在更靠近半导体基板90的背面侧的位置，进行第四次质子注入。这样，在半导体基板的背面侧与正面侧之间的不同深度的位置进行质子注入。
在质子注入阶段中，若将第一次、第二次、第三次以及第四次的质子注入中的每单位面积的注入量分别设为N1、N2、N3以及N4，则满足N2＜N1～N3＜N4的关系即可。在本说明书中，N1～N3是指N1和N3大致相同。在本例中，N1＝N3＝1E+13/cm2。在质子注入结束之后，对半导体基板90进行热处理，形成作为n型杂质区的第一杂质区～第四杂质区。由此，完成FS层50。
应予说明，第一次质子注入中的每单位面积的注入量N1比N2大，并且注入量可以为1E+12/cm2以上且1E+14/cm2以下，进一步可以为3E+12/cm2以上且3E+13/cm2以下。另外，第一杂质区51a可以在向栅极关断的IGBT施加的电压下完全地耗尽。为此，从第二导电型区34到第一杂质区51a与第二杂质区51b之间的边界的载流子浓度的积分值可以至少比临界积分浓度nc小，优选为比临界积分浓度nc的一半小。
在此，临界积分浓度nC如下所述。雪崩击穿所产生的电场强度的值被称为临界电场强度(Critical Electric Field Strength)。雪崩击穿取决于半导体的构成元素、掺杂到半导体中的杂质、以及杂质的浓度。若将施主浓度设为ND，将临界电场强度设为EC，使用硅(Si)中的碰撞电离系数进行离子积分，则临界电场强度EC由数式1表示。
[数式1]
Ec＝4010·(ND)1/8
由数式1可知，如果施主浓度ND确定，则临界电场强度EC也确定。另外，泊松式在仅考虑一维方向(设为x方向)的情况下，由数式2表示。
[数式2]
dE/dx＝(q/εrε0)(p-n+ND-NA)
在此，q为基本电荷(1.062×1015[C])，ε0为真空介电常数(8.854×10-14[F/cm])，εr为物质相对介电常数。在使用硅的情况下，εr＝11.9。p为空穴浓度，n为电子浓度，NA为受主浓度。由于考虑到单边突变结且仅为n型层，所以不存在受体(NA＝0)。进一步，若假设为不存在空穴和电子的完全耗尽的(n＝p＝0)耗尽层，则以深度x对数式2进行积分，得到数式3。
[数式3]
E＝(q/εrε0)∫NDdx
将pn结的位置设为原点0，将n型层中与pn结相反一侧的位置中的耗尽层的端部的位置设为x0。并且，以0～x0对整个耗尽层进行积分，数式3的E成为电场强度分布的最大值。若将其设为Em，则Em由数式4表示。
[数式4]
Em＝(q/εrε0)∫0 X0NDdx
若电场强度分布的最大值Em到达临界电场强度Ec，则数式4由数式5表示。
[数式5]
Ec(εrε0/q)＝∫0 X0NDdx
数式5的两边均是恒定值。由于数式5的右边为n型层中完全耗尽的范围，所以根据本说明书中记载的定义，表示为临界积分浓度nc。由此得到以下的数式6。数式6表示临界积分浓度nc与临界电场强度Ec的对应关系。这样，临界积分浓度nc成为与临界电场强度Ec对应的恒定值。
[数式6]
Ec(εrε0/q)＝nc
应予说明，在上述计算中，假设施主浓度ND在n型层的x方向的浓度分布是一样的。由于临界电场强度Ec取决于n型层的施主浓度ND(数式5)，因而临界积分浓度nc也取决于n型层的施主浓度ND。若施主浓度ND为1×1013(/cm3)～1×1015(/cm3)的范围，则临界积分浓度nc为1.1×1012(/cm3)～2.0×1012(/cm2)。鉴于施主浓度具有跨及几个数量级的浓度范围，因而临界积分浓度nc也可视为几乎恒定。
例如，在实施方式的半导体装置100的额定电压为1200V的例子中，若将基区层40的施主浓度ND设为6.1×1013(/cm3)，则根据数式6，可以将临界积分浓度nc评价为约1.4×1012(/cm2)。另外，在额定电压为600V的例子中，若将基区层40的施主浓度ND设为1.4×1014(/cm3)，则根据数式6，可以将临界积分浓度nc评价为约1.55×1012(/cm2)。另外，上述的临界总杂质量的说法并不限于使用硅的情况，还可应用于使用碳化硅(SiC)、氮化镓(GaN)、金刚石、氧化镓(Ga2O3)等的宽禁带半导体。即，为了导出数式1，碰撞电离系数、数式2中的相对介电常数使用各物质的相应值即可。
图3是表示对注入了质子的半导体基板90进行热处理之后的第一杂质区～第四杂质区中的载流子浓度分布的图。第一杂质区51a是具有含预先决定的载流子浓度的杂质区。在本例中，第一杂质区51a具有0.8E+15/cm3的载流子浓度。第二杂质区51b的载流子浓度比第一杂质区51a中的所述预先决定的载流子浓度低。在本例中，第二杂质区51b具有0.7E+15/cm3的载流子浓度。第三杂质区51c具有1.0E+15/cm3的载流子浓度，第四杂质区51d具有超过5.0E+15/cm3的载流子浓度。这样，FS层50的n型杂质区在半导体基板90的不同深度的位置具有载流子浓度的多个峰。
图4是表示与本例的FS层50的有无对应的漏电流的比较结果的图。横轴表示施加到IGBT的反向电压的大小(V)，纵轴表示漏电流(A)。无质子注入表示利用除质子注入以外的方法制成FS层。例如，通过注入磷而形成FS层的情况。另一方面，有质子注入是表示如本例所示通过质子注入形成FS层50。与利用除质子注入以外的方法制成FS层的情况相比，具有本例的FS层50的情况漏电流小。认为其原因是在热处理时使质子扩散到靠近半导体基板90的正面侧的位置而使缺陷恢复，其结果使栅极阈值增加恢复到规定值。
图5a～图5f是表示半导体装置100的制造阶段的图。首先，如图5a所示，将MOS栅结构30形成于半导体基板90的正面侧。形成MOS栅结构30的阶段包括在半导体基板90的正面侧形成作为阻挡金属部的第一金属层20和第一金属的氮化物层22的阶段。在该阶段中，形成第一导电型区32、第二导电型区34和栅电极36以及栅极绝缘膜38时产生的缺陷等存在于沟道形成区。
之后，如图5b所示，对半导体基板90的背面侧进行研磨使其变薄。再之后，如图5c所示，从半导体基板90的背面侧注入质子，形成杂质区。如之前的图2所示那样，质子的注入分成第一次至第四次进行。从第一次至第四次依次减弱加速电压而调节质子注入深度，使得第一次质子注入位置最靠近半导体基板90的正面侧，第四次质子注入位置最靠近半导体基板90的背面侧。若将第一次至第四次的每单位面积的注入量分别设为N1、N2、N3以及N4，则满足N2＜N1～N3＜N4的关系。
之后，如图5d所示，在300℃至500℃的温度下对半导体基板90进行30分钟至10小时的热处理。在热处理阶段中，注入的质子的一部分在FS层50中形成VOH缺陷。另外，其他一部分在半导体基板90内扩散到达正面侧，恢复基区层40中的剩余缺陷和沟道形成区的缺陷。应予说明，由于认为质子也到达栅极绝缘膜38与半导体基板90的第二导电型区34之间的界面，所以氢原子可以不存在于该界面。即，第二导电型区34的硅的悬挂键可以通过质子终结，形成硅‐氢键。由此，能够减少施加反向电压时的漏电流，并且能够减少栅极阈值电压(Vth)的偏差。
图5e是示意性地表示半导体基板90的缺陷得到恢复的情况的图。之后，如图5f所示，在半导体基板90的背面侧注入磷等杂质而形成作为p+型硅层的集电极层60。接着，通过进行铝的蒸镀或者溅射，在集电极层60的背面侧形成集电极70。
根据本实施例，在形成阻挡金属部之后，从半导体基板90的背面侧进行质子注入，之后通过热处理使质子扩散到正面侧，因而一次性进行用于缺陷恢复的热处理即可。即，没有必要从半导体基板90的正面侧和背面侧进行两次质子注入和热处理。因此，与进行两次质子注入和热处理的情况相比较，能够减少热处理的工序次数而抑制制造成本。
图6a～图6c是表示半导体装置200的制造阶段的图。本例在如下两方面与半导体装置100不同，即，不是以与第一金属层20和第二金属层24两者同时直接接触的方式设置第一金属的氮化物层22；在第一金属的氮化物层22和第二金属层24之间具有插件28。其他均与半导体装置100的例子相同。本例的插件28可以为由钨构成的插件28。插件28将第一金属的氮化物层22和第二金属层24连接。图6a相当于图5c，是表示从半导体基板90的背面侧进行质子注入的阶段的图。图6b相当于图5d，是表示对半导体基板90进行热处理的阶段的图。图6c相当于图5e和图5f，是表示在使半导体基板90的缺陷恢复之后，在半导体基板90的背面侧形成集电极层60和集电极70的阶段的图。
在本例中，在形成MOS栅结构30之后从半导体基板90的背面侧如图2所示进行质子注入。由此，在应用了阻挡金属部的半导体装置200中，能够减少施加反向电压时的漏电流，能够减少栅极阈值电压(Vth)的偏差。另外，与经两次进行质子注入和热处理的情况相比较，能够减少热处理的工序次数并抑制制造成本。应予说明，本说明书中记载的技术的应用不限于IGBT。例如，也能够应用于在形成阻挡金属部之后限定使用期限的元件。
图7是表示半导体基板90中的氢的分布的图。在图7中，示出半导体装置100的截面和本实施方式的净掺杂浓度分布。应予说明，半导体装置200也可以具有相同的净掺杂浓度分布和氢浓度分布。
注入氢的深度可以由最深的质子的射程决定。另一方面，通过质子注入后的热处理，如图7所示，比最深的质子的射程更深地向正面侧扩散数十μm。将该扩散的区域设为氢扩散区nn95。该氢扩散区nn优选以充足的氢浓度设置到沟道形成区。例如，沟道形成区中的氢的浓度可以为1E+14cm-3以上，且形成朝向半导体基板90的背面侧氢的浓度增加的分布。
以上，使用实施方式对本发明进行了说明，但本发明的技术范围并不限于上述实施方式中记载的范围。可以对上述实施方式进行多种变更或者改进对本领域技术人员是显而易见的。根据权利要求中记载的内容，进行了多种变更或者改进的实施方式可包含在本发明的技术范围内是显而易见的。
在权利要求、说明书以及附图中示出的装置、系统、程序，以及方法中的动作、顺序、步骤以及阶段等各处理的执行顺序没有特别明示为“在之前”，“首先”等，并且只要不是在后的处理需要使用之前的处理的结果，就可以以任意的顺序实现。关于权利要求、说明书以及附图中的动作流程，为了方便，即使使用“首先，”、“接下来，”等进行说明，也并不是指必须以该顺序实施。

Claims (11)

1.一种半导体装置，其特征在于，具备：
半导体基板，在其背面侧具有包含质子的n型杂质区；
p型杂质区，设置于所述半导体基板的正面侧；
n型第二杂质区，在所述半导体基板的所述正面侧，设置于所述p型杂质区的正面侧；
基区，位于所述p型杂质区与所述n型杂质区之间，且具有n型杂质；
沟槽，设置于所述半导体基板的所述正面侧，与所述n型第二杂质区、所述p型杂质区以及所述基区接触；
栅极绝缘膜，设置于所述沟槽的内壁；
栅电极，设置于所述栅极绝缘膜的内侧；
阻挡金属部，在所述半导体基板的所述正面侧对质子具有阻挡效果；以及
层间绝缘膜，将所述栅电极与所述阻挡金属部绝缘，
所述n型杂质区具有：
第一杂质区，具有预先决定的峰值载流子浓度；
第二杂质区，峰值载流子浓度比所述预先决定的峰值载流子浓度低，且设置于比所述第一杂质区更靠近背面侧的位置，
第三杂质区，设置于比所述第二杂质区更靠近所述背面侧的位置，且峰值载流子浓度比所述预先决定的峰值载流子浓度高；以及
第四杂质区，设置于比所述第三杂质区更靠近所述背面侧的位置，且峰值载流子浓度比所述第三杂质区的所述峰值载流子浓度高，
在所述栅极绝缘膜与所述半导体基板之间的界面存在氢原子。
2.根据权利要求1所述的半导体装置，其中，
所述n型杂质区在所述背面侧与所述正面侧之间的不同深度的位置具有载流子浓度的多个峰。
3.根据权利要求1所述的半导体装置，其中，
从所述p型杂质区到所述第一杂质区的载流子浓度的积分值比临界积分浓度小。
4.根据权利要求3所述的半导体装置，其中，
在所述栅极绝缘膜与所述p型杂质区之间的界面具有硅-氢键。
5.根据权利要求3所述的半导体装置，其中，
从所述p型杂质区的沟道形成区到所述第一杂质区的长度为20μm以上且70μm以下。
6.根据权利要求3所述的半导体装置，其中，
所述半导体基板从所述第一杂质区到所述p型杂质区的沟道形成区具有1E+14cm-3以上的氢浓度。
7.根据权利要求3～6中任一项所述的半导体装置，其中，
所述半导体基板的沟道形成区具有朝向所述第一杂质区增加的氢浓度。
8.一种半导体装置的制造方法，其特征在于，具备：
在半导体基板的正面侧形成p型杂质区的阶段；
在所述半导体基板的所述正面侧形成设置于所述p型杂质区的正面侧的n型第二杂质区的阶段；
在所述半导体基板的所述正面侧形成与所述n型第二杂质区、所述p型杂质区以及基区接触的沟槽的阶段；
在所述沟槽的内壁形成栅极绝缘膜的阶段；
在所述栅极绝缘膜的内侧形成栅电极的阶段；
形成层间绝缘膜的阶段；
在所述半导体基板的所述正面侧形成对质子具有阻挡效果并通过所述层间绝缘膜与所述栅电极绝缘的阻挡金属部的阶段；
从所述半导体基板的背面侧注入质子，形成杂质区的阶段；以及
对已注入了质子的所述半导体基板进行热处理的阶段，
形成所述杂质区的阶段具有：
进行第一次质子注入的阶段，形成含预先决定的峰值载流子浓度的所述杂质区的第一部分；
进行第二次质子注入的阶段，改变注入条件以使峰值载流子浓度比所述预先决定的峰值载流子浓度低，并且在比通过所述第一次质子注入而形成的所述杂质区的所述第一部分更靠近所述半导体基板的所述背面侧的位置形成所述杂质区的第二部分；
进行第三次质子注入的阶段，在比通过所述第二次质子注入而形成的所述杂质区的所述第二部分更靠近所述半导体基板的所述背面侧的位置，形成具有比所述预先决定的峰值载流子浓度高的峰值载流子浓度的所述杂质区的第三部分；以及
进行第四次质子注入的阶段，在比通过所述第三次质子注入而形成的所述杂质区的所述第三部分更靠近所述半导体基板的所述背面侧的位置，形成具有比所述杂质区的所述第三部分的所述峰值载流子浓度高的峰值载流子浓度的所述杂质区的第四部分，
在所述栅极绝缘膜与所述半导体基板之间的界面存在氢原子，
若将所述第一次、所述第二次、所述第三次以及所述第四次质子注入中的每单位面积的注入量分别设为N1、N2、N3以及N4，则满足N2＜N1～N3＜N4的关系，其中，N1～N3是指N1和N3大致相同。
9.根据权利要求8所述的半导体装置的制造方法，其中，
形成所述杂质区的阶段还包括改变包含加速电压和每单位面积的注入量的注入条件，通过包含所述第一次质子注入和所述第二次质子注入的多次注入对不同深度的位置注入质子的阶段。
10.根据权利要求8所述的半导体装置的制造方法，其中，
在形成所述阻挡金属部的阶段之后，执行进行所述第一次质子注入的阶段。
11.根据权利要求8所述的半导体装置的制造方法，其中，
在从所述半导体基板的所述背面侧注入质子而形成所述杂质区的阶段之后，具有对已注入了质子的所述半导体基板进行热处理的阶段。
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