CN105938840A - 一种阵列基板及显示面板 - Google Patents
一种阵列基板及显示面板 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 239000004973 liquid crystal related substance Substances 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000000994 depressogenic effect Effects 0.000 claims 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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Abstract
本发明公开了一种阵列基板及显示面板,其中阵列基板包括基板;设置在基板上的图案化的中间层;以及设置在图案化的中间层上的无图案化的像素电极层,像素电极层对应图案化的中间层形成凹陷区和凸出区。采用本发明的阵列基板可以有效的改善暗纹的问题。
Description
技术领域
本发明涉及显示技术领域,特别是涉及一种阵列基板及显示面板。
背景技术
当前显示器的发展迅速,按照其显示原理可分为液晶显示器、等离子显示器、有机电致发光显示器等。
在液晶显示器的各种显示模式中,垂直排列(VA)显示模式因具有良好的视角而受到市场欢迎,一般来说VA显示模式采用多畴设计,而当前实现多畴设计有两种模式:一是像素电极的裂缝形成侧向电场的PVA模式;而是像素单元中的凸起使得液晶分子形成多畴排列的MVA模式,然而在两种模式中,液晶显示器都存在暗纹或显示不佳的问题。
发明内容
本发明的目的在于提供一种阵列基板及显示面板,以解决使用现有阵列基板的显示面板上出现暗纹的问题。
为解决上述问题,本发明提出一种阵列基板,该阵列基板包括:基板;设置在基板上的图案化的中间层;以及设置在图案化的中间层上的无图案化的像素电极层,像素电极层对应图案化的中间层形成凹陷区和凸出区。
其中,图案化的中间层为沟槽结构或条状结构。
其中,沟槽结构包括凹槽和凸起,像素电极层对应凹槽形成凹陷区,像素电极层对应凸起形成凸出区。
其中,条状结构包括条块和条块之间的狭缝,像素电极层对应条块形成凸出区,像素电极层对应狭缝形成凹陷区。
其中,图案化的中间层为鱼骨状图案。
其中,图案化的中间层为有源层。
其中,有源层与像素电极层之间设置有钝化层。
其中,有源层的材料为非晶硅或铟镓锌氧化物。
为解决上述技术问题,本发明还提出一种显示面板,该显示面板包括上述阵列基板。
其中,显示面板进一步包括对应阵列基板设置的彩色滤光片基板,以及设置在阵列基板和彩色滤光片基板之间的液晶层。
本发明阵列基板包括:基板,设置在基板上的图案化的中间层,以及设置在图案化的中间层上的无图案化的像素电极层,像素电极层对应图案化的中间层形成凹陷区和凸出区。本发明阵列基板中的像素电极层为无图案化的,即块状像素电极层,不存在狭缝,使用该阵列基板的显示面板不会出现暗纹、显示亮度和对比度不佳的问题。
附图说明
图1是本发明阵列基板第一实施方式的结构示意图;
图2是本发明阵列基板第二实施方式的结构示意图;
图3是图2所示阵列基板第二实施方式像素电极层的俯视图;
图4是图2所示阵列基板第二实施方式的制作流程图;
图5是本发明显示面板一实施方式的结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对发明所提供的一种阵列基板及显示面板做进一步详细描述。
参阅图1,图1是本发明阵列基板第一实施方式的结构示意图,本实施方式阵列基板100包括基板11、中间层12、像素电极层13。
中间层12为图案化的中间层12,即形成中间层12的过程包括能够实现图案化的刻蚀工艺。无图案化的像素电极层13则形成在中间层12上,像素电极层13对应图案化的中间层12形成凸出区131和凹陷区132。
具体来说图案化的中间层12可以为条状结构(如图1(A))或沟槽结构(如图1(B))。
条状结构的中间层12包括条块121和条块121之间形成的狭缝122,即在刻蚀工艺中,将狭缝122处的中间层12完全去除。对于此类中间层12,像素电极层13上对应条块121形成凸出区131,对应于狭缝122形成凹陷区132。
沟槽结构的中间层12则包括凸起121和凹槽122,凹槽122处还保留有较薄的中间层12,即在刻蚀工艺中,只是将凹槽122处的中间层12部分去除。对于该类中间层12,像素电极层13上对应凸起121形成凸出区131,对应凹槽122形成凹陷区132。
无论是对于条状结构或沟槽结构的中间层12,像素电极层13均在其上形成具有凸出区131和凹陷区132的块状电极,保证使用该阵列基板100的显示面板中的液晶均能发生翻转,显示面板不会出现暗纹。
具体到应用中,中间层12与像素电极层13之间还可以设置别的层,像素电极层13可以直接沉积在中间层12上,也可以不直接沉积在中间层12上。
本实施方式阵列基板包括基板,设置在基板上的图案化的中间层,以及设置在图案化的中间层上的无图案化的像素电极层,像素电极层对应图案化的中间层形成凹陷区和凸出区。其中像素电极层为无图案化的,即为块状像素电极层,不存在狭缝,使用该阵列基板的显示面板不会出现暗纹、显示亮度和对比度不佳的问题。
请参阅图2,图2是本发明阵列基板第二实施方式的结构示意图,本实施方式阵列基板200包括玻璃基板21,以及在玻璃基板21上依次形成的栅极22、栅极绝缘层23、有源层24、阻挡层25、源/漏极26、钝化层27和像素电极层28。
其中,有源层24为本发明中图案化的中间层,像素电极层28设置在有源层24上方,对应于有源层24形成有凸出区281和凹陷区282,本实施方式中的有源层24为条状结构,当然也可为沟槽结构,具体来说图案化的有源层24为鱼骨状图案。相应的像素电极层28的凸出区281和凹陷区282也构成鱼骨状图案的纹路,可参阅图3,图3是图2所示阵列基板第二实施方式像素电极层的俯视图。
对于本实施方式阵列基板200,其制造过程可参阅图4,图4是图2所示阵列基板第二实施方式的制作流程图,该制造过程包括以下步骤。
S401:在玻璃基板上形成栅极和栅极绝缘层。
采用物理气相沉积及湿法刻蚀工艺在玻璃基板21上形成栅极22,然后采用化学气相沉积及干法刻蚀工艺形成栅极绝缘层23。
S402:栅极绝缘层上形成图案化的有源层。
在栅极绝缘层23上形成图案化的有源层24,主要是在阵列基板对应的显示区域形成该有源层24,以使得对应该图案化有源层24的像素电极层28具有凸出区281和凹陷区282,该图案化的有源层24为条状结构的鱼骨状图案,形成有源层24的材料可以为非晶硅或铟镓锌氧化物(IGZO)。
S403:形成具有开口的阻挡层。
在形成图案化的有源层24后,采用化学气相沉积及干法刻蚀工艺形成阻挡层25,该阻挡层25为刻蚀阻挡层25,即在后续刻蚀工艺中起到阻挡作用,避免已形成的有源层24又被刻蚀。由于后续形成的源/漏极26需要与有源层24电性连接,因此在阻挡层25上还形成两开口,以分别供源极和漏极与有源层24接触。
S404:阻挡层上形成源/漏极,源/漏极均通过阻挡层的开口与有源层电性连接。
源极和漏极为同一种金属,因此在本步骤S404中同时形成,具体来说,首先采用物理气相沉积一金属层,然后通过湿法刻蚀工艺对该金属层进行图案化处理,以形成源极和漏极。在沉积金属层时,由于阻挡层25上具有开口,因此金属层可沉积于开口中,以实现与有源层24的电性连接。
S405:形成具有开口的钝化层。
为延缓金属的源/漏极26的氧化,继续形成一钝化层27,由于后续形成的像素电极层28需要与漏极电性连接,因此在钝化层27上还形成一开口,使得像素电极层28能够通过该开口与漏极接触。具体来说钝化层的形成采用化学气相沉积和干法刻蚀工艺。
S406:形成像素电极层,像素电极层通过钝化层的开口与漏极电性连接。
本实施方式中像素电极层28由铟锡氧化物(ITO)采用物理气相沉积法制得,ITO能够沉积于钝化层27的开口中,实现与漏极的电性连接。
由于本实施方式中形成的有源层24为条状结构,因此形成在其上方的阻挡层25、钝化层27以及像素电极层28均有凸出区和凹陷区,对于像素电极层28,对应于有源层24的条块,其形成凸出区281,对应于有源层24的狭缝,其形成有凹陷区282。
本实施方式中所形成的像素电极层28为具有凸出区281和凹陷区282的块状像素电极层,不存在狭缝,因此,使用该阵列基板200的显示面板不会出现暗纹、显示亮度和对比度不佳的问题。
请参阅图5,图5是本发明显示面板一实施方式的结构示意图,本实施方式显示面板500包括阵列基板51、彩色滤光片基板52以及液晶层53。
液晶层53位于阵列基板51和彩色滤光片基板52之间,本实施方式显示面板500中的阵列基板51与上述阵列基板200类似,具体不再赘述。
本实施方式的液晶层53在阵列基板51和彩色滤光片基板52之间均能得到有效翻转,显示面板500不会出现暗纹、显示亮度和对比度不佳的问题。
以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。
Claims (10)
1.一种阵列基板,其特征在于,所述阵列基板包括:
基板;
设置在所述基板上的图案化的中间层;
以及设置在所述图案化的中间层上的无图案化的像素电极层,所述像素电极层对应所述图案化的中间层形成凹陷区和凸出区。
2.根据权利要求1所述的阵列基板,其特征在于,所述图案化的中间层为沟槽结构或条状结构。
3.根据权利要求2所述的阵列基板,其特征在于,所述沟槽结构包括凹槽和凸起,所述像素电极层对应所述凹槽形成所述凹陷区,所述像素电极层对应所述凸起形成所述凸出区。
4.根据权利要求2所述的阵列基板,其特征在于,所述条状结构包括条块和条块之间的狭缝,所述像素电极层对应所述条块形成所述凸出区,所述像素电极层对应所述狭缝形成所述凹陷区。
5.根据权利要求2所述的阵列基板,其特征在于,所述图案化的中间层为鱼骨状图案。
6.根据权利要求1所述的阵列基板,其特征在于,所述图案化的中间层为有源层。
7.根据权利要求6所述的阵列基板,其特征在于,所述有源层与所述像素电极层之间设置有钝化层。
8.根据权利要求6所述的阵列基板,其特征在于,所述有源层的材料为非晶硅或铟镓锌氧化物。
9.一种显示面板,其特征在于,所述显示面板包括权利要求1-8中任一项所述的阵列基板。
10.根据权利要求9所述的显示面板,其特征在于,所述显示面板进一步包括对应所述阵列基板设置的彩色滤光片基板,以及设置在所述阵列基板和所述彩色滤光片基板之间的液晶层。
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