CN105897015A - PSR constant-current constant-voltage AC/DC chip - Google Patents
PSR constant-current constant-voltage AC/DC chip Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
- H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
- H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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Abstract
本发明涉及一种PSR恒流恒压AC/DC芯片,包括控制芯片和PSR反激式变压器,控制芯片包括软件驱动模块、恒流环路模块、恒压环路模块、软驱动模块,PSR反激式变压器通过反馈电路模块与恒流环路模块相连接,SR反激式变压器通过采样电路模块与恒压环路模块相连接,恒流环路模块和恒压环路模块的输出端分别与软驱动模块相连接。本发明与现有技术相比,提出了一种高精度的恒流恒压芯片设计,使输出电压和输出电流的精度得到大大提高。同时系统拥有较高的整机效率和稳定,在芯片内模块的协调配合下使该芯片具备较高的工作性能。
The invention relates to a PSR constant current and constant voltage AC/DC chip, which includes a control chip and a PSR flyback transformer. The control chip includes a software drive module, a constant current loop module, a constant voltage loop module, a soft drive module, and a PSR flyback The exciting transformer is connected to the constant current loop module through the feedback circuit module, and the SR flyback transformer is connected to the constant voltage loop module through the sampling circuit module. The output terminals of the constant current loop module and the constant voltage loop module are respectively connected to The soft drive module is connected. Compared with the prior art, the present invention proposes a high-precision constant-current constant-voltage chip design, which greatly improves the precision of output voltage and output current. At the same time, the system has high overall efficiency and stability, and the coordination and cooperation of the modules in the chip make the chip have high working performance.
Description
技术领域technical field
本发明涉及恒流恒压控制芯片领域,具体涉及一种PSR恒流恒压AC/DC芯片。The invention relates to the field of constant current and constant voltage control chips, in particular to a PSR constant current and constant voltage AC/DC chip.
背景技术Background technique
在当今社会中,人们的日常生活和工作中开始越来越多的使用到电子设备。而电源管理芯片的功能相当于电子设备的“心脏”,它为电子设备起着对电能的转换,分配,安全检测和高效工作的管理功能。发展至今,开关电源已广泛应用在各种电子通信设备中,已经逐渐成为了现代电子信息产业高速发展过程中不可或缺的一种关键核心技术。随着半导体制造工艺技术的发展及集成电路工艺水平的不断改进,开关电源技术朝着高集成度、高效率、高可靠性、低噪声和抗电磁干扰等传统发展方向不断继续发展,传统的大电流高速充电方案具备不可避免的缺点:兼容性较差,充电器成本高,体积大。快速充电方案的提出对电源管理芯片的设计提出了新的挑战,同时对开关电源的发展具有重要的意义。In today's society, more and more electronic devices are used in people's daily life and work. The function of the power management chip is equivalent to the "heart" of electronic equipment, which plays a role in the management of electric energy conversion, distribution, safety detection and efficient work for electronic equipment. Up to now, switching power supply has been widely used in various electronic communication equipment, and has gradually become an indispensable key core technology in the rapid development of modern electronic information industry. With the development of semiconductor manufacturing technology and the continuous improvement of integrated circuit technology, switching power supply technology continues to develop in the traditional direction of high integration, high efficiency, high reliability, low noise and anti-electromagnetic interference. The current high-speed charging solution has inevitable disadvantages: poor compatibility, high charger cost, and large volume. The proposal of the fast charging scheme poses new challenges to the design of power management chips, and at the same time, it is of great significance to the development of switching power supplies.
发明内容Contents of the invention
本发明的目的就是提供一种PSR恒流恒压AC/DC芯片,其可有效的解决上述问题,精确控制输出的恒流和恒压精度,同时保证了系统的简化和高效。The purpose of the present invention is to provide a PSR constant current and constant voltage AC/DC chip, which can effectively solve the above problems, precisely control the output constant current and constant voltage accuracy, and at the same time ensure the simplification and high efficiency of the system.
为实现上述目的,本发明采用了以下技术方案:To achieve the above object, the present invention adopts the following technical solutions:
一种PSR恒流恒压AC/DC芯片,其特征在于:包括控制芯片和PSR反激式变压器,控制芯片包括软件驱动模块、恒流环路模块、恒压环路模块、软驱动模块,PSR反激式变压器通过反馈电路模块与恒流环路模块相连接,SR反激式变压器通过采样电路模块与恒压环路模块相连接,恒流环路模块和恒压环路模块的输出端分别与软驱动模块相连接。芯片内还包括新型的采样控制模块和软驱动模块,以及过压欠压、过温保护和振荡器等模块。A PSR constant-current constant-voltage AC/DC chip is characterized in that: it includes a control chip and a PSR flyback transformer, and the control chip includes a software drive module, a constant-current loop module, a constant-voltage loop module, a soft drive module, and a PSR The flyback transformer is connected to the constant current loop module through the feedback circuit module, and the SR flyback transformer is connected to the constant voltage loop module through the sampling circuit module. The output terminals of the constant current loop module and the constant voltage loop module are respectively Connect with soft drive module. The chip also includes a new sampling control module and soft drive module, as well as overvoltage and undervoltage, overtemperature protection and oscillator modules.
具体的方案为:PSR反激式变压器包括由绕组NAUX、原边绕组NP、次边绕组NS组成的辅助线圈绕组以及二极管D0、D1;二极管D1的负极分两路分别连接电容C0的一端和电阻R3一端,二极管D1的正极和原边绕组NP一端均接入功率晶体管M0的漏极,电容C0、电阻R3以及原边绕组NP的另一端均与吸收电路相连接,功率晶体管M0的栅极连接控制芯片的G引脚,功率晶体管M0的源极分两路分别连接控制芯片的CS引脚和电阻RS的一端,绕组NAUX一端连接电阻R1的一端,电阻R1的另一端与电阻R2的一端相连接,电阻R1、R2之间的接点接入控制芯片的FB引脚,电阻RS、电阻R2、绕组NAUX的另一端均接入外接信号;次边绕组NS的一端连接二极管D0的正极,二极管D0负极分两路分别连接电容C1的一端、电阻R0的一端,电容C1、电阻R0的另一端均与次边绕组NS的另一端相连接。其中:CS引脚用于采集外电路信息反馈给限流比较器决定功率管的关断,FB引脚用于向控制芯片反馈经过电阻分压后的表示输出电压变化的信息,G引脚用于控制外部的功率管M0。The specific scheme is: PSR flyback transformer includes auxiliary coil winding composed of winding NAUX, primary winding NP and secondary winding NS, and diodes D0 and D1; the negative pole of diode D1 is divided into two ways to connect one end of capacitor C0 and resistor One end of R3, the anode of the diode D1 and one end of the primary winding NP are all connected to the drain of the power transistor M0, the capacitor C0, the resistor R3 and the other end of the primary winding NP are connected to the absorption circuit, and the gate of the power transistor M0 is connected to The G pin of the control chip and the source of the power transistor M0 are connected in two ways to the CS pin of the control chip and one end of the resistor RS, one end of the winding NAUX is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the resistor R2. Connection, the contact between the resistors R1 and R2 is connected to the FB pin of the control chip, the other end of the resistor RS, the resistor R2, and the winding NAUX are connected to the external signal; one end of the secondary winding NS is connected to the anode of the diode D0, and the diode D0 The negative electrode is divided into two circuits and connected to one end of the capacitor C1 and one end of the resistor R0 respectively, and the other ends of the capacitor C1 and the resistor R0 are both connected to the other end of the secondary winding NS. Among them: the CS pin is used to collect external circuit information and feed it back to the current-limiting comparator to determine the shutdown of the power tube; the FB pin is used to feed back the information indicating the output voltage change after the resistor divider to the control chip; It is used to control the external power tube M0.
采样电路模块包括晶体管Vbias、运算放大器CA,VDD连接晶体管Vbias的源极,晶体管Vbias的漏极连接晶体管M9的源极,运算放大器CA的同相端分别连接晶体管M9、M1、M2的漏极,运算放大器CA的反相端分别连接晶体管M5、M6、M7、M8的漏极以及电容C2的一端,运算放大器CA的输出端连接采样信息输出端SH,晶体管M1的源极分三路分别连接晶体管M3的漏极、电容C0的一端、晶体管M8的源极,晶体管M2的源极分三路分别连接晶体管M7的源极、晶体管M4的漏极以及电容C1的一端,晶体管M3、M4、M5、M6的源极以及电容C0、C1、C2的一端均与连接点A相连接。The sampling circuit module includes a transistor Vbias and an operational amplifier CA. VDD is connected to the source of the transistor Vbias, the drain of the transistor Vbias is connected to the source of the transistor M9, and the non-inverting terminal of the operational amplifier CA is respectively connected to the drains of the transistors M9, M1, and M2. The inverting terminal of the amplifier CA is respectively connected to the drains of the transistors M5, M6, M7, M8 and one terminal of the capacitor C2, the output terminal of the operational amplifier CA is connected to the sampling information output terminal SH, and the source of the transistor M1 is divided into three ways and respectively connected to the transistor M3 The drain of the transistor, one end of the capacitor C0, the source of the transistor M8, and the source of the transistor M2 are connected in three ways to the source of the transistor M7, the drain of the transistor M4, and one end of the capacitor C1, and the transistors M3, M4, M5, M6 The source of , and one end of the capacitors C0, C1, C2 are all connected to the connection point A.
软驱动电路模块包括电平转换模块、触发器,电平转换模块的两个驱动输出端分别连接触发器输入端的R、S引脚,触发器输出端的Q引脚分别连接晶体管M1、M3、M5的栅极,触发器输出端的QN引脚分别连接晶体管M6、M9的栅极以及反相器CD的正极,VDD连接晶体管M1的源极和晶体管M4的漏极,晶体管M1的漏极连接晶体管M2的源极,晶体管M2的漏极分三路分别连接晶体管M3、M5的漏极以及晶体管M4的栅极,晶体管M3、M5的源极接地,晶体管M4的源极分别连接晶体管M7、M8的漏极以及电阻R1的一端,反相器CD的负极分别连接晶体管M7、M8的栅极以及晶体管M6的漏极,晶体管M6的源极接VDD,电阻R1的另一端连接电阻R2的一端,晶体管M3、M5、M7、M8的源极以及电阻R2的另一端均接地,晶体管M9、M10、M11、M12的源极接VDD,晶体管M12的栅漏短接,晶体管M12漏极分两路分别连接晶体管M19、M13的漏极,晶体管M11的栅漏短接,晶体管M11的漏极与晶体管M18的漏极相连,晶体管M11的栅极与晶体管M10的栅极相连,晶体管M10的漏极分四路分别连接晶体管M15、M16的漏极以及晶体管M14、M15的栅极,晶体管M9的漏极分两路分别连接晶体管M17的漏极和反相器CE的正极,反相器CE的负极连接晶体管M13的栅极,M13的源极连接晶体管M14的漏极,电流源DC的负极连接VDD,电流源DC的正极分四路分别连接晶体管M20的漏极以及晶体管M18、M19、M20的栅极,晶体管M17的栅极连接反馈电压VFB,晶体管M16的栅极连接电压UP,晶体管M20、M19、M18、M17、M16、M15、M14的源极均接地。The soft drive circuit module includes a level conversion module and a trigger. The two drive output terminals of the level conversion module are respectively connected to the R and S pins of the trigger input terminal, and the Q pins of the trigger output terminal are respectively connected to transistors M1, M3, and M5. The gate of the flip-flop output, the QN pin of the flip-flop output terminal is respectively connected to the gates of transistors M6 and M9 and the anode of the inverter CD, VDD is connected to the source of transistor M1 and the drain of transistor M4, and the drain of transistor M1 is connected to transistor M2 The source of the transistor M2 is divided into three ways to connect the drains of the transistors M3 and M5 and the gate of the transistor M4 respectively, the sources of the transistors M3 and M5 are grounded, and the source of the transistor M4 is respectively connected to the drains of the transistors M7 and M8 pole and one end of the resistor R1, the negative pole of the inverter CD is respectively connected to the gates of the transistors M7 and M8 and the drain of the transistor M6, the source of the transistor M6 is connected to VDD, the other end of the resistor R1 is connected to one end of the resistor R2, and the transistor M3 , M5, M7, M8 sources and the other end of resistor R2 are grounded, the sources of transistors M9, M10, M11, M12 are connected to VDD, the gate-drain of transistor M12 is short-circuited, and the drains of transistor M12 are connected to transistors in two ways The drains of M19 and M13, the gate-drain of the transistor M11 are short-circuited, the drain of the transistor M11 is connected to the drain of the transistor M18, the gate of the transistor M11 is connected to the gate of the transistor M10, and the drain of the transistor M10 is divided into four ways respectively The drains of the transistors M15 and M16 are connected to the gates of the transistors M14 and M15, the drain of the transistor M9 is divided into two paths and respectively connected to the drain of the transistor M17 and the positive pole of the inverter CE, and the negative pole of the inverter CE is connected to the gate of the transistor M13 The gate and the source of M13 are connected to the drain of the transistor M14, the negative pole of the current source DC is connected to VDD, and the positive pole of the current source DC is divided into four ways to respectively connect the drain of the transistor M20 and the gates of the transistors M18, M19, and M20, and the transistor M17 The gate of the transistor M16 is connected to the feedback voltage VFB, the gate of the transistor M16 is connected to the voltage UP, and the sources of the transistors M20, M19, M18, M17, M16, M15, and M14 are all grounded.
电平转换电路模块包括晶体管M1、M2、M3、M4和反相器CB,信号Driver-logic分别接入反相器CB的正极和晶体管M2的栅极,反相器CB的负极连接晶体管M3的栅极,VCC连接晶体管M1、M4的源极,晶体管M2、M3的源极接地,晶体管M1栅极、晶体管M3、M4的漏极均与DOWN端相连接,晶体管M4栅极、晶体管M1、M2的漏极均与UP端相连接,UP端、DOWN端为该电平转换电路模块的驱动信号输出端,信号Driver-logic为驱动控制信号。The level conversion circuit module includes transistors M1, M2, M3, M4 and an inverter CB. The signal Driver-logic is respectively connected to the positive pole of the inverter CB and the gate of the transistor M2, and the negative pole of the inverter CB is connected to the gate of the transistor M3. Gate, VCC is connected to the sources of transistors M1 and M4, the sources of transistors M2 and M3 are grounded, the gate of transistor M1, the drains of transistors M3 and M4 are connected to the DOWN terminal, the gate of transistor M4, the transistors M1 and M2 The drains of each are connected to the UP terminal, the UP terminal and the DOWN terminal are the drive signal output terminals of the level conversion circuit module, and the signal Driver-logic is the drive control signal.
该芯片通过检测退磁时间从而调节系统工作频率来实现一个新型的恒流控制方式,采样电路模块则是选取辅助绕组退磁时间区间的2/3点处作为反馈电压的采样点,进而通过误差放大器与设计阈值基准的误差放大,软驱动设计包括电平转换模块,软驱动模块和图腾柱结构的栅极驱动模块,用来减小开关动作EMI干扰和提高效率。The chip realizes a new type of constant current control mode by detecting the demagnetization time to adjust the system operating frequency. The sampling circuit module selects the 2/3 point of the demagnetization time interval of the auxiliary winding as the sampling point of the feedback voltage, and then passes the error amplifier and The error amplification of the threshold reference is designed, and the soft drive design includes a level conversion module, a soft drive module and a gate drive module with a totem pole structure, which are used to reduce switching EMI interference and improve efficiency.
本发明与现有技术相比,提出了一种高精度的恒流恒压芯片设计,使输出电压和输出电流的精度得到大大提高。同时系统拥有较高的整机效率和稳定,在芯片内模块的协调配合下使该芯片具备较高的工作性能。Compared with the prior art, the present invention proposes a high-precision constant current and constant voltage chip design, which greatly improves the precision of output voltage and output current. At the same time, the system has high overall efficiency and stability, and the coordination and cooperation of the modules in the chip make the chip have high working performance.
附图说明Description of drawings
图1为本发明的结构示意图;Fig. 1 is a structural representation of the present invention;
图2为反激式变压器的结构示意图;Fig. 2 is a structural schematic diagram of a flyback transformer;
图3为采样电路模块的电路结构原理图;Fig. 3 is the schematic diagram of the circuit structure of the sampling circuit module;
图4为电平转换电路模块的结构原理图;Fig. 4 is a schematic structural diagram of a level conversion circuit module;
图5为软驱动电路模块的结构原理图。Fig. 5 is a schematic diagram of the structure of the soft driving circuit module.
具体实施方式detailed description
为了使本发明的目的及优点更加清楚明白,以下结合实施例对本发明进行具体说明。应当理解,以下文字仅仅用以描述本发明的一种或几种具体的实施方式,并不对本发明具体请求的保护范围进行严格限定。In order to make the objects and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with examples. It should be understood that the following words are only used to describe one or several specific implementation modes of the present invention, and do not strictly limit the protection scope of the specific claims of the present invention.
本发明中未详细介绍的模块,本领域普通技术人员可以按照现有技术中芯片所采用的手段进行实施。For modules not described in detail in the present invention, those skilled in the art can implement them according to the means adopted by chips in the prior art.
本发明采取的技术方案如图1所示,一种高精度PSR恒流恒压AC/DC芯片,包括PSR反激式变压器、恒流环路模块、恒压环路模块、控制电路模块、采样保持电路模块和软驱动等模块。PSR反馈控制系统通过添加辅助线圈绕组,利用辅助线圈绕组的反馈电压和输出电压的关系对输出电压进行反馈采样,配合芯片中的恒流/恒压控制环路,使输出具有较高的精度,同时软驱动的慢速软启动过程保证了EMI,快速关断设计保证了工作效率。The technical scheme adopted by the present invention is shown in Figure 1, a high-precision PSR constant current constant voltage AC/DC chip, including a PSR flyback transformer, a constant current loop module, a constant voltage loop module, a control circuit module, a sampling Keep modules such as circuit modules and soft drives. The PSR feedback control system uses the relationship between the feedback voltage of the auxiliary coil winding and the output voltage to sample the output voltage by adding an auxiliary coil winding, and cooperates with the constant current/constant voltage control loop in the chip to make the output have higher accuracy. At the same time, the slow soft start process of the soft drive ensures EMI, and the fast shutdown design ensures work efficiency.
图2为反激式变压器,Controller为本发明所要设计的控制芯片,控制芯片有G、FB、CS三个引脚,CS引脚采集外电路信息从而反馈给限流比较器决定功率管的关断,FB引脚反馈给芯片的是经过电阻分压后的表示输出电压变化的信息,最后从G引脚控制外部的功率管M0,电容C0和电阻R3并联,一端接吸收电路,另一端接晶体管M0的漏极,原边绕组NP一端接吸收电路,另一端接晶体管M0的漏极,功率晶体管M0的栅极接控制芯片的G引脚,源极接控制芯片的CS接口,电阻RS一端接晶体管M0的源极,另一端接外接信号,次边绕组NS一端接二极管D0的正极,另一端接电容C0,D0负极接电容C0一端,电阻R0与电容C0并联,绕组NAUX一端接电阻RS的一端,另一端接电阻R1,R1的另一端接电阻R2,R2的另一端接电阻RS,R1和电阻R2的中间点与控制芯片的FB端相连接。Fig. 2 is a flyback transformer, Controller is the control chip to be designed in the present invention, the control chip has three pins of G, FB, and CS, and the CS pin collects external circuit information so as to feed back to the current-limiting comparator to determine the switching of the power tube The FB pin feeds back to the chip the information indicating the output voltage change after the resistor divider. Finally, the external power tube M0 is controlled from the G pin. The capacitor C0 and the resistor R3 are connected in parallel. The drain of the transistor M0, one end of the primary winding NP is connected to the absorbing circuit, the other end is connected to the drain of the transistor M0, the gate of the power transistor M0 is connected to the G pin of the control chip, the source is connected to the CS interface of the control chip, and one end of the resistor RS Connect the source of the transistor M0, the other end is connected to the external signal, one end of the secondary winding NS is connected to the positive pole of the diode D0, the other end is connected to the capacitor C0, the negative pole of D0 is connected to one end of the capacitor C0, the resistor R0 and the capacitor C0 are connected in parallel, and the winding NAUX is connected to the resistor RS The other end of R1 is connected to resistor R1, the other end of R1 is connected to resistor R2, the other end of R2 is connected to resistor RS, and the middle point between R1 and resistor R2 is connected to the FB end of the control chip.
图3为采样电路的结构图,SH为采样信息输出端,VDD接晶体管Vbias的源极,Vbias的漏极接晶体管M9的源极,晶体管M9的漏极连接运算放大器CA的同相端,晶体管M1的漏极连接晶体管M9的漏极,其源极连接晶体管M3的漏极和电容C0的一端,晶体管M3的源极连接电容C0的另一端,晶体管M2的漏极连接晶体管M9的漏极和CA的同相端,其源极连接晶体管M7的源极和晶体管M4的漏极,晶体管M4的源极连接电容C1和电容C0的一端,电容C1的另一端连接晶体管M4的漏极,晶体管M8的源极连接M1的源极,其漏极连接运算放大器CA的反相端,CA反相端还连接晶体管M7的漏极和晶体管M5,M6的漏极,晶体管M5和M6的源极连接晶体管M3和M4的源极,电容C2的两端分别连接晶体管M5和M6的源极和漏极。Figure 3 is a structural diagram of the sampling circuit, SH is the sampling information output terminal, VDD is connected to the source of the transistor Vbias, the drain of Vbias is connected to the source of the transistor M9, the drain of the transistor M9 is connected to the non-inverting terminal of the operational amplifier CA, and the transistor M1 The drain of the transistor M9 is connected to the drain of the transistor M9, its source is connected to the drain of the transistor M3 and one end of the capacitor C0, the source of the transistor M3 is connected to the other end of the capacitor C0, and the drain of the transistor M2 is connected to the drain of the transistor M9 and CA The non-inverting terminal of the transistor M7, its source is connected to the source of the transistor M7 and the drain of the transistor M4, the source of the transistor M4 is connected to one end of the capacitor C1 and the capacitor C0, the other end of the capacitor C1 is connected to the drain of the transistor M4, and the source of the transistor M8 The pole is connected to the source of M1, and its drain is connected to the inverting terminal of the operational amplifier CA, and the CA inverting terminal is also connected to the drain of the transistor M7 and the drains of the transistors M5 and M6, and the sources of the transistors M5 and M6 are connected to the transistors M3 and The source of M4 and the two ends of the capacitor C2 are respectively connected to the source and drain of the transistors M5 and M6.
图4为电平转换电路模块的结构图,UP端和DOWN端为该模块的驱动信号输出端,Driver-logic为驱动控制信号,VCC连接晶体管M1和M4的源极,晶体管M1栅极连接晶体管M3的漏极和输出down,M1的漏极连接晶体管M2的漏极和输出up,晶体管M4的栅极连接M2的漏极,其源极连接晶体管M3的漏极,晶体管M2的栅极接反相器CB的正极和输入信号端,反相器CB的负极接晶体管M3的栅极,晶体管M2和M3的源极接地。Figure 4 is a structural diagram of the level conversion circuit module, the UP terminal and the DOWN terminal are the drive signal output terminals of the module, Driver-logic is the drive control signal, VCC is connected to the sources of transistors M1 and M4, and the gate of transistor M1 is connected to the transistor The drain and output of M3 are down, the drain of M1 is connected to the drain of transistor M2 and output up, the gate of transistor M4 is connected to the drain of M2, its source is connected to the drain of transistor M3, and the gate of transistor M2 is reversed The positive pole of the phase converter CB is connected to the input signal terminal, the negative pole of the inverter CB is connected to the gate of the transistor M3, and the sources of the transistors M2 and M3 are grounded.
图5为软驱动电路的结构图,Driver模块为图4中的电平转换模块,其两个驱动输出端连接RS触发器R和S引脚,晶体管M1的源极和晶体管M4的漏极接VDD,VFB为反馈电压,晶体管M1的栅极接RS触发器的Q端,漏极接晶体管M2的源极,M2的漏极接晶体管M3和M5的漏极,晶体管M3和M5的栅极连接触发器Q端,其源极接地晶体管M4栅极接M2的漏极,其源极接晶体管M7和M8的漏极,晶体管M7的漏极接电阻R1的一端,电阻R1的另一端与电阻R2一端相接,晶体管M7、M8的源极和电阻R2的一端接地,晶体管M7、M8的栅极接反相器CD的负极,反相器正极接RS触发器的QN端,晶体管M6的源极接VDD,栅极接QN,漏极接反相器CD的负极,反相器CD正极连接晶体管M9的栅极,晶体管M9、M10、M11、M12的源极接VDD,晶体管M12的栅漏短接,其漏极连接晶体管M19的漏极,晶体管M19的栅极连接晶体管M20的栅极和电流源DC的正极,晶体管M20的漏极连接电流源DC的正极,晶体管M20、M19、M18、M17、M16、M15、M14的源极接地,晶体管M11的栅漏短接,与晶体管M18的漏极相连,晶体管M18的栅极接电流源DC的正极,晶体管M10的栅极连接晶体管M11的栅极,其漏极连接晶体管M16的漏极,晶体管M9的漏极连接反相器CE的正极和晶体管M17的漏极,反相器CE的负极接晶体管M13的栅极,M13的漏极接晶体管M12的漏极,其源极连接晶体管M14的漏极,晶体管M14、M15的栅极连接晶体管M10的漏极,晶体管M15的漏极连接晶体管M10和M16的漏极。Figure 5 is a structural diagram of the soft drive circuit, the Driver module is the level conversion module in Figure 4, its two drive output terminals are connected to the R and S pins of the RS flip-flop, the source of the transistor M1 and the drain of the transistor M4 are connected to VDD and VFB are feedback voltages, the gate of transistor M1 is connected to the Q terminal of the RS flip-flop, the drain is connected to the source of transistor M2, the drain of M2 is connected to the drains of transistors M3 and M5, and the gates of transistors M3 and M5 are connected Trigger Q terminal, its source is grounded, the gate of transistor M4 is connected to the drain of M2, its source is connected to the drains of transistors M7 and M8, the drain of transistor M7 is connected to one end of resistor R1, and the other end of resistor R1 is connected to resistor R2 One end is connected, the sources of transistors M7 and M8 and one end of resistor R2 are grounded, the gates of transistors M7 and M8 are connected to the negative pole of the inverter CD, the positive pole of the inverter is connected to the QN terminal of the RS flip-flop, and the source of transistor M6 Connect to VDD, connect the gate to QN, connect the drain to the negative pole of the inverter CD, connect the positive pole of the inverter CD to the gate of the transistor M9, connect the sources of the transistors M9, M10, M11, and M12 to VDD, and connect the gate to the drain of the transistor M12 The drain is connected to the drain of the transistor M19, the gate of the transistor M19 is connected to the gate of the transistor M20 and the positive pole of the current source DC, the drain of the transistor M20 is connected to the positive pole of the current source DC, and the transistors M20, M19, M18, M17 , M16, M15, M14's sources are grounded, the gate-drain of transistor M11 is short-circuited and connected to the drain of transistor M18, the gate of transistor M18 is connected to the positive pole of current source DC, and the gate of transistor M10 is connected to the gate of transistor M11 , the drain of which is connected to the drain of transistor M16, the drain of transistor M9 is connected to the anode of inverter CE and the drain of transistor M17, the cathode of inverter CE is connected to the gate of transistor M13, and the drain of M13 is connected to transistor M12 The drain of the transistor M15 has its source connected to the drain of the transistor M14, the gates of the transistors M14 and M15 are connected to the drain of the transistor M10, and the drain of the transistor M15 is connected to the drains of the transistors M10 and M16.
总之,本发明可有效的降低成本和简化了系统设计,同时改良了PSR技术固有的缺陷,实现了较高的恒流精度和输出电压精度,最终结合各个模块的相互配合实现了一个高效率的恒流恒压控制芯片。以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在获知本发明中记载内容后,在不脱离本发明原理的前提下,还可以对其作出若干同等变换和替代,这些同等变换和替代也应视为属于本发明的保护范围。In a word, the present invention can effectively reduce the cost and simplify the system design, improve the inherent defects of PSR technology at the same time, realize higher constant current accuracy and output voltage accuracy, and finally realize a high-efficiency Constant current constant voltage control chip. The above is only a preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, after knowing the content recorded in the present invention, they can also make changes to it without departing from the principle of the present invention. Several equivalent transformations and substitutions should also be deemed to belong to the protection scope of the present invention.
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