CN105871532A - Phase synchronous device and method - Google Patents
Phase synchronous device and method Download PDFInfo
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- CN105871532A CN105871532A CN201610191636.8A CN201610191636A CN105871532A CN 105871532 A CN105871532 A CN 105871532A CN 201610191636 A CN201610191636 A CN 201610191636A CN 105871532 A CN105871532 A CN 105871532A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a phase synchronous device and method. The device comprises a differential discriminator which takes receiving signals as input and is used for removing modulation information of the receiving signals; an error compensator which comprises a first input end and a second input end, wherein the first input end is connected with the output end of the differential discriminator; a loop filter which comprises a first output end and a second output end, wherein the input end is connected with the output end of the error compensator; a first reconstructor of which input end is connected with the first output end of the loop filter, output end is connected with the second input end of the error compensator, wherein the first reconstructor is used for generating loop locking signals; and a second reconstructor of which input end is connected with the second output end of the loop filter, wherein the first reconstructor is used for generating local carriers of which phase is synchronous with that of the receiving signals according to the signals output by the second output end of the loop filter.
Description
Technical field
The present invention relates to Phase synchronization technical field, particularly relate to a kind of phase synchronous device and method.
Background technology
During high-speed digital communication, owing to environment and other influence factors cause being accurately received letter
Number.Such as: owing to making information misjudge in the impact of the residual frequency deviation of receiving terminal or remaining skew.Thus,
Need to be tracked carrier phase synchronizing.
Existing a kind of phase synchronous device is referred to as section's Stas (Costas) ring, and its principle structure figure is such as
Shown in Fig. 1.Its advantage is the phase bit flipping that can eliminate signal in carrier modulation.
Actual realize Costas loop time, existing way has two kinds, a kind of phase place built-in for loop with
Step device, as shown in Figure 2 A.Another kind is the phase synchronous device that loop is external, as shown in Figure 2 B.Phase
For the phase synchronous device that loop is built-in, the external phase synchronous device of loop can allow for therein
Differential discriminator introduces time delay.
But, phase synchronous device that either loop is built-in or the external phase synchronous device of loop,
Needing during Phase synchronization to calculate angle, this needs bigger amount of calculation, therefore to consume more hardware
Resource.
Summary of the invention
It is an object of the invention to provide a kind of phase synchronous device and method, to solve prior art is deposited
Above-mentioned technical problem.
An embodiment provides a kind of phase synchronous device, including: differential discriminator, it is to receive
Signal is as input, for removing the modulation intelligence receiving signal；Error compensator, it includes that first is defeated
Entering end and the second input, first input end is connected with the outfan of differential discriminator；Loop filter, its
Including the first outfan and the second outfan, its input is connected with the outfan of error compensator；The
One reconstructor, its input is connected with the first outfan of loop filter, and its outfan is mended with error
The second input repaying device is connected, and is used for producing loop-locking signal；And second reconstructor, it is defeated
Enter end to be connected with the second outfan of loop filter, for the second outfan according to loop filter
Signal produce and receive the phase locked local carrier of signal.
An alternative embodiment of the invention provides a kind of phase synchronization method, including: remove and receive signal
Modulation intelligence；According to removing the later amplitude receiving signal of modulation intelligence and the amplitude of loop-locking signal
Produce error signal；Loop-locking signal and reconstruction signal is produced by the amplitude of alignment error signal；
And produce and receive the phase locked local carrier of signal by reconstruction signal being carried out tired taking advantage of.
Accompanying drawing explanation
By reading the detailed description of hereafter preferred implementation, various other advantage and benefit for ability
Territory those of ordinary skill will be clear from understanding.Accompanying drawing is only used for illustrating the purpose of preferred implementation, and also
It is not considered as limitation of the present invention.And in whole accompanying drawing, it is denoted by the same reference numerals identical
Parts.The most in the accompanying drawings, the alphabetic flag after reference number indicates multiple identical parts, when referring to
During these parts, its last alphabetic flag will be omitted.In the accompanying drawings:
Fig. 1 is the principle structure figure of Costas loop；
Fig. 2 A is the structure chart of the built-in phase synchronous device of existing loop；
Fig. 2 B is the structure chart of the external phase synchronous device of existing loop；
Fig. 3 show the structure chart of an embodiment of the phase synchronous device of the present invention；
Fig. 4 is the flow chart of an embodiment of the phase synchronization method of the present invention.
In the accompanying drawings, use same or similar label to refer to same or similar element.
Detailed description of the invention
The illustrative embodiments of the present invention is described in detail referring now to accompanying drawing.Should be appreciated that in accompanying drawing
The embodiment illustrated and describe is merely exemplary, it is intended that the principle of the explaination present invention and spirit, and also
Unrestricted the scope of the present invention.
Phase synchronous device in the present invention and method, by directly processing the amplitude vector of complex signal
Complete Phase synchronization.Therefore, each step in the input of each module in following device and method
Rapid input, is all amplitude vector rather than the phase place of signal of signal.Correspondingly, the place in each module
Processing procedure in reason process and each step, is also the amplitude vector for complex signal.
Fig. 3 show the structure chart of an embodiment of the phase synchronous device 300 of the present invention.Such as Fig. 3 institute
Show, phase synchronous device 300 may include that differential discriminator 301, error compensator 302, loop filter 303,
First reconstructor 304 and the second reconstructor 305.
Differential discriminator 301 is using reception signal as input, for removing the modulation intelligence receiving signal.Owing to adjusting
Phase place processed is Given information, it is therefore possible to use any means remove the phase of modulated signal in differential discriminator
Position, such as: utilize the method that two complex signals are mutually multiply-add.In one embodiment of the invention, differential discriminator
In can also comprise phase place concatenation module, it can use early late gate technique to carry out phase place to splice to overcome phase place
The problem of cycle-skipping.
Error compensator 302 can include first input end and the second input.First input end can be with mirror
The outfan of the 301 of difference device is connected.Second input can be with the outfan phase of the 304 of the first reconstructor
Connect.
In one embodiment of the invention, it is the width of complex signal due to the input information of error compensator 302
Degree vector, therefore, error compensator may be constructed such that by calculate from first input end signal with
Conjugate product from the signal of the second input obtains the phase contrast of the two signal.
Loop filter 303 can include the first outfan 3031 and the second outfan, and its input can be with
The outfan of error compensator 302 is connected.The signal of the first outfan output of loop filter can be used
In loop-locking, the signal of the second outfan output may be used for being reconstructed signal.
Owing to entering the amplitude vector that the input information of loop filter 303 is complex signal, therefore, at this
In a bright embodiment, loop filter 303 may further include range value adjusting module, and it is by structure
Make as by keeping its value of real part not while the imaginary values of the input end signal of adjustment loop wave filter 303
Become and change its phase place.Can keep that value of real part is constant to be changed by the imaginary values adjusting complex signal simultaneously
Its phase place.Such as: if phase theta (n) to be synchronized=Δ f n+ Δ φ, then, when matching Δ f, letter can be made
Number real part keep constant, and imaginary part restrains with certain step-length.And reality can also be made during matching Δ φ
Portion keeps constant, and imaginary part restrains with certain step-length.
Owing to the range value of the signal after range value adjusting module adjusts angle also can be changed, therefore,
In order to keep the range value of signal to occur without big variation, in one embodiment of the invention, loop is filtered
Ripple device 303 may further include range value and keeps module, and it is configured to according to range value adjusting module defeated
Go out the variation that it is weighted offsetting range value by the range value size of signal.
In one embodiment of the invention, range value holding module can be according to following Weighted Rule to it
Input signal is weighted:
As | Sc | > 4 time, y=Sc*0.0625；
When 2 < | Sc | < when 4, y=Sc*0.5；
When 0 < | Sc | < when 0.25, y=Sc*8；
When 0.25 < | Sc | < when 0.5, y=Sc*2；
When 0.5 < | Sc | < when 2, y=Sc.
Wherein, Sc represents the output of range value adjusting module, the signal that y obtains after representing holding.
It is emphasized that the rule of above-mentioned point of Pyatyi weighting is an example, it is also possible to be divided into other level
Number is weighted, and the weighted value of every one-level can also adjust change.
Additionally, due to done the process removing modulation intelligence in differential discriminator 301, so, for adopting
For signal with MPSK modulation, as phase theta (n) to be synchronized=Δ f n+ Δ φ, the vector entering ring is taken
The parameter to be estimated of band is D=M Δ f n+M Δ φ.Therefore, need during loop-locking to enter with D=M Δ f n+M Δ φ
Row locking.And the parameter to be estimated in signal is D=Δ f n+ Δ φ, so needing when signal is compensated to use
D=Δ f n+ Δ φ compensates.
The input of the first reconstructor 304 can be connected with the first outfan of loop filter 303, the
The outfan of one reconstructor 304 can be connected with the second input of error compensator 302.So, warp
The signal that first reconstructor 304 reconstructs may be used for producing loop-locking signal.
The input of the second reconstructor 305 can be connected with the second outfan of loop filter 303, the
Two reconstructor 305 produce for the signal of the second outfan according to loop filter 303 and receive signal
Phase locked local carrier.That is: the second reconstructor 305 can export the defeated of phase synchronous device 300
Go out signal.
Owing to entering the amplitude vector that the information of the first reconstructor 304 and the second reconstructor 305 is all signal,
Therefore, the two reconstructor can use and input signal carries out the tired mode taken advantage of reconstruct corresponding letter
Number.When the signal that phase synchronous device receives uses MPSK modulation, the input of the first reconstructor 304
Meeting the relation of M:1 between the input signal of signal and the second reconstructor 305, wherein M represents MPSK
Order of modulation.
So far describing phase synchronous device according to embodiments of the present invention, this phase synchronous device can reduce
Amount of calculation during Phase synchronization, reduces the consumption to hardware resource.
Present invention also offers a kind of phase synchronization method.It is the Phase synchronization side of the present invention with reference to Fig. 4, Fig. 4
The flow chart of one embodiment of method 400.In one embodiment of the invention, phase synchronization method 400
May include steps of 401 to 404.
In step 401, the modulation intelligence of reception signal is removed.
Owing to phase modulation is Given information, it is therefore possible to use any means remove tune in differential discriminator
The phase place of signal processed, such as: utilize the method that two complex signals are mutually multiply-add.In one embodiment of the present of invention
In, it is also possible to use gate technique the latest to carry out phase place and splice with the problem overcoming phase place cycle-skipping.
In step 402, according to removing the later amplitude receiving signal of modulation intelligence and loop-locking signal
Amplitude produce error signal.
In one embodiment of the invention, can be missed by calculating the conjugate product of the two signal
Difference signal, contains the phase contrast of the two signal in error signal.
In step 403, loop-locking signal and reconstruction signal are produced by the amplitude of alignment error signal.
In one embodiment of the invention, real part can be kept by the imaginary values adjusting complex signal simultaneously
Value is constant changes its phase place.Such as: if phase theta (n) to be synchronized=Δ f n+ Δ φ, then when matching Δ f,
The real part that can make signal keeps constant, and imaginary part restrains with certain step-length.And during matching Δ φ also
Real part can be made to keep constant, and imaginary part restrains with certain step-length.
Owing to the range value of the signal after being adjusted also can be changed, therefore, in order to keep the width of signal
Angle value occurs without big variation, in one embodiment of the invention, after can adjusting according to range value
It is weighted compensating to offset the variation of range value by the range value size of signal.
In one embodiment of the invention, according to following Weighted Rule, its input signal can be added
Power:
As | Sc | > 4 time, y=Sc*0.0625；
When 2 < | Sc | < when 4, y=Sc*0.5；
When 0 < | Sc | < when 0.25, y=Sc*8；
When 0.25 < | Sc | < when 0.5, y=Sc*2；
When 0.5 < | Sc | < when 2, y=Sc.
Wherein, Sc represents the signal after real part or imaginary part adjustment, and y represents the signal after range value keeps.
It is emphasized that the rule of above-mentioned point of Pyatyi weighting is an example, it is also possible to be divided into other level
Number is weighted, and the weighted value of every one-level can also adjust change.
Additionally, due to done the process removing modulation intelligence, so, for using
For the signal of MPSK modulation, as phase theta (n) to be synchronized=Δ f n+ Δ φ, enter entrained by the vector of ring
Parameter to be estimated be D=M Δ f n+M Δ φ.Therefore, need during loop-locking to use
D=M Δ f n+M Δ φ locks, and the parameter to be estimated in signal is D=Δ f n+ Δ φ, so to letter
Need to compensate with D=Δ f n+ Δ φ when number compensating.
In step 404, produce and receive the phase locked of signal by reconstruction signal being carried out tired taking advantage of
Local carrier.
Respectively loop-locking signal and reconstruction signal can be carried out tired taking advantage of, obtain for loop-locking signal and
With the phase locked local carrier receiving signal.
So far describing phase synchronization method according to embodiments of the present invention, this phase synchronization method can reduce
Amount of calculation during Phase synchronization, reduces the consumption to hardware resource.
Claims (9)
1. a phase synchronous device, including:
Differential discriminator, it is using reception signal as input, for removing the modulation intelligence receiving signal；
Error compensator, it includes first input end and the second input, described first input end with
The outfan of described differential discriminator is connected；
Loop filter, it includes the first outfan and the second outfan, its input and described mistake
The outfan of difference compensator is connected；
First reconstructor, its input is connected with the first outfan of loop filter, its output
End is connected with the second input of error compensator, is used for producing loop-locking signal；With
And
Second reconstructor, its input is connected, for root with the second outfan of loop filter
Produce according to the signal of the second outfan of loop filter and receive the phase locked of signal
Local carrier.
Phase synchronous device the most according to claim 1, is characterized in that, described error compensator
Take advantage of from the signal of first input end and the conjugation of the signal from the second input by calculating
Amass and obtain phase contrast.
Phase synchronous device the most according to claim 1, is characterized in that, described loop filter
Farther include:
Range value adjusting module, it is configured to input end signal by adjustment loop wave filter
Keep while imaginary values that value of real part is constant changes its phase place.
Phase synchronous device the most according to claim 3, is characterized in that, described loop filter
Farther include:
Range value keeps module, and it is configured to according to described range value adjusting module output signal
It is weighted by range value size.
Phase synchronous device the most according to claim 1, is characterized in that, described first reconstructor
It is configured to produce by the output signal of the first outfan of loop filter carries out tired taking advantage of
Raw loop-locking signal.
Phase synchronous device the most according to claim 1, is characterized in that, described second reconstructor
It is configured to produce by the output signal of the second outfan of loop filter carries out tired taking advantage of
The raw phase locked local carrier with reception signal.
7. a phase synchronization method, is characterized in that, including:
Remove the modulation intelligence receiving signal；
Amplitude according to removing the later amplitude receiving signal of modulation intelligence and loop-locking signal is produced
Raw error signal；
Loop-locking signal and reconstruction signal is produced by the amplitude of alignment error signal；And
The phase locked this locality producing and receiving signal is taken advantage of to carry by carrying out reconstruction signal tiring out
Ripple.
Method the most according to claim 7, is characterized in that, described by alignment error signal
Amplitude produces the step of loop-locking signal and reconstruction signal and farther includes:
Keep constant its phase place that changes of value of real part to obtain while the imaginary values of alignment error signal
Error signal after phase place adjustment.
Method the most according to claim 8, is characterized in that, described by alignment error signal
Amplitude produces the step of loop-locking signal and reconstruction signal and farther includes:
It is weighted by the range value size of the error signal after adjusting according to phase place.
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