CN105870191B

CN105870191B - Gate alignment contact and manufacturing method thereof

Info

Publication number: CN105870191B
Application number: CN201610305963.1A
Authority: CN
Inventors: O·戈隆茨卡; S·希瓦库马; C·H·华莱士; T·加尼
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2011-12-22
Filing date: 2011-12-22
Publication date: 2020-09-15
Anticipated expiration: 2031-12-22
Also published as: CN105870191A

Abstract

Gate alignment contacts and methods of forming gate alignment contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures over an active region formed over a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts are formed, each contact formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts and a plurality of gate structures are formed after the plurality of contact plugs are formed.

Description

Gate alignment contact and manufacturing method thereof

The application is a divisional application, and the original application is international patent application PCT/US2011/066989 with the international application date of 2011, 12 and 22, which is in a Chinese national stage of entering China at 6 and 20 days 2014, and the original application is China national application number 201180075764.1 and is named as a grid alignment contact part and a manufacturing method thereof.

Technical Field

Embodiments of the present invention are in the field of semiconductor devices and processing, and in particular, to gate alignment contacts and methods of forming gate alignment contacts.

Background

Scaling of features in integrated circuits has been a driving force in support of the ever-increasing semiconductor industry over the past decades. Scaling to smaller and smaller features enables increased density of functional units on the limited footprint of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, resulting in the fabrication of products with increased capacity. However, the pursuit of greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

In the manufacture of integrated circuit devices, multi-gate transistors (e.g., tri-gate transistors) are becoming more common as device dimensions continue to scale down. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some examples, bulk silicon substrates are preferred due to their lower cost and because they enable less complex tri-gate fabrication processes. In other instances, silicon-on-insulator substrates are preferred due to the improved short channel characteristics of tri-gate transistors.

Scaling the multiple gate transistors, however, is not without consequence. As the size of these basic building elements of a microelectronic circuit decreases and as the absolute number of basic building elements fabricated in a given area increases, constraints on the lithographic processes used to pattern these building elements become overwhelming. In particular, there is a tradeoff between the minimum size of features patterned in a semiconductor stack (critical dimension) and the spacing between such features.

Disclosure of Invention

Embodiments of the invention include a gate alignment contact and a method of forming a gate alignment contact.

In an embodiment, a semiconductor structure includes a plurality of gate structures disposed over a top surface of a three-dimensional active region disposed over a substrate and along sidewalls of the three-dimensional active region. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contacts are included, each contact disposed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contact plugs is also included, each contact plug disposed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures.

In another embodiment, a method of fabricating a semiconductor structure includes forming a plurality of gate structures over an active region formed over a substrate. Each gate structure includes a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts are formed, each contact formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts and a plurality of gate structures are formed after the plurality of contact plugs are formed.

In another embodiment, a method of fabricating a semiconductor structure includes forming a grid of gate lines over a substrate. The gate line grating includes a plurality of dummy gate lines. The masking stack is formed over and between dummy gate lines of the gate line grid. The patterned hard mask layer is formed from the masking stack only over and between first portions of the dummy gate lines of the gate line grid, exposing second portions of the dummy gate lines. A dielectric layer is formed over the patterned hard mask layer and over and between the second portions of the dummy gate lines. The dielectric layer is planarized to form a patterned dielectric layer over and between the second portions of the dummy gate lines and to re-expose the patterned hard mask layer. The patterned hard mask layer is removed from the first portion of the dummy gate line of the gate line grid, re-exposing the first portion of the dummy gate line. An interlayer dielectric layer is formed over the patterned dielectric layer and over and between the first portions of the dummy gate lines. The interlayer dielectric layer and the patterned dielectric layer are planarized to form a first permanent interlayer dielectric portion between but not over the first portions of the dummy gate lines and a sacrificial dielectric portion between but not over the second portions of the dummy gate lines, respectively. One or more of the dummy gate lines of the first or second portions of the dummy gate lines, or both, are patterned to provide a trench region in the plurality of dummy gates and among the remaining regions of the first permanent interlayer dielectric portion and the sacrificial dielectric portion. The trench region is filled with a second permanent interlayer dielectric portion. The plurality of dummy gates are replaced with permanent gate structures. The remaining regions of the sacrificial dielectric portion are removed to provide contact openings. A contact is then formed in the contact opening.

Drawings

Fig. 1A-1K illustrate cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate aligned contact in accordance with an embodiment of the present invention, wherein:

FIG. 1A illustrates forming a gate line grid over a substrate, the gate line grid including a plurality of dummy gate lines;

FIG. 1B illustrates the formation of a masking stack over and between dummy gate lines of the gate line grid of FIG. 1A;

FIG. 1C illustrates the formation of a patterned hard mask layer from the masking stack of FIG. 1B, the patterned hard mask layer formed over and between only a first portion of a dummy gate line of the gate line grid, exposing a second portion of the dummy gate line;

FIG. 1D illustrates forming a dielectric layer over the patterned hard mask layer of FIG. 1C and over and between the second portions of the dummy gate lines;

FIG. 1E shows the dielectric layer of FIG. 1D planarized to form a patterned dielectric layer over and between the second portions of the dummy gate lines and to re-expose the patterned hardmask layer;

FIG. 1F shows the patterned hard mask layer of FIG. 1E removed from the first portion of the dummy gate line of the gate line grid, re-exposing the first portion of the dummy gate line;

FIG. 1G illustrates an interlayer dielectric layer formed over the patterned dielectric layer and over and between the first portions of the dummy gate lines;

FIG. 1H shows the interlayer dielectric layer and the patterned dielectric layer planarized to form a first permanent interlayer dielectric portion between but not over the first portions of the dummy gate lines and a sacrificial dielectric portion between but not over the second portions of the dummy gate lines, respectively;

FIG. 1I shows one or more dummy gate lines of the first or second portions of the dummy gate lines of FIG. 1H, or both, patterned to provide a trench region in the plurality of dummy gate lines and among the remaining regions of the first permanent interlayer dielectric portion and the sacrificial dielectric portion, the trench region filled with a second permanent interlayer dielectric portion;

FIG. 1J illustrates the replacement of the plurality of dummy gates of FIG. 1I with a permanent gate structure; and

fig. 1K shows the remaining regions of the sacrificial dielectric portion removed to provide contact openings.

Figure 2 illustrates a cross-sectional view of a semiconductor structure having a gate alignment contact in accordance with an embodiment of the present invention.

Figure 3 illustrates a plan view of a semiconductor structure having a gate alignment contact in accordance with an embodiment of the present invention.

Fig. 4 illustrates a plan view of another semiconductor structure having gate alignment contacts in accordance with another embodiment of the present invention.

FIG. 5 illustrates a computing device in accordance with one implementation of the invention.

Detailed Description

Gate alignment contacts and methods of forming gate alignment contacts are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure embodiments of the invention. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

One or more embodiments of the invention relate to a gate aligned contact process. Such a process may be implemented to form contact patterns for semiconductor structure fabrication, such as for integrated circuit fabrication. In an embodiment, the contact pattern is formed to be aligned with an existing gate pattern. In contrast, conventional methods generally involve an additional lithographic process of lithographically patterning a contact pattern in combination with a selective contact etch in close registration with the existing gate pattern. For example, a conventional process may include patterning a poly (gate) grid by patterning contacts and contact plugs, respectively.

According to one or more embodiments described herein, a method of contact formation includes the formation of a contact pattern that is perfectly aligned with an existing gate pattern while eliminating the use of a photolithography step due to a very tight registration budget. In one such embodiment, the method enables the use of an inherently highly selective wet etch (e.g., as opposed to conventionally implemented dry or plasma etches) to create the contact openings. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method can eliminate the need for critical lithographic operations that would otherwise produce contact patterns as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

Fig. 1A-1K illustrate cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate alignment contact in accordance with an embodiment of the present invention. Figure 2 illustrates a cross-sectional view of a semiconductor structure having a gate alignment contact in accordance with an embodiment of the present invention.

Referring first to fig. 2, the semiconductor structure includes a plurality of gate structures 134 disposed over the active region 102 of the substrate. For example, the active region may include a diffusion region 104 as depicted in fig. 2. Gate structures 134 each include a gate dielectric layer 136, a gate electrode 138, and sidewall spacers 110. A dielectric cap 140 may also be included, as described in more detail below. A plurality of contacts 142 is included, each contact being disposed directly between sidewall spacers 110 of two adjacent gate structures of the plurality of gate structures 134. A plurality of contact plugs 128/132 are also included, each contact plug being disposed directly between sidewall spacers 110 of two adjacent gate structures of the plurality of gate structures. Possible material choices for gate structure 134, active region 102, diffusion region 104, gate dielectric layer 136, gate electrode 138, sidewall spacers 110, dielectric cap 140, contact 142, and contact plug 128/132 are provided below. Thus, in an embodiment, there is no intervening material layer or residue so disposed between the sidewall spacers 110 and the contacts 142 of the gate structure 134.

Referring to fig. 1A, an initiation point in a method for fabricating a semiconductor structure (e.g., the structure described in conjunction with fig. 2) may begin with the fabrication of gate line grid 106. The gate line grid 106 may include a dummy gate 106 with spacers 110. A grid of gate lines 106 may be formed over the active area 102 and in some places over the diffusion regions 104 of the active area 102. Thus, in embodiments, source and drain regions (e.g., region 104) are fabricated at this stage. However, the final gate pattern is not yet formed although the gate grid pattern is already formed. The gate line grating 106 may be comprised of nitride pillars or some other sacrificial material, which may be referred to as a gate dummy material, as described in more detail below.

In an embodiment, the active region 102 is composed of a single crystalline material including, but not limited to, silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. Diffusion region 104 is a heavily doped region of active region 102 in one embodiment. In one embodiment, the active region 102 is composed of a group IV material and the one or more portions 104 are doped with boron, arsenic, phosphorous, indium, or a combination thereof. In another embodiment, active region 102 is composed of a III-V material and one or more portions 104 are doped with carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium. In an embodiment, at least a portion of the active region 102 is strained. The active region 102 may be a portion or all of a three-dimensional structure (e.g., a patterned semiconductor body) in one embodiment. Optionally, in another embodiment, the active region 102 is generally planar.

The active region 102 may be included as part of a wider substrate. The substrate may be comprised of a material suitable for semiconductor device fabrication. In an embodiment, the substrate is a bulk substrate. For example, in one embodiment, the substrate is a bulk substrate composed of a single crystalline material, including but not limited to silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. Optionally, the substrate includes an upper epitaxial layer and a lower body portion, either of which may be composed of a single crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. An intermediate insulator layer of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride may be disposed between the upper epitaxial layer and the lower body portion.

The gate line grid 106 may be formed from dummy gates 108. Dummy gate 108 is in embodiments comprised of a material suitable for removal in a replacement gate operation, as discussed below. In one embodiment, the dummy gate 108 is comprised of polysilicon, amorphous silicon, silicon dioxide, silicon nitride, or a combination thereof. In another embodiment, a protective cap layer (not shown), such as a silicon dioxide or silicon nitride layer, is formed over dummy gate 108. In an embodiment, an underlying dummy gate dielectric layer (also not shown) is included. In an embodiment, the dummy gate 108 also includes sidewall spacers 110, which may be comprised of a material suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts. For example, in one embodiment, the spacers 110 are comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

Referring to fig. 1B, a masking stack 112 is formed over and between dummy gates 108 of gate line grid 106. Masking stack 112 includes a hard mask layer 114 and an anti-reflective coating (ARC) layer 116 and a patterned photoresist layer 118. In accordance with an embodiment of the present invention, the photoresist layer 118 of the masking stack 112 is patterned to ultimately facilitate the formation of an interruption (interruption) in the subsequently formed contact pattern. The interruption may be referred to as a "contact plug".

In an embodiment, the hard mask layer 114 is comprised of a material suitable to act as a subsequent sacrificial layer. For example, in one embodiment, as described in more detail below, the hard mask layer 114 is ultimately patterned to leave remaining portions that are subsequently removed selectively to other features. In certain such embodiments, the hard mask layer 114 consists essentially of carbon, for example as a layer of a crosslinked organic polymer. In one embodiment, the hard mask layer 114 is comprised of an organic polymeric material, such as a bottom anti-reflective coating (BARC). In an embodiment, the hard mask layer 114 is formed by a Chemical Vapor Deposition (CVD) process.

In an embodiment, ARC layer 116 is adapted to suppress reflective interference during photolithographic patterning of photoresist layer 118. In one such embodiment, ARC layer 116 is comprised of a spin-on-glass material. The patterned photoresist layer 118 may be comprised of a material suitable for use in a photolithographic process. In one embodiment, patterned photoresist layer 118 is formed by first masking the blanket layer of photoresist material and then exposing it to a light source. The patterned photoresist layer 118 may then be formed by developing the blanket photoresist layer. In an embodiment, the portion of the photoresist layer exposed to the light source is removed when developing the photoresist layer. Thus, the patterned photoresist layer 118 is composed of a positive photoresist material. In particular embodiments, patterned photoresist layer 118 is composed of a positive photoresist material such as, but not limited to, 248nm resist, 193nm resist, 157nm resist, Extreme Ultraviolet (EUV) resist, e-beam imprinting layer, or a phenolic resin matrix with an orthoazidonaphthoquinone sensitizer. In another embodiment, the portion of the photoresist layer exposed to the light source is retained when the photoresist layer is developed. Thus, the patterned photoresist layer 118 is composed of a negative photoresist material. In particular embodiments, patterned photoresist layer 118 is comprised of a negative photoresist material, such as, but not limited to, cis-polyisoprene or polyvinyl cinnamate.

Referring to fig. 1C, the pattern of the photoresist layer 118 is transferred to the hard mask layer 114 by an etching process to provide a patterned hard mask layer 120 over and between some of the dummy gates 108 of the gate line grid 106. The photoresist layer 118 is removed. However, the patterned portion of ARC layer 116 may remain, as depicted in fig. 1C. According to an embodiment of the present invention, the pattern of the photoresist layer 118 is transferred to the hard mask layer 114 to expose the dummy gate 108 over the diffusion region 104, as also depicted in fig. 1C. In one such embodiment, the pattern of the photoresist layer 118 is transferred to the hard mask layer 114 using a plasma etch process.

Referring to fig. 1D, any remaining portion of ARC layer 116 is removed and a dielectric layer 122 is formed over patterned hard mask layer 120 and over and between exposed dummy gates 108 of gate line grid 106. In an embodiment, the dielectric layer 122 is comprised of a material suitable to act as a subsequent sacrificial layer. For example, in one embodiment, the dielectric layer 122 is ultimately removed selectively with respect to other exposed features, as described in more detail below. In a particular embodiment, the dielectric layer is comprised of silicon dioxide.

Referring to fig. 1E, dielectric layer 122 is planarized to form patterned dielectric layer 124 and to re-expose patterned hard mask layer 120. In an embodiment, the dielectric layer 122 is planarized by a Chemical Mechanical Planarization (CMP) process operation. In one such embodiment, the CMP process operation involves polishing the dielectric layer 122 on a polishing pad using a slurry. In another embodiment, a dry etch process is used.

Referring to fig. 1F, the patterned hard mask layer 120 is removed with selectivity to the patterned dielectric layer 124 and with selectivity to the underlying dummy gate 108 of the gate line grid 106. In an embodiment, the patterned hard mask layer 120 is comprised substantially or entirely of carbon and is removed with selectivity to the patterned dielectric layer 124 comprised of silicon dioxide. In an embodiment, the patterned hard mask layer 120 is substantially or entirely comprised of carbon and is removed using an ash process. In one embodiment, the patterned hard mask layer 120 is composed of a carbon-containing substance and utilizes oxygen (O)₂) Gas or nitrogen (N)₂) Gas and hydrogen (H)₂) The combination of gases is removed in a dry ashing operation.

Referring to fig. 1G, an interlayer dielectric layer 126 is formed over the patterned dielectric layer 124 and over and between the exposed dummy gates 108 of the gate line grid 106. According to an embodiment of the present invention, the interlevel dielectric layer 126 provides a first portion of a permanent interlevel dielectric layer, as described below. In one embodiment, the inter-level dielectric layer 126 is composed of a silicon carbide material. In certain such embodiments, the silicon carbide material is formed using a Chemical Vapor Deposition (CVD) process. In another embodiment, the inter-level dielectric layer 126 is composed of a material such as, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride.

Referring to fig. 1H, the interlayer dielectric layer 126 and the patterned dielectric layer 124 are planarized to expose top portions of all dummy gates 108 of the gate line grid 106. According to an embodiment of the invention, the planarization provides a first permanent interlayer dielectric portion 128 and a sacrificial dielectric portion 130. In an embodiment, the inter-level dielectric layer 126 and the patterned dielectric layer 124 are planarized by a CMP process operation, as described above in connection with fig. 1E.

At this stage, the dummy gate 108 of the gate line grid 106, including the spacers 110, may be patterned perpendicular to the grid structure. As an example, portions of gate line grating 106 not over diffusion regions, e.g., over isolation regions, may be removed. In another example, the patterning produces a discrete dummy gate structure. Referring to fig. 1I, in one such embodiment, portions of the dummy gate 108 (and corresponding spacer 110 portions) that are not over the diffusion region 104 are removed, for example, by photolithography and etching processes.

Referring again to fig. 1I, the removed portion of gate line grating 106 may then be filled with a second permanent interlayer dielectric portion 132. Second permanent interlayer dielectric portion 132 may be formed, for example, by deposition and planarization in a manner similar to first permanent interlayer dielectric portion 128 and from the same or similar material as first permanent interlayer dielectric portion 128. It should be understood that the view in FIG. 1I may have a cross-section at a different location (e.g., into or out of the page) than the cross-section shown in FIG. 1H. Thus, at this time, the permanent interlayer dielectric layer may be defined by a combination of the first permanent interlayer dielectric portion 128 formed in the first region (not shown in fig. 1I) and the second permanent interlayer dielectric portion 132 formed in the second region. In one such embodiment, first permanent interlayer dielectric portion 128 and second permanent interlayer dielectric portion 132 are both comprised of silicon carbide.

At this stage, the remaining dummy gates 108 that are exposed may be replaced in a replacement gate process scheme. In such an approach, the dummy gate material (e.g., polysilicon or silicon nitride pillar material) may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being completed from an earlier process.

In an embodiment, the dummy gate 108 is removed by a dry etch or wet etch process. In one embodiment, the dummy gate 108 is made of polysilicon or amorphous silicon and uses including SF₆Is removed. In another embodiment, the dummy gate 108 is made of polysilicon or amorphous silicon and includes aqueous NH₄And removing OH or tetramethyl ammonium hydroxide by wet etching. In one embodiment, dummy gate 108 is comprised of silicon nitride and is removed using a wet etch comprising aqueous phosphoric acid.

Referring to fig. 1J, a permanent gate structure 134 is formed to include a permanent gate dielectric layer 136 and a permanent gate electrode layer or stack 138. Furthermore, in an embodiment, a top portion of the permanent gate structure 134 is removed, for example by an etching process, and replaced with a dielectric cap 140. In an embodiment, dielectric cap 140 is composed of the same material as both first and second permanent

interlayer dielectric portions

128, 132 composed of silicon carbide. In one such embodiment, all of dielectric cap 140, first permanent interlayer dielectric portion 128, and second permanent interlayer dielectric portion 132 are composed of silicon carbide.

In an embodiment, permanent gate dielectric layer 136 is comprised of a high-K material. For example, in one embodiment, permanent gate dielectric layer 136 is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or combinations thereof. Furthermore, a portion of permanent gate dielectric layer 136 may include a layer of native oxide formed from the top few layers of diffusion region 104. In an embodiment, permanent gate dielectric layer 136 is comprised of a top high-k portion and a lower portion comprised of an oxide of a semiconductor material. In one embodiment, permanent gate dielectric layer 136 is comprised of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

In an embodiment, the permanent gate electrode layer or stack 138 is comprised of a metal gate. In one embodiment, permanent gate electrode layer or stack 138 is comprised of a metal layer such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a particular embodiment, the permanent gate electrode layer or stack 138 is comprised of a non-workfunction setting fill material formed over a metal workfunction setting layer. In an embodiment, the permanent gate electrode layer or stack 138 also includes sidewall spacers 110, which may be comprised of an insulating dielectric material, as described above.

Referring to fig. 1K, sacrificial dielectric portion 130 is removed selectively with respect to dielectric cap 140, first permanent interlayer dielectric portion 128, second permanent interlayer dielectric portion 132, spacers 110, and the exposed portions of diffusion region 104. In an embodiment, the sacrificial dielectric portion 130 is removed using a dry etch or wet etch process, such as an aqueous hydrofluoric acid (HF) wet etch process. According to an embodiment of the invention, the sacrificial dielectric portion 130 acts as a sacrificial placeholder for subsequent contact formation.

Referring again to fig. 2, once sacrificial dielectric portion 130 is disposed, contact 142 is formed. Thus, a contact 142 is formed between the permanent gate structures 134. In an embodiment, the contact 142 is formed by deposition and planarization (e.g., by CMP) of a conductive material. The contact portion 142 may be composed of a conductive material. In an embodiment, the contact portion 142 is composed of a metal substance. The metal species may be a pure metal (e.g., nickel or cobalt), or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

Figure 3 illustrates a plan view showing certain features of a semiconductor structure, in accordance with an embodiment of the present invention. Referring to fig. 3, the semiconductor structure includes a plurality of gate structures 134 disposed over an active region 102 (e.g., diffusion region 104) of a substrate. A plurality of contacts 142 is included, each contact being disposed directly between two adjacent gate structures of the plurality of gate structures 134, e.g., directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures 134.

Accordingly, in an embodiment, a method of fabricating a semiconductor structure includes forming a grid of gate lines over a substrate. The gate line grating includes a plurality of dummy gate lines. The masking stack is formed over and between dummy gate lines of the gate line grid. A patterned hard mask layer is formed from the masking stack over and between only a first portion of the dummy gate lines of the gate line grid, exposing a second portion of the dummy gate lines. A dielectric layer is formed over the patterned hard mask layer and over and between the second portions of the dummy gate lines. The dielectric layer is planarized to form a patterned dielectric layer over and between the second portions of the dummy gate lines and to re-expose the patterned hard mask layer. The patterned hard mask layer is removed from the first portion of the dummy gate line of the gate line grid, re-exposing the first portion of the dummy gate line. An interlayer dielectric layer is formed over the patterned hard mask layer and over and between the first portions of the dummy gate lines. The interlayer dielectric layer and the patterned dielectric layer are planarized to form a first permanent interlayer dielectric portion between but not over the first portions of the dummy gate lines and a sacrificial dielectric portion between but not over the second portions of the dummy gate lines, respectively. One or more of the dummy gate lines of the first or second portions of the dummy gate lines, or both, are patterned to provide a trench region in the plurality of dummy gates and among the remaining regions of the first permanent interlayer dielectric portion and the sacrificial dielectric portion. The trench region is filled with a second permanent interlayer dielectric portion. The plurality of dummy gates are replaced with permanent gate structures. The remaining regions of the sacrificial dielectric portion are removed to provide contact openings. A contact is then formed in the contact opening.

In one such embodiment, forming the patterned hard mask layer includes forming a layer of crosslinked organic polymer, forming the dielectric layer includes forming a layer of silicon dioxide, forming the interlayer dielectric layer includes forming a layer of silicon carbide, and partially filling the trench regions with the second permanent interlayer dielectric includes forming and planarizing the second layer of silicon carbide. In a particular such embodiment, replacing the plurality of dummy gates with the permanent gate structures includes forming a permanent gate dielectric layer, a permanent gate layer, and a silicon carbide cap layer. In another such embodiment, forming a gate line grid over the substrate includes forming dummy gate lines over a top surface of the three-dimensional active region and along sidewalls of the three-dimensional active region.

In an embodiment, one or more methods described herein effectively contemplate dummy and replacement gate processes in combination with dummy and replacement contact processes. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in certain such embodiments, the annealing of at least a portion of the permanent gate structure is performed at a temperature greater than approximately 600 degrees celsius, for example, after the gate dielectric layer is formed. The annealing is performed prior to the formation of the permanent contact.

In an embodiment, the dummy contact is formed prior to the formation of the contact plug. That is, the dummy contacts may be formed prior to cutting the dummy gate structures in the gate grid. Such an approach may provide flexibility in the final layout. In one such embodiment, a contact structure is formed in contact with two or more diffusion regions. For example, fig. 4 shows a plan view of another semiconductor structure having gate alignment contacts in accordance with another embodiment of the present invention.

Referring to fig. 4, the semiconductor structure includes a plurality of gate structures 134 disposed over an active region 102 (e.g., diffusion region 104) of a substrate. A plurality of contacts 142 is included, each contact being disposed directly between two adjacent gate structures of the plurality of gate structures 134, e.g., directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures 134. One of the contacts 144 is formed in contact with both diffusion regions. In a particular embodiment, the formation of the contacts 144 is facilitated by a pre-existing dummy gate grid line that is not cut until at least the dummy contact placeholder for the contacts 144 is formed.

It should be understood that not all aspects of the processes described above need to be performed to fall within the spirit and scope of embodiments of the present invention. For example, in one embodiment, the dummy gate never needs to be formed. The gate stack described above may actually be a permanent gate stack as originally formed. In one such embodiment, benefits and advantages are realized so long as plug formation is followed by a gate cut operation.

The processes described herein may be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or the like. For example, in an embodiment, the semiconductor device is a Metal Oxide Semiconductor (MOS) transistor, or a bipolar transistor for logic or memory. Furthermore, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, or a FIN-FET.

FIG. 5 illustrates a computing device 500 in accordance with an implementation of the invention. The computing device 500 houses a board 502. The board 502 may include a number of components including, but not limited to, a processor 504 and at least one communication chip 506. The processor 504 is physically and electrically coupled to the board 502. In some implementations, at least one communication chip 506 is also physically and electrically coupled to the board 502. In further implementations, the communication chip 506 is part of the processor 504.

Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to board 502. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.).

The communication chip 506 enables wireless communication for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 506 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher generation. The computing device 500 may include a plurality of communication chips 506. For example, a first communication chip 506 may be dedicated for shorter range wireless communications (e.g., Wi-Fi and Bluetooth), while a second communication chip 506 may be dedicated for longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and so on.

The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors, constructed in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. According to another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors, constructed according to an implementation of the invention.

In further implementations, another component housed within the computing device 500 may include an integrated circuit die that includes one or more devices, such as MOS-FET transistors, constructed in accordance with implementations of the invention.

In various implementations, the computing device 500 may be a laptop computer, a netbook, a notebook computer, an ultrabook computer, a smartphone, a tablet computer, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

Accordingly, a gate alignment contact and a method of forming a gate alignment contact are disclosed. In an embodiment, a method of fabricating a semiconductor structure includes forming a plurality of gate structures over an active region formed over a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug being formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts are formed, each contact formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed after the plurality of contact plugs are formed. In one embodiment, the plurality of gate structures are formed by replacing the plurality of dummy gates prior to forming the plurality of contacts. In one embodiment, forming the plurality of contacts includes forming a contact structure in contact with two or more diffusion regions of the active region.

Claims

1. A semiconductor structure, comprising:

a plurality of gate structures, each of the plurality of gate structures disposed over a three-dimensional active region of a substrate without being disposed over an isolation region, each of the plurality of gate structures comprising a gate dielectric layer, a gate electrode, sidewall spacers, and a dielectric cap layer located between and laterally adjacent to the sidewall spacers, wherein the sidewall spacers comprise a first dielectric material, wherein the dielectric cap layer comprises a second dielectric material that is independent of the first dielectric material, and wherein the first dielectric material of the sidewall spacers intersects the second dielectric material of the dielectric cap layer at a substantially vertical interface;

a plurality of contacts, each of the plurality of contacts disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures and each disposed over the three-dimensional active region and not over the isolation region, and a top surface of each of the plurality of contacts being substantially coplanar with a top surface of the dielectric cap layer of the plurality of gate structures; and

a plurality of contact plugs, each of the plurality of contact plugs disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures, and a top surface of each of the plurality of contact plugs is substantially coplanar with the top surface of the dielectric cap layer of the plurality of gate structures and substantially coplanar with the top surface of the plurality of contacts.

2. The semiconductor structure of claim 1, wherein each of the plurality of gate structures comprises a high-K gate dielectric, a metal gate, and a silicon carbide cap of the second dielectric material as the dielectric cap.

3. The semiconductor structure of claim 1, wherein said sidewall spacers are comprised of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

4. The semiconductor structure of claim 3, wherein said dielectric cap layer is comprised of silicon carbide.

5. The semiconductor structure of claim 1, wherein said plurality of contacts comprise a conductive material and said plurality of contact plugs comprise silicon carbide.

6. The semiconductor structure of claim 5, wherein each of the plurality of gate structures comprises a high-K gate dielectric, a metal gate, and a silicon carbide cap of the second dielectric material as the dielectric cap.

7. The semiconductor structure of claim 1, wherein one of the plurality of contacts is in contact with two or more diffusion regions of the three-dimensional active region.

8. A semiconductor structure, comprising:

a plurality of gate structures, each of the plurality of gate structures disposed over an active region of a substrate and not disposed over an isolation region, each of the plurality of gate structures comprising a gate dielectric layer, a gate electrode, sidewall spacers, and a dielectric capping layer located between and laterally adjacent to the sidewall spacers, wherein the sidewall spacers comprise a first dielectric material, wherein the dielectric capping layer comprises a second dielectric material that is independent of the first dielectric material, and wherein the first dielectric material of the sidewall spacers intersects the second dielectric material of the dielectric capping layer at a substantially vertical interface;

a plurality of contacts, each of the plurality of contacts disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures and each disposed over the active region and not disposed over the isolation region, and a top surface of each of the plurality of contacts is substantially coplanar with a top surface of the dielectric cap layer of the plurality of gate structures; and

9. The semiconductor structure of claim 8, wherein each of the plurality of gate structures comprises a high-K gate dielectric, a metal gate, and a silicon carbide cap of the second dielectric material as the dielectric cap.

10. The semiconductor structure of claim 8, wherein said sidewall spacers are comprised of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

11. The semiconductor structure of claim 10, wherein said dielectric cap layer is comprised of silicon carbide.

12. The semiconductor structure of claim 8, wherein said plurality of contacts comprise a conductive material and said plurality of contact plugs comprise silicon carbide.

13. The semiconductor structure of claim 12, wherein each of the plurality of gate structures comprises a high-K gate dielectric, a metal gate, and a silicon carbide cap of the second dielectric material as the dielectric cap.

14. The semiconductor structure of claim 8, wherein one of the plurality of contacts is in contact with two or more diffusion regions of the active region of the substrate.