CN105826367A - Large-current silicon on insulator lateral insulated gate bipolar transistor device - Google Patents
Large-current silicon on insulator lateral insulated gate bipolar transistor device Download PDFInfo
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- 239000012212 insulator Substances 0.000 title claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 13
- 239000010703 silicon Substances 0.000 title claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 24
- 239000001301 oxygen Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 4
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 4
- 238000009413 insulation Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 235000019994 cava Nutrition 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 210000000746 body region Anatomy 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000036039 immunity Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229940125782 compound 2 Drugs 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000027950 fever generation Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
The invention discloses a novel large-current silicon on insulator lateral insulated gate bipolar transistor. According to the semiconductor, a buried oxide is arranged on a P-type substrate, an N-type drift region is arranged on the buried oxide, a P-type body region and an N-type buffer region are arranged on the N-type drift region, the N-type buffer region is internally provided with a P-type collector region, a collector metal is connected onto the P-type collector region, a field oxygen layer is arranged above the N-type drift region, the P-type body region is internally provided with a P-type emitter region, an N-type emitter region is arranged around, an emitter metal is connected onto the N-type emitter region and the P-type emitter region, a gate oxide is arranged between the field oxygen layer and the N-type emitter region, a first polysilicon layer is arranged on the surface of the gate oxide, a first gate metal is connected onto the surface of the first polysilicon layer, a longitudinal groove is arranged outside the P-type body region, the longitudinal groove is internally provided with silicon dioxide and a second polysilicon layer coated by other medium, and a second gate metal is connected onto the second polysilicon layer.
Description
Technical field
The invention mainly relates to power semiconductor device technology field, be silicon landscape insulation bar double-pole-type transistor in a kind of novel big current insulator, be particularly well-suited in monolithic integrated power chip, be used for realizing the accurate control to electric system.
Background technology
Insulated gate bipolar transistor IGBT be mos gate device architecture combine with bipolar transistor structure evolve compound power device, it is provided simultaneously with the feature of metal-oxide-semiconductor and bipolar transistor, there is the tradeoff between good on state current and switching loss.Silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LateralInsulatedGateBipolarTransistor, SOI-LIGBT) it is a kind of typical device based on SOI technology, there is advantages such as being easily integrated, pressure height, current drive capability are strong, switching speed is fast, be widely applied in power integrated circuit.
Due to the above advantage, SOI-LIGBT is frequently as core devices, in monolithic integrated power chip.But, SOI-LIGBT device current capability is less than normal is that restriction monolithic integrated power working frequency of chip is higher, work efficiency more preferably, bottleneck that chip area is less.Therefore, in order to improve the current capacity of device, it is currently suggested some devices, but these devices are while improving current capacity, can bring again new problem.SOI-LIGBT structure is generally used in circuit adjusting the energy being sent to various load by DC source, by accident, load in circuit can form short circuit, cause DC source will be attached directly to colelctor electrode and the emitter stage of SOI-LIGBT, and now its gate bias still turns on, now device can bear high voltage and big electric current simultaneously, and the drain electrode bigger in electric current density can produce obvious heat effect, once exceeding the short circuiting work time of device, device can occur thermal breakdown to lose efficacy.Meanwhile, the ON state BV value of device substantially can reduce due to the thermal breakdown in this region, and pressure decline can reduce the maximum operating voltage of device, makes the utilization of device be restricted.
Additionally, due to the lifting of current capacity, device can be easier to latch-up, and latch-up can make gate signal lose the control to device, and device architecture may experience destructive failure, the decline of breech lock rejection ability so that the reliability of device reduces.
Therefore, retainer member pressure, do not reduce the breech lock rejection ability of SOI-LIGBT on the basis of improve the conducting current density of SOI-LIGBT and SOA ability is to develop the main development direction of monolithic integrated power chip in electric system.
Summary of the invention
The present invention is directed to the problems referred to above, it is proposed that silicon landscape insulation bar double-pole-type transistor device in a kind of big current insulator that can improve injection efficiency and energy boost device overall current ability.This structure is pressure in retainer member, suppression is on the premise of breech lock ability reduces, significantly improve the electric current density of device, extend its effective and safe working area, enable to meet in electric system monolithic integrated power chip to SOI-LIGBT device high pressure, big electric current and highly reliable requirement.
nullSilicon landscape insulation bar double-pole-type transistor device in a kind of big current insulator，Including: P type substrate，P type substrate is provided with and buries oxygen，N-type drift region it is provided with on oxygen burying，It is respectively provided on two sides with N-type relief area and PXing Ti district in N-type drift region，Heavily doped p-type collector area is had in N-type relief area，Connect on heavily doped p-type collector area and have collector electrode metal，Heavily doped p-type emitter region it is provided with in PXing Ti district，Periphery at heavily doped p-type emitter region is provided with heavily doped N-type launch site，Above-mentioned heavily doped p-type emitter region and heavily doped N-type launch site connect and has emitter metal，It is arranged over an oxygen layer in N-type drift region，One lateral boundaries of described field oxygen layer falls above N-type relief area，Opposite side border connects with PXing Ti district，It is provided with gate oxide between oxygen layer on the scene and heavily doped N-type launch site，It is provided with the first polysilicon layer on gate oxide surface and described first polysilicon layer extends to above an oxygen layer，Connect on the surface of the first polysilicon layer and have first grid metal，It is characterized in that，It is provided with longitudinal groove outside described PXing Ti district，The second polysilicon layer wrapped up by silicon dioxide or other pressure medium it is provided with in longitudinal groove，Second polysilicon layer connects and has second gate metal.
Silicon landscape insulation bar double-pole-type transistor device in described big current insulator, it is characterised in that be provided with p type buried layer in described PXing Ti district, and described p type buried layer is positioned at the lower section of heavily doped p-type emitter region.
Silicon landscape insulation bar double-pole-type transistor device in described big current insulator, it is characterized in that, heavily doped p-type emitter region is made up of the heavily doped p-type emitter region block being arranged in a linear, heavily doped N-type launch site between adjacent heavily doped p-type emitter region block caves inward, and gate oxide and the first polysilicon layer are charged into and extended and occupy described sunk area.
Silicon landscape insulation bar double-pole-type transistor device in described big current insulator, it is characterised in that the concentration of described p type buried layer is higher than PXing Ti district.
Compared with prior art, present invention have the advantage that
The present invention solves the problem that ON state BV value is degenerated.In traditional SOI-LIGBT device, existence due to JFET region, as shown in Figure 1, in the case of break-over of device, substantial amounts of electronics can be assembled in this region, bigger by the electric current in this region, and the resistance value of this part is relatively large, so region can produce obvious heat effect, cause device to puncture, reduce the BV value of device.Present planar structure cannot fundamentally solve the problem that the local pyrexia of JFET region causes device breakdown.The present invention is provided with the raceway groove of Z-direction can effectively reduce the electronics aggregation extent in JEFT region in conventional planar device, thus reduces its probability that thermal breakdown occurs so that present configuration reliability in short-circuit process is higher.
The present invention solves the contradictory problems between high current density and latch-up immunity.In SOI-LIGBT device, the lifting of current capacity can cause device inside parasitic NPN audion to be easier to open so that the latch-up immunity of device reduces.One aspect of the present invention is due to the existence of the longitudinal channel of Z-direction, make electronics can be directly entered drift region by this longitudinal channel, hole current from colelctor electrode can flow along BOX layer to PXing Ti district, the present invention can be combined in PXing Ti district with the hole from colelctor electrode directly below by the electronics of longitudinal groove, thus reducing hole current density so that latch-up is more difficult to occur for comparing traditional structure.As shown in Fig. 7 compound 2, the introducing of longitudinal groove reduces hole injection efficiency so that endoparasitic NPN pipe is difficult to open for comparing traditional structure；On the other hand, the present invention is provided with high concentration p type buried layer in PXing Ti district, reduces its resistance, so that the pressure drop that electric current produces after flowing through is relatively low, when this pressure drop is less than the cut-in voltage of PN junction, parasitic NPN audion will not be opened, thus the problem avoiding device generation breech lock reliability.
Invention increases the raceway groove of Z-direction, and then improve the current capacity of device.
Meanwhile, the ratio W of the length of side of evagination square region drift region square with N-type1\W2Adjustable, can be more flexible in reality application, compromise between conducting current density and the conducting resistance reducing JFET region increasing.
Therefore device of the present invention is on the basis of significantly improving the conducting current density of device, improves again the breech lock rejection ability of device, extend its safety operation area so that it is more suitable for being operated in the motor driven systems of high-voltage great-current.
Accompanying drawing explanation
Fig. 1 show the device profile structure chart of silicon landscape insulation bar double-pole-type transistor in conventional insulator.
Fig. 2 show the top view of present configuration.
Fig. 3 show the sectional structure chart of present configuration.
Fig. 4 show present configuration and removes the graphics of metal electrode.
Fig. 5 show the graphics after present configuration region portions amplifies.
Fig. 6 show present configuration and removes metal electrode and field oxygen layer post tensioned unbonded prestressed concrete adds the top view of malleation.
Fig. 7 show present configuration electric current and produces and building mechanism and equivalent circuit horizontal section schematic diagram.
Fig. 8 show present configuration and traditional structure ON state BV comparison diagram in the case of same current density.
Fig. 9 show the pressure comparison diagram of present configuration and traditional structure.
Figure 10 show present configuration W2Normallized current density during change.
Figure 11 show the I-V curve comparison diagram of present configuration and traditional structure.
Detailed description of the invention
Below in conjunction with Fig. 2, Fig. 3, Fig. 4, the present invention is elaborated:
nullSilicon landscape insulation bar double-pole-type transistor device in a kind of big current insulator，Including: P type substrate 1，P type substrate 1 is provided with and buries oxygen 2，N-type drift region 3 it is provided with on oxygen 2 burying，It is respectively provided on two sides with district 14, N-type relief area 4 and PXing Ti in N-type drift region 3，Heavily doped p-type collector area 5 is had in N-type relief area 4，Connect on heavily doped p-type collector area 5 and have collector electrode metal 21，Heavily doped p-type emitter region 8 it is provided with in PXing Ti district 14，Periphery at heavily doped p-type emitter region 8 is provided with heavily doped N-type launch site 9，Above-mentioned heavily doped p-type emitter region 8 and heavily doped N-type launch site 9 connect and has emitter metal 18，It is arranged over an oxygen layer 6 in N-type drift region 3，One lateral boundaries of described field oxygen layer 6 falls above N-type relief area 4，Opposite side border connects with PXing Ti district 14，It is provided with gate oxide 10 between oxygen layer 6 on the scene and heavily doped N-type launch site 9，It is provided with the first polysilicon layer 7 on gate oxide 10 surface and described first polysilicon layer 7 extends to above an oxygen layer 6，Connect on the surface of the first polysilicon layer 7 and have first grid metal 20，It is provided with longitudinal groove 11 outside described PXing Ti district 14，The second polysilicon layer 12 wrapped up by silicon dioxide or other pressure medium it is provided with in longitudinal groove 11，Second polysilicon layer 12 connects and has second gate metal 17.
In this example, in described PXing Ti district 14, it is provided with p type buried layer 13, and described p type buried layer 13 is positioned at the lower section of heavily doped p-type emitter region 8；nullHeavily doped p-type emitter region 8 is made up of the heavily doped p-type emitter region block being arranged in a linear，Heavily doped N-type launch site 9 between adjacent heavily doped p-type emitter region block caves inward，Gate oxide 10 and the first polysilicon layer 7 are charged into and are extended and occupy described sunk area，Gate oxide 10 and the first polysilicon layer 7 are charged into and extended occupied region can be a square region 16，The both sides of the evagination square region 15 of emitter region 9 are respectively defined as the second N-type emitter region 9b and the 4th N and are spaced emitter region 9d，The emitter region part on the summit, both sides, inner side connecting the evagination square region 16 of emitter region 9 is defined as the first N-type emitter region 9a，The bottom of the evagination square region 15 of emitter region 9 is defined as the 3rd N-type emitter region 9c，Above-mentioned first emitter region 9a、Second emitter region 9b、3rd emitter region 9c、4th emitter region 9d surrounds p-type emitter region 8，Above-mentioned evagination square region 16 is spaced apart along the 3rd N-type emitter region 9c，The middle interval of adjacent two evagination square region 16 is with the square drift region of N-type 15，Outside the square drift region of N-type 15、The inner side of the 3rd N-type emitter region is provided with PXing Ti district 14，It is provided with gate oxide 10 in the region of above-mentioned PXing Ti district 14 beyond p type buried layer 13 full square region 16，Described gate oxide 10 extends to field oxygen layer 6 and terminates in the border of an oxygen layer 6，It is provided with polysilicon layer 7 on gate oxide 10 surface and described polysilicon layer 7 extends to above an oxygen layer 6；The concentration of described p type buried layer 13 is higher than PXing Ti district 14.
Below in conjunction with the accompanying drawings the present invention is further described.
The operation principle of the present invention:
The grid structure of this device is made up of, such as Fig. 5 the deep trouth grid of planar gate and Z-direction.When two gate electrodes of this device all add malleation, the PXing Ti district below planar gate defines one and connects heavily doped N-type launch site and the N-type lateral channel of N-type drift region, such as Fig. 6.In the PXing Ti district, inner side of groove grid, define one connect heavily doped N-type launch site and the N-type longitudinal channel of N-type drift region.When colelctor electrode adds malleation, such as Fig. 7, electronic current IeIt is sent to N-type drift region from N-type launch site respectively by longitudinal channel and lateral channel.The efficiency that electronics injects from channel region gets a promotion.Electronic current, as the ideal base drive current of PNP transistor, promotes hole to inject N-type drift region from heavily doped p-type collecting zone, and injected holes defines the emitter current I of PNP transistorh.Traditional devices compared by described device, because the relation that electronic current increases, ideal base drive current increases, and more hole can be attracted to inject N-type drift region, increase the emitter current of PNP transistor.Electric current from colelctor electrode to emitter stage is made up of two parts, including the electronic current I through MOSFET region raceway grooveeWith the hole current I flowing through PNP pipeh, described device makes this two-part electric current all increase, and the total current of device rises.
When device is in short-circuit condition, device can cause inefficacy due to high-voltage large current situation, in order to device has the longer short circuiting work time, it is desirable to device should have bigger ON state BV value.For traditional structure, the inherent mechanism causing inefficacy in short-circuit process is, when device is opened, the square region of caving in of traditional structure can assemble substantial amounts of electronics, corresponding electric current density is the biggest, and owing to emitter stage and the colelctor electrode of device are direct and power supply short circuit, therefore device both end voltage value is the highest, while high voltage and big electric current, existence can cause this region to produce obvious heat effect at short notice, thus causes inefficacy.And invention introduces the longitudinal channel of Z-direction, originally the electronics that can only flow in device surface single-groove road can be flowed by longitudinal channel, thus reduce the aggregation extent of traditional structure electronics, the heat effect making JFET region reduces, and then suppress the problem that its ON state BV degenerates, in the case of high-voltage great-current, reliability is higher, extends the effective range of its safety operation area so that present invention reliability in short-circuit process is higher.
LIGBT structure is alternately made up of 4 layers of N-type and territory, p type island region, such as Fig. 4, this generates the IGCT of parasitism.When LIGBT electric current is too big, make that IGCT NPN's is partially ON, then parasitic thyristor latch, now in device, electric current continues to increase, and gate signal will be unable to control the shutoff of LIGBT, makes LIGBT structure experience destructive failure.Increasing the conducting current density of device, device will enter into latch mode at lower voltage, reduces the reliability of device.For traditional devices, when hole flows into through N-type drift region from colelctor electrode, then it flow to emitter stage through PXing Ti district, due to the base resistor existence in this region, pressure drop when electric current flows through this region, can be produced, when this pressure drop is more than the cut-in voltage of PN junction, above-mentioned NPN pipe is opened, and latch-up occurs.On the one hand this structure is provided with Z-direction longitudinal channel, make electronics can be directly entered drift region by this longitudinal channel, occur compound with the hole from colelctor electrode, reduce hole current density so that parasitic NPN pipe is difficult to open, compound 2 as shown in Figure 7, owing to the introducing of longitudinal channel reduces hole current, improve the unlatching difficulty of parasitic NPN pipe, on the other hand, this structure is provided with high concentration p type buried layer in PXing Ti district, the resistance value making this region is relatively small, the pressure drop that electric current flows through the generation of this region is the most relatively small, when this pressure drop is less than PN junction cut-in voltage, parasitic NPN pipe will not be opened.Comprehensive two above aspect, the latch-up immunity of device is improved.
Evagination square region and length of side W of the square drift region of N-type for described device1With W2The most adjustable.Second N-type emitter region, the 3rd N-type emitter region, the 4th N-type emitter region define a JFET region, 15 region in Fig. 2, and JEFT district creates extra resistance RJEFT, but in the ordinary course of things, drift resistance is main Rdrain ＞ ＞ RJEFT, JEFT district resistance can be ignored.Changing W1With W2Length time, the shape in JEFT region also changes, and the resistance in JEFT district the most just changes.Work as W2During reduction, RJEFTTo increase, the length of the 3rd N-type emitter region little to a certain extent time, RJEFTWill be unable to ignore, the most total conducting resistance increases, and conducting current density reduces, W to be ensured2Can not be the least.
And changing length of side W of the square drift region of N-type2Time, the length of the first N-type emitter region is the longest, and equivalence channel length is the longest, and the injection efficiency of electronics is the highest, and conducting current density increases.But the first N-type emitter region is the biggest, and the resistance in JEFT district is the biggest, when the length of the first N-type emitter region is too big, RJEFTWill be unable to ignore, make total conducting resistance increase, conducting current density reduces, and therefore the length of the first N-type emitter region has certain limitations, it is impossible to unrestrictedly increase.
In order to verify advantages of the present invention, this patent has carried out contrast simulation to structure, as shown in Fig. 8～Figure 11 by semiconductor device simulation software SentaurusTcad.Fig. 8 is present configuration and traditional structure ON state BV in the case of same current density, present configuration device ON state BV value in the case of same current density is higher as seen from the figure, i.e. correspond to its safety operation area wider, in the case of high-voltage great-current, reliability is higher.Fig. 9 is the pressure comparison diagram of present configuration and traditional devices, and present configuration is pressure identical with traditional devices as seen from the figure, is improving the electric current density of device, and in the case of improve the breech lock rejection ability of device, the pressure not loss of device.In Figure 10, W2The length of side for the square drift region of N-type.Figure 10 indicates N-type square drift region length of side value W of present configuration2Normallized current density value during change, as seen from the figure when length of side W of the square drift region of N-type2Reduce, RJEFTTo increase, W2Little to a certain extent time, RJEFTWill be unable to ignore, the most total conducting resistance increases, and conducting current density reduces, W to be ensured2Value can not be the least；Length of side W when the square drift region of N-type2Time the biggest, length of side W of evagination square region1Reducing, the equivalent channel length of unit sizes reduces, and electron injection efficiency reduces, and conducting current density reduces, therefore length of side W of the square drift region of N-type2Can not be the biggest.Figure 11 is the I-V curve comparison diagram of present configuration and traditional structure, and the conducting current capacity of present configuration is stronger than traditional structure as seen from the figure.
Therefore device of the present invention is on the basis of significantly improving the conducting current density of device, improves again the breech lock rejection ability of device, extend its safety operation area so that it is more suitable for being operated in the motor driven systems of high-voltage great-current.
Claims (4)
- null1. silicon landscape insulation bar double-pole-type transistor device in a big current insulator，Including: P type substrate (1)，P type substrate (1) is provided with and buries oxygen (2)，N-type drift region (3) it is provided with on oxygen (2) burying，It is respectively provided on two sides with N-type relief area (4) and PXing Ti district (14) in N-type drift region (3)，Heavily doped p-type collector area (5) is had in N-type relief area (4)，The upper connection of heavily doped p-type collector area (5) has collector electrode metal (21)，Heavily doped p-type emitter region (8) it is provided with in PXing Ti district (14)，Periphery heavily doped p-type emitter region (8) is provided with heavily doped N-type launch site (9)，Emitter metal (18) is had in the upper connection of above-mentioned heavily doped p-type emitter region (8) and heavily doped N-type launch site (9)，It is arranged over an oxygen layer (6) in N-type drift region (3)，One lateral boundaries of described field oxygen layer (6) falls in the top of N-type relief area (4)，Opposite side border connects with PXing Ti district (14)，Gate oxide (10) it is provided with between oxygen layer on the scene (6) and heavily doped N-type launch site (9)，It is provided with the first polysilicon layer (7) on gate oxide (10) surface and described first polysilicon layer (7) extends to the top of an oxygen layer (6)，Connect on the surface of the first polysilicon layer (7) and have first grid metal (20)，It is characterized in that，It is provided with longitudinal groove (11) in described PXing Ti district (14) outside，The second polysilicon layer (12) wrapped up by silicon dioxide or other pressure medium it is provided with in longitudinal groove (11)，Second gate metal (17) is had in the upper connection of the second polysilicon layer (12).
- Silicon landscape insulation bar double-pole-type transistor device in big current insulator the most according to claim 1, it is characterized in that, in described PXing Ti district (14), it is provided with p type buried layer (13), and described p type buried layer (13) is positioned at the lower section of heavily doped p-type emitter region (8).
- Silicon landscape insulation bar double-pole-type transistor device in big current insulator the most according to claim 2, it is characterized in that, heavily doped p-type emitter region (8) is made up of the heavily doped p-type emitter region block being arranged in a linear, heavily doped N-type launch site (9) between adjacent heavily doped p-type emitter region block caves inward, and gate oxide (10) and the first polysilicon layer (7) are charged into and extended and occupy described sunk area.
- Silicon landscape insulation bar double-pole-type transistor device in big current insulator the most according to claim 2, it is characterised in that the concentration of described p type buried layer (13) is higher than PXing Ti district (14).
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| CN201610158757.2A CN105826367A (en) | 2016-03-18 | 2016-03-18 | Large-current silicon on insulator lateral insulated gate bipolar transistor device |
| PCT/CN2017/076687 WO2017157289A1 (en) | 2016-03-18 | 2017-03-15 | High-current silicon-on-insulator-lateral insulated gate bipolar transistor device |
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