CN105808405B - A kind of high-performance pipeline ADC frequency domain parameter assessment system based on SoPC - Google Patents

Abstract

The present invention relates to a kind of high-performance pipeline ADC frequency domain parameter assessment systems with SoPC cores in order to control, including sample collection and processing SoPC, ADC chips daughter board, Graphic Interface Control end, signal source and clock source to be assessed.Sample collection and processing SoPC configure ADC daughter boards to be assessed using Microblaze processors by daughterboard interface, cache the sample from ADC chips daughter board to be assessed using asynchronous FIFO module, are stored sample to DDR3 memories by dma controller.ADC chips daughter board to be assessed receives signal source with the signal of clock source generation as input sample signal and clock signal.Graphic Interface Control end is communicated with Microblaze processors by serial ports, receives sample, and frequency domain parameter assessment is completed in Graphic Interface Control end.The present invention uses modular method, shortens the frequency domain Performance Evaluation period, has the advantages that at low cost, easy to operate.

Description

A High Performance Pipeline ADC Frequency Domain Parameter Evaluation System Based on SoPC

technical field

The invention belongs to the field of integrated circuit testing and relates to a SoPC-based high-performance pipeline ADC frequency domain parameter evaluation system.

Background technique

With the rapid development of microelectronics technology and digital signal processing technology, the role of analog-to-digital converter (Analog-to-digital Converter, ADC) as an interface connecting the analog world and digital systems is becoming more and more obvious. Among them, the high-performance pipeline ADC is widely used in signal processing fields such as military radar communication due to its high speed and high precision; as the core component of the system, the frequency domain characteristics of the ADC often directly determine the system performance. However, due to the influence of many external factors such as the manufacturing process, the actual parameter performance of the high-performance pipeline ADC is difficult to achieve the ideal value of the design. Therefore, in order to ensure that the performance of the ADC meets the requirements, it is necessary to perform performance evaluation on it.

At present, foreign companies mostly evaluate the performance of high-performance pipeline ADCs based on dedicated automatic evaluation equipment, such as NI’s PXIe series measurement evaluation system and ADI’s dedicated ADC performance evaluation system. Such equipment is expensive and complicated to operate. The equipment cost and labor cost of the project are too high, and as the performance of the pipeline ADC continues to improve, its performance evaluation requires the evaluation system to have higher processing power. Programming devices such as microcontrollers and DSP (Digital Signal Processor) can simplify the performance parameter evaluation process. However, the evaluation system based on single-chip microcomputer has a low clock frequency, which cannot meet the characteristics of high-performance pipeline ADC with fast speed, high resolution, and large number of samples; DSP has high-speed processing capabilities, powerful and flexible interfaces and communication capabilities, but At the same time, there are also weaknesses such as insufficient control, which wastes valuable computing resources of DSP. Due to its fast clock frequency, flexible control, and rich interface resources, FPGA can meet the system requirements. Therefore, it is of great practical significance to construct a SoPC-based high-performance pipeline ADC performance evaluation system with FPGA as the carrier.

Contents of the invention

In view of the deficiencies in the prior art, the purpose of the present invention is to provide a SoPC-based high-performance pipeline ADC frequency domain parameter evaluation system, which can realize functions such as data acquisition, data deceleration, handling and storage, and utilize modular methods to make different The indexed ADC enables the actual frequency domain parameter evaluation on a common sample acquisition and processing SoPC.

The present invention realizes through following technical scheme:

A high-performance pipelined ADC frequency-domain parameter evaluation system with SoPC as the control core is characterized in that it includes a sample collection and processing SoPC, an ADC chip sub-board to be evaluated, a graphical interface control terminal, a signal source and a clock source. The sample collection and processing SoPC includes a Microblaze processor, a serial port communication module, an asynchronous FIFO module, a DMA controller, a DDR3 memory and a sub-board interface. The sample collection and processing SoPC is connected to the ADC chip sub-board to be evaluated for logic control, sample collection and processing, and connected to the graphical interface control terminal for communication and frequency domain parameter evaluation. The ADC chip sub-board to be evaluated includes an ADC chip to be evaluated, an analog input circuit, a clock management circuit, and a motherboard interface, and accepts signals generated by the signal source and the clock source as input sampling signals and clock signals. The graphical interface control terminal includes a serial port communication module, a parameter evaluation module, and a data storage module, and mainly realizes two-way communication and control with the sample collection and processing SoPC. The evaluation steps are: the Microblaze processor configures the sub-board of the ADC chip to be evaluated for sample collection through the sub-board interface, uses the asynchronous FIFO module to buffer the samples from the sub-board of the ADC chip to be evaluated, and stores the samples to DDR3 through the DMA controller memory, and then send the sample to the graphical interface control terminal for parameter evaluation.

Description of drawings

FIG. 1 is a schematic structural diagram of a SoPC-based high-performance pipeline ADC frequency-domain parameter evaluation system provided by the present invention.

Fig. 2 is a schematic diagram of a data storage path provided by the present invention.

Fig. 3 is a schematic diagram of functional modules of the ADC chip sub-board to be evaluated provided by the present invention.

Fig. 4 is a schematic diagram of the control evaluation flow provided by the present invention.

Fig. 5 is a schematic diagram of the evaluation interface of the control terminal provided by the present invention.

Detailed ways

The present invention will be further described below in conjunction with specific drawings and implementation examples.

Embodiments of the present invention relate to a SoPC-based high-performance pipelined ADC frequency-domain parameter evaluation system. As shown in FIG. Signal source and clock source. The specific steps are as follows: the Microblaze processor configures the daughter board to be evaluated through the daughter board interface to collect samples, uses the asynchronous FIFO module to buffer the samples from the daughter board of the ADC chip to be evaluated, stores the samples to the DDR3 memory through the DMA controller, and then sends the samples to Go to the GUI control terminal for parameter evaluation.

The sample acquisition and processing of the SoPC SoPC includes a Microblaze processor, a serial port communication module, an asynchronous FIFO module, a DMA controller, a DDR3 memory and a sub-board interface. The Microblaze processor is an embedded soft core applied to Xilinx FPGA. As the control core of sample collection and processing SoPC, it controls sample collection and processing other parts of SoPC through the AXI4 bus interface, including controlling the ADC chip sub-board to be evaluated, which is used for Communicate with the graphical interface control terminal, and simultaneously control the asynchronous FIFO module, DMA controller, and DDR3 memory for sample storage. The sub-board interface is used to expand the I/O of the sample acquisition and processing SoPC, and is respectively connected to the motherboard interface of the sample acquisition and processing SoPC and the ADC chip sub-board to be evaluated. It is defined by 68 user-defined single-ended signals or 34 user-defined The differential pair, serial transceiver pair, and clock structure are used to support the data transmission from the daughter board of the ADC chip to be evaluated to the sample acquisition and processing SoPC. The serial port communication module is implemented by a USB-UART interface, wherein the USB port is connected to the graphical interface control terminal, and the UART is connected to the sample collection and processing SoPC for communication between the graphical interface control terminal and the sample collection and processing SoPC and debugging. Since the clock frequency of the SoPC sample collection of the ADC chip sub-board to be evaluated cannot match the AXI4 bus rate of the sample collection and processing SoPC, an asynchronous FIFO module is required to cache the samples generated by the high-speed time domain state of the ADC chip sub-board to be evaluated to meet AXI4 bus speed. The DMA controller takes over the Microblaze processor for data transmission during the sample collection process, and is used to control the storage channel from the asynchronous FIFO module to the DDR memory, so that the Microblaze processor can be freed from heavy data handling; DDR3 memory is not only for the code In addition to providing a running space, it is also used to store the samples generated by the daughter board of the ADC chip to be evaluated. The path from sample generation to storage is shown in Figure 2: the single-ended analog signal generated by the clock source enters the analog input circuit to generate an analog differential signal, and then enters the ADC chip to be evaluated for A/D conversion to output a digital differential signal. After the delay, it is combined into the final required digital data; after being buffered by the asynchronous FIFO module, it is sent to the DDR3 memory through the DMA controller. Each sub-board of the ADC chip to be evaluated has its own DMA channel. When there are multiple ADC chips to be evaluated, it is only necessary to add its own dedicated channel for each ADC chip to be evaluated.

The functional module connection relationship of the ADC chip sub-board to be evaluated is as shown in Figure 3, including an ADC chip to be evaluated, an analog input circuit, and a clock management circuit; the ADC chip sub-board to be evaluated is connected to the sample collection through a motherboard interface It is connected with the processing SoPC and receives the signals from the signal source and the clock source as the sampling signal and the clock signal; the analog input circuit is used as the buffer of the ADC chip to be evaluated, and the signal generator inputs the high-purity single-ended analog signal after filtering, After being converted and amplified by the analog input circuit, the differential signal is output to the ADC chip to be evaluated for A/D conversion; the clock management circuit is connected to the ADC chip to be evaluated and the clock source, and provides a programmable clock signal for the ADC chip to be evaluated.

The graphical interface control terminal is developed by Labview, including a serial port communication module, an evaluation module, and a data storage module, which are used to communicate with the sample collection and processing SoPC, data collection, transmission and performance evaluation, and its control flow is shown in Figure 4 shown. After the serial port communication module is initialized and the relevant communication parameters are set, the graphical interface control terminal and the sample collection and processing SoPC start to communicate at this time. If the signal that the sample collection and processing SoPC is ready is received, it can be controlled on the graphical interface The graphical interface of the terminal is used for subsequent operations; the specific interface of the graphical interface control terminal is shown in Figure 5. Before the program starts, relevant settings for data sampling need to be set, including conversion accuracy, sampling rate, evaluation algorithm, etc.; after starting the program, wait for the described To evaluate the successful initialization of the ADC chip sub-board, the corresponding sine wave diagram will be displayed along with the received time domain diagram of the sampled data, and the frequency domain characteristic evaluation can be completed by clicking on the performance evaluation.

Finally, it is noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out Modifications or equivalent replacements without departing from the spirit and scope of the technical solution of the present invention shall be covered by the claims of the present invention.

Claims (1)

1. a kind of high-performance pipeline ADC frequency domain parameter assessment system with SoPC cores in order to control, it is characterised in that：Including sample This acquisition and processing SoPC, ADC chips daughter board, Graphic Interface Control end, signal source and clock source to be assessed；

The sample collection and processing SoPC include Microblaze processors, serial communication modular, asynchronous FIFO module, DMA Controller, DDR3 memories and daughterboard interface；The asynchronous FIFO module is for caching high-speed time domain state ADC chips to be assessed The sample that daughter board generates so that clock frequency when the ADC chips daughter board sample collection to be assessed and the sample collection and Handle the AXI4 Bus Speeds matching of SoPC；The dma controller is deposited for controlling the asynchronous FIFO module to the DDR3 The memory channel of reservoir, take over Microblaze processors carry out data transmission in sample collection procedure；The daughterboard interface For extending sample collection and handling the I/O of SoPC, by 68 user-defined single-ended signals or 34 user-defined differences Point to and serial transceiver, clock is constituted, for support the ADC chips daughter board to be assessed to the sample collection with Handle the data transmission of SoPC；

The ADC chips daughter board to be assessed includes that ADC chips, analog input circuit, clock management circuits and motherboard to be assessed connect Mouthful, receive signal source with the signal of clock source generation as input sample signal and clock signal；The analog input circuit is made For the buffer of ADC chips to be assessed, the single-ended analog signal of high-purity is inputted after filtered by signal generator, by simulation Output difference signal to ADC chips to be assessed carry out analog-to-digital conversion after the conversion of input circuit, amplification；The Clock management electricity Road is connected with ADC chips to be assessed and clock source, and programmable clock signal is provided for ADC chips to be assessed；Figure circle Face control terminal, including serial communication modular, parameter evaluation module, data memory module；The Graphic Interface Control end, assessment When ADC chips, parameter setting, including conversion accuracy, sample rate, assessment algorithm first are carried out to the ADC chips daughter board to be assessed, It then waits for the ADC chips daughter board to be assessed and initializes successful information, sampled data is then received by serial ports, data connect By after, clicks performance evaluating and frequency domain characteristic assessment can be completed；

The sample collection and processing SoPC are connected by daughterboard interface with the motherboard interface of the ADC chips daughter board to be assessed, Realize logic control, sample collection and the processing to carrying out the ADC chips daughter board to be assessed；

The serial communication modular phase of the serial communication modular and the Graphic Interface Control end of the sample collection and processing SoPC Even, it realizes the sample collection and handles the two-way communication and control of SoPC and the Graphic Interface Control end；

Appraisal procedure is：Microblaze processors configure the ADC chips daughter board to be assessed by daughterboard interface and carry out sample Acquisition caches the sample from the ADC chips daughter board to be assessed using the asynchronous FIFO module, is controlled by the DMA Device stores sample to the DDR3 memories, then send sample to the Graphic Interface Control end and carries out parameter evaluation.