CN105790887A - Method and device for generating parallel CRC values for packets - Google Patents
Method and device for generating parallel CRC values for packets Download PDFInfo
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- CN105790887A CN105790887A CN201410828923.6A CN201410828923A CN105790887A CN 105790887 A CN105790887 A CN 105790887A CN 201410828923 A CN201410828923 A CN 201410828923A CN 105790887 A CN105790887 A CN 105790887A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004364 calculation method Methods 0.000 claims abstract description 13
- 238000010009 beating Methods 0.000 claims description 4
- 230000002612 cardiopulmonary effect Effects 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims description 4
- 125000004122 cyclic group Chemical group 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 238000004422 calculation algorithm Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
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Abstract
The invention provides a method and device for generating parallel CRC values for packets. The packets comprise at least one data byte. The method comprises following steps of adding one or more filling bytes in the data bytes of the packets, thus enabling the lengths of the added filling bytes and the data bytes to be divided by a maximum valid byte width exactly; selecting an initial value according to the remainders obtained through division of the lengths of the data bytes by the maximum valid byte width; and calculating the CRC values for the packets according to the initial value, the data bytes and the filling bytes. According to the method and the device, only one CRC calculation circuit can be used for generating the parallel CRC values for the packets, and the demanded circuit structure can be greatly simplified.
Description
Technical field
The present invention relates generally to communication network.More specifically it relates to a kind of method and apparatus for generating cardiopulmonary bypass in beating heart redundancy check (CRC) value for packet.
Background technology
When transmitting packet in a network, for instance when transmitting in Fast Ethernet, in order to reduce the operating frequency of system clock, grouped data parallel width is typically greater than a byte.Such as, in 10G Ethernet, packet has 8 actual blocked bytes as input data, and packet has 80 bytes in 100G Ethernet.But, the length owing to being grouped in ethernet networks is not fixing, and at the end position place of packet, not all byte must be all effective byte.This makes to meet system requirements for the Parallel CRC computational algorithm of fixed byte width.
A kind of traditional method is to adopt the multi-set parallel CRC counting circuit with different input byte wide simultaneously run.Such as, as illustrated in fig. 1 and 2, in 100G Ethernet, having 80 groups of CRC parallel computation circuit, it calculates a byte, two bytes respectively ... until the input data of the packet of 80 bytes.Before the end position of packet, calculate the crc value of all bytes and be chosen as always and currently export result.But when concluding ending (EOP) that (assert) is grouped, according to number data bytes, in all CRC value of calculation is chosen as final result, and is then inserted in Frame Check Sequence (FCS) field of packet.The shortcoming of this method clearly as organize the CRC a large amount of logical resource of counting circuit consumption more so that design complexity.
The initial value that CRC calculates is 0xFFFFFFFF.CRC counting circuit is started working time (SOP) from ETH packet.Before concluding ETHSOP, ETHMOD is fixed as constant binary number 1001111 (i.e. decimal number 79), it means that all bytes of packet are all effective.Therefore, select to calculate the CRC counting circuit of 80 bytes always.When concluding ETHEOP, namely in the end position of packet, the quantity according to the data byte of packet, the selected output of CRC value of calculation is as final result.Such as, in ETHEOP time slot, if ETHMOD is equal to 0, then CRC32 (1 byte) module is chosen output value of calculation as final CRC result；If equal to 78, then CRC32 (79 byte) selected output value of calculation is as final CRC result.
Summary of the invention
The present invention relates to a kind of method and apparatus for generating crc value for packet.
According to the first aspect of the invention, it is provided that a kind of method for generating crc value for packet, this packet includes at least one data byte, and described method includes:
One or more byte of paddings are added the data byte of described packet to so that the length of the byte of padding that adds and described data byte can be divided exactly by maximum effective byte width；
Length according to described data byte selects initial value divided by the remainder of described maximum effective byte width；And
To calculate described crc value for described packet according to described initial value and described data byte and described byte of padding.
According to the first aspect of the invention, it is provided that a kind of equipment for generating Parallel CRC value for packet, this packet includes at least one data byte, and described equipment includes:
Adding set, is configured to one or more byte of paddings add to the data byte of described packet so that the length of the byte of padding that adds and described data byte can be divided exactly by maximum effective byte width；
Select device, be configured to length according to described data byte and select initial value divided by the remainder of described maximum effective byte width；And
Calculation element, is configured to calculate described crc value for described packet according to described initial value and described data byte and described byte of padding.
In an exemplary embodiment of the present invention embodiment, the method and apparatus provided can use only one CRC counting circuit, the 80 groups of CRC parallel computation circuit used in prior art, it is used for generating Parallel CRC value to packet, this can be greatly simplified required circuit structure, saves the circuit logic resource for hardware designs (such as ASIC or FPGA design).
Accompanying drawing explanation
In conjunction with the following drawings by described in detail below to embodiment of reference read, it is possible to be more fully understood that the present invention, its mode and further purpose are preferably used, in the drawing:
Fig. 1 shows the typical sequential chart in prior art for the packet of 100G Ethernet；
Fig. 2 shows the CRC computing block diagram of 100G Ethernet packet in prior art；
Fig. 3 shows according to the embodiment of the present invention for calculating the flow chart of the method for Parallel CRC value for packet；
Fig. 4 shows the typical sequential chart of packet for 100G Ethernet according to the embodiment of the present invention；
Fig. 5 shows the CRC computing block diagram of the packet of 100G Ethernet according to the embodiment of the present invention；And
Fig. 6 exemplarily shows the block diagram of the equipment for calculating Parallel CRC value for packet according to the embodiment of the present invention.
Detailed description of the invention
Embodiments of the present invention are described in detail with reference to the accompanying drawings.It is not meant to, with reference to the feature of entire disclosure, advantage or similar language, all feature and advantage that the present invention is capable of and all should adopt the arbitrary single embodiment of the present invention.The language relating to described feature and advantage should be understood to mean to include at least one embodiment of the present invention in conjunction with the special characteristic of an embodiment description, advantage or characteristic.Additionally, described inventive feature, advantage and characteristic can merge in any suitable way in one or more embodiments.Those skilled in the relevant art will recognize that and can realize the present invention when not using one or more certain features or the advantage of a particular implementation.In other examples, will be consequently realised that the other feature and advantage that can not occur in all of the embodiments of the present invention in some embodiments.
As shown in Figure 3, the invention provides a kind of method for generating cardiopulmonary bypass in beating heart redundancy check (CRC) value for packet, this packet includes at least one data byte, said method comprising the steps of: in step S101, one or more byte of paddings are added the data byte of described packet to so that the length of the byte of padding that adds and described data byte can be divided exactly by maximum effective byte width, this maximum effective byte width can set according to network, such as 10G Ethernet, maximum effective byte width can set that to be 8, for 100G Ethernet, maximum effective byte width can set that to be 80, wherein byte of padding can be such as zero byte, i.e. " 0 " byte, this zero byte can be all-zero word joint；In step S102, length according to described data byte selects initial value divided by the remainder of described maximum effective byte width, specifically, calculate the length (namely not there is the length of the actually active blocked byte of the packet of zero byte of interpolation) of described data byte divided by described maximum effective byte width, and select initial value according to calculated remainder；And in step S103, to calculate described crc value for described packet according to described initial value and described data byte and described byte of padding.Then calculated crc value can be added to the FCS field of packet, and then packet and its crc value can be sent collectively to destination.
In one embodiment, described crc value is calculated by only one CRC counting circuit.
In one embodiment, before the one or more byte of padding is placed on described data byte.
Thus, method provided by the invention can use only one CRC counting circuit, rather than the 80 groups of CRC parallel computation circuit used in prior art, to generate Parallel CRC value for packet, this can be greatly simplified the structure of circuit, saves the logical resource for hardware designs (such as ASIC or FPGA design).It will be appreciated by those skilled in the art that the present invention can also be applied to calculate crc value into more than one packet.
In the emitting side of Ethernet packet, before sending packets, the length of packet is for commonly known emitting side.Such as, when emitting side generates new packet, block length is to configure from the upper layer software (applications) of emitting side；When being grouped through emitting side or forwarding in emitting side, whole packet intactly stores in a buffer, and thus, the length of packet is also known.
Therefore, before one group of zero byte is placed in the blocked byte (ranging for from 0 to (maximum effective byte width-1) of the quantity of zero byte) of reality, so that " newly " length including the packet of zero byte and the actual blocked byte added can be divided exactly by maximum effective byte width.After such processing, equipment only needs one group of CRC circuit to calculate crc value for any number of blocked byte.Such as, for 10G Ethernet, it is only necessary to the CRC counting circuit of one 8 input byte to calculate crc value for packet；For 80G Ethernet, it is only necessary to the CRC counting circuit of one 80 input byte to calculate crc value for packet.The actual packet byte of packet can be the valid data of packet.
In an illustrative embodiments, step S102 may include that and finds described initial value in a lookup table, and this look-up table has possible quantity and its initial value being associated of described byte of padding.
In an illustrative embodiments, the acquiescence initial value used when described initial value is not have byte of padding in the quantity considering described byte of padding and described packet calculates.
Described initial value can be predetermined, and stores in memory, for instance is stored in read only memory (ROM).It practice, described remainder can correspond to the quantity of zero byte, for instance, in 100G Ethernet, if remainder is 0, then need not add zero byte；If remainder is 1, then mean to add 79 zero bytes.
The initial value of IEEE802.3 protocol definition CRC32 is not complete zero, but 0xFFFFFFFF.Therefore, before the data byte for packet calculates crc value, zero byte added will affect final result of calculation.But, according to the CRC principle calculated, if the data byte of original CRC value and packet (as input data) is known, then unique during result.Thus, system can set that zero byte added in packet header is compensated by different initial values.Initial value can be stored in the look-up table in ROM.When a packet is sent, CRC counting circuit searches the look-up table in ROM according to the length of the data byte of packet divided by the remainder of maximum effective byte width, and selects suitable initial value.Then CRC counting circuit can to calculate final crc value for packet according to the data byte of described initial value and packet.
Different initial values can be determined according to many algorithms, for instance, when byte of padding is zero byte, a kind of computational algorithm can be exemplarily expressed as follows by hardware description language Verilog:
Although algorithm here is only provide for the situation that byte of padding is zero byte it should be appreciated that based on the teachings of the present invention, it is possible to some algorithms can realize for non-zero byte.
The quantity of initial value and zero corresponding byte can exemplarily show in table 1 below.
Table 1
| The quantity of zero byte | CRC initial value |
| 0 | 0xFFFFFFFF |
| 1 | 0x9BF1A90F |
| 2 | 0x09B93859 |
| 3 | 0x816474C5 |
| 4 | 0x46AF6449 |
| 5 | 0x339FDE2F |
| … | … |
| 78 | 0xCF8B3345 |
| 79 | 0xC48105D5 |
In an exemplary embodiment, crc value can be calculated by only one CRC counting circuit, rather than use in prior art 80 groups of CRC counting circuits, thus enormously simplify the structure of CRC counting circuit.
Such as, in 100G Ethernet, only have parallel computation 80 and input the CRC circuit of byte.The length of the data byte of packet divided by 80 the reading address of the remainder corresponding initial value that is counted as in described look-up table.Such as, if remainder is 0, then without zero byte, initial value is complete 1；If remainder is 1, then meaning that 79 zero bytes should be added and calculate together with data byte, initial value is 0xC48105D5.
In an exemplary embodiment, the reading address of the corresponding initial value that remainder is counted as in described look-up table, and required suitable initial value can find according to computed remainder.
In an exemplary embodiment, before the one or more byte of padding is placed on described data byte, preferably, the one or more byte of padding is placed on the higher bit position in described packet, and at least one data byte described is placed on the low bit position in described packet.
In an exemplary embodiment, the method according to the invention can also include: before step S101, receives packet.Specifically, the step receiving packet may comprise steps of: receives the first signal (such as CLK signal), this periodic clock signal of the first signal designation；Receiving secondary signal (such as VALID signal), this secondary signal instruction data byte arrives；The 3rd signal (such as SOP signal) is concluded, the beginning of data byte described in the 3rd signal designation when receiving described secondary signal；Start to receive the 4th signal (such as DATA signal) from the time concluding described 3rd signal and be used as described data byte, until concluding the 5th signal (such as eop signal), the end of data byte described in the 5th signal designation.
Fig. 4 shows the typical sequential chart of packet for 100G Ethernet according to the embodiment of the present invention.As shown in Figure 4, there occurs change according to the sequential chart of the present invention compared with the prior art of display in Fig. 1.It is different in that, it is no longer necessary to signal ETHMOD.It addition, when concluding ETHSOP, ETHDATA includes zero byte and the data byte that add.Zero byte is placed on the higher bit position of packet, and the blocked byte of reality is placed on the low bit position of packet.
Fig. 5 shows the CRC computing block diagram of the packet of 100G Ethernet according to the embodiment of the present invention.It can be seen that owing to only used a CRC counting circuit, the circuit structure that the present invention needs is simplified compared with the circuit structure of the prior art of display in Fig. 2.
Fig. 6 exemplarily shows the equipment for calculating Parallel CRC value for packet according to the embodiment of the present invention.
As shown in Figure 6, present invention also offers a kind of equipment for generating cardiopulmonary bypass in beating heart redundancy check (CRC) value for packet, this packet includes at least one data byte, described equipment may include that adding set 610, the length of the byte of padding that adds and described data byte it is configured to one or more byte of paddings (such as " 0 " byte) add to the data byte of described packet so that can be divided exactly by maximum effective byte width, this maximum effective width can be set as arbitrary value as required, for instance 8 or 80；Select device 620, be configured to length according to described data byte and select initial value divided by the remainder of described maximum effective byte width；And calculation element 630, it is configured to calculate described crc value for described packet according to described initial value and described data byte and described byte of padding.
In an illustrative embodiments, described equipment can also include look-up table, and this look-up table has possible quantity and its initial value being associated of described byte of padding, and wherein said selection device is configured to find described initial value in a lookup table.
In an illustrative embodiments, described calculation element includes only one CRC counting circuit.
In an illustrative embodiments, the acquiescence initial value used when described initial value is not have byte of padding in the quantity considering described byte of padding and described packet calculates.
In an illustrative embodiments, the reading address of the corresponding initial value that described remainder is counted as in described look-up table.
In an illustrative embodiments, described equipment can also include: receiving device, be configured to receive described packet, it is configured to: receive the first signal (such as CLK signal), this periodic clock signal of the first signal designation；Receiving secondary signal (such as VALID signal), this secondary signal instruction data byte arrives；The 3rd signal (such as SOP signal) is concluded, the beginning of data byte described in the 3rd signal designation when receiving described secondary signal；Start to receive the 4th signal (such as DATA signal) from the time concluding described 3rd signal and be used as described data byte, until concluding the 5th signal (such as eop signal), the end of data byte described in the 5th signal designation.
In an illustrative embodiments, before the one or more byte of padding is placed on described data byte, preferably the one or more byte of padding is placed on the higher bit position in described packet, and at least one data byte described is placed on the low bit position in described packet.
Owing to only used a CRC counting circuit, the circuit structure in described equipment is very simple, so can save the circuit logic resource for hardware designs (such as ASIC or FPGA design).
As long as having emitting side and largest packet byte wide in equipment more than 1, the method for the present invention is exactly useful for a user.Except Fast Ethernet, described method can be applicable to arbitrarily other networks, the situation that especially block length is variable and initial value is not zero.
At least one in adding set 610, selection device 620, calculation element 630 and reception device is envisioned for and includes following procedure instruction, when this programmed instruction is performed, it is possible to make described equipment operate according to illustrative embodiments as above.Any device in above-mentioned adding set 610, selection device 620, calculation element 630 and reception device can integrate to live and be realized by the assembly separated, and can be suitable in local technical environment any type of, as nonrestrictive example, it can include general purpose computer, special-purpose computer, microprocessor, digital signal processor (DSP) and based on one or more in the processor of polycaryon processor framework.Above-mentioned ROM can be any type of of applicable local technical environment, and the data storage technology that can use any appropriate realizes, for instance based on the quasiconductor of storage device, flash memory, magnetic storage apparatus and system, light storage device and system, read-only storage and removable memorizer.
In general, each illustrative embodiments can realize by hardware or special circuit, software, logic or its combination in any.Such as, some aspects can realize with hardware, and other aspects can realize with firmware or the software that can be performed by controller, microprocessor or other computing equipments, but the present invention is not limited to this.Although the various aspects of the illustrative embodiments of the present invention can arbitrarily representing of other diagrams describes with block diagram, flow chart or use, it is to be understood that, as nonrestrictive example, these frames described herein, equipment, system, technology or method can be realized by hardware, software, firmware, special circuit or logic, common hardware or controller or other computing equipments or its combination.
Be to be understood that the present invention illustrative embodiments at least some aspect can by one or more computers or other set redundant computer executable instruction (such as one or more program modules) and realize.In general, program module includes performing particular task when being run by the processor in computer or other equipment or implementing the thread of particular abstract data type, program, object, assembly, data structure etc..The executable instruction of computer can be stored on computer readable medium, for instance is stored in hard disk, CD, removable storage medium, solid-state memory, random access storage device (RAM) etc..It will be appreciated by the appropriately skilled person that the function of program module or can be separated in middle merging as needed in each embodiment.It addition, described function can as realizing in whole or in part in firmware or hardware equivalent (such as integrated circuit, field programmable gate array (FPGA) etc.).
Although having been disclosed for only certain exemplary embodiments of this invention, but skilled artisans appreciate that when without departing substantially from the spirit and scope of the present invention, it is possible to particular implementation is changed.Therefore the scope of the present invention is not limited to particular implementation, its objective is that appended claim covers any and all this application, amendment and embodiment in the scope of the invention.
Claims (18)
1. the method for generating parallel cyclic redundancy check (CRC) (CRC) value for packet, this packet includes at least one data byte, and described method includes:
One or more byte of paddings are added the data byte of described packet to so that the length of the byte of padding that adds and described data byte can be divided exactly by maximum effective byte width；
Length according to described data byte selects initial value divided by the remainder of described maximum effective byte width；And
To calculate described crc value for described packet according to described initial value and described data byte and described byte of padding.
2. method according to claim 1, the step of wherein said selection includes:
Finding described initial value in a lookup table, this look-up table has possible quantity and its initial value being associated of described byte of padding.
3. method according to claim 1 and 2, wherein said byte of padding is " 0 " byte.
4. the method according to any claim in claims 1 to 3, the acquiescence initial value used when wherein said initial value is not have byte of padding in the quantity considering described byte of padding and described packet calculates.
5. the method according to any claim in Claims 1-4, wherein said crc value is calculated by only one CRC counting circuit.
6. the method according to any claim in claim 1 to 5, the reading address of the corresponding initial value that wherein said remainder is counted as in described look-up table.
7. the method according to any claim in claim 1 to 6, the method also includes:
Before described interpolation step, receiving described packet, it farther includes:
Receive the first signal, this periodic clock signal of the first signal designation；
Receiving secondary signal, this secondary signal instruction data byte arrives；
The 3rd signal is concluded, the beginning of data byte described in the 3rd signal designation when receiving described secondary signal；
Start to receive the 4th signal from the time concluding described 3rd signal and be used as described data byte, until concluding the 5th signal, the end of data byte described in the 5th signal designation.
8. the method according to any claim in claim 1 to 7, before wherein said one or more byte of paddings are placed on described data byte.
9. method according to claim 8, wherein said one or more byte of paddings are placed on the higher bit position in described packet, and at least one data byte described is placed on the low bit position in described packet.
10., for generating an equipment for cardiopulmonary bypass in beating heart redundancy check (CRC) value for packet, this packet includes at least one data byte, and described equipment includes:
Adding set, is configured to one or more byte of paddings add to the data byte of described packet so that the length of the byte of padding that adds and described data byte can be divided exactly by maximum effective byte width；
Select device, be configured to length according to described data byte and select initial value divided by the remainder of described maximum effective byte width；And
Calculation element, is configured to calculate described crc value for described packet according to described initial value and described data byte and described byte of padding.
11. equipment according to claim 10, wherein this equipment also includes look-up table, and this look-up table has possible quantity and its initial value being associated of described byte of padding, and wherein said selection device is configured to find described initial value in a lookup table.
12. the equipment according to claim 10 or 11, wherein said byte of padding is " 0 " byte.
13. the equipment according to any claim in claim 10 to 12, the acquiescence initial value used when wherein said initial value is not have byte of padding in the quantity considering described byte of padding and described packet calculates.
14. the equipment according to any claim in claim 10 to 13, wherein said calculation element includes only one CRC counting circuit.
15. the equipment according to any claim in claim 10 to 14, the reading address of the corresponding initial value that wherein said remainder is counted as in described look-up table.
16. the equipment according to any claim in claim 10 to 15, this equipment also includes:
Receiving device, be configured to receive described packet, it is configured to:
Receive the first signal, this periodic clock signal of the first signal designation；
Receiving secondary signal, this secondary signal instruction data byte arrives；
The 3rd signal is concluded, the beginning of data byte described in the 3rd signal designation when receiving described secondary signal；
Start to receive the 4th signal from the time concluding described 3rd signal and be used as described data byte, until concluding the 5th signal, the end of data byte described in the 5th signal designation.
17. the equipment according to any claim in claim 10 to 16, before wherein said one or more byte of paddings are placed on described data byte.
18. equipment according to claim 17, wherein said one or more byte of paddings are placed on the higher bit position in described packet, and at least one data byte described is placed on the low bit position in described packet.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410828923.6A CN105790887A (en) | 2014-12-26 | 2014-12-26 | Method and device for generating parallel CRC values for packets |
| PCT/IB2015/002256 WO2016103015A1 (en) | 2014-12-26 | 2015-11-09 | A method and apparatus for generating a crc value for a packet |
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| CN201410828923.6A CN105790887A (en) | 2014-12-26 | 2014-12-26 | Method and device for generating parallel CRC values for packets |
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| CN201410828923.6A Pending CN105790887A (en) | 2014-12-26 | 2014-12-26 | Method and device for generating parallel CRC values for packets |
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Cited By (3)
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| CN111385269A (en) * | 2018-12-29 | 2020-07-07 | 广州市百果园网络科技有限公司 | Data transmission method and device |
| CN111800223A (en) * | 2019-08-15 | 2020-10-20 | 北京京东尚科信息技术有限公司 | Method, device and system for generating sending message and processing receiving message |
| CN113190376A (en) * | 2021-05-10 | 2021-07-30 | 天津光电通信技术有限公司 | Method for checking FCS value of 100GE data packet |
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| US7577895B2 (en) * | 2004-09-30 | 2009-08-18 | Intel Corporation | Initialization seed to allow data padding for cyclic redundancy code calculation |
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| US7577895B2 (en) * | 2004-09-30 | 2009-08-18 | Intel Corporation | Initialization seed to allow data padding for cyclic redundancy code calculation |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111385269A (en) * | 2018-12-29 | 2020-07-07 | 广州市百果园网络科技有限公司 | Data transmission method and device |
| CN111800223A (en) * | 2019-08-15 | 2020-10-20 | 北京京东尚科信息技术有限公司 | Method, device and system for generating sending message and processing receiving message |
| CN113190376A (en) * | 2021-05-10 | 2021-07-30 | 天津光电通信技术有限公司 | Method for checking FCS value of 100GE data packet |
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| WO2016103015A1 (en) | 2016-06-30 |
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