CN105589993A - Microprocessor function verification apparatus and microprocessor function verification method - Google Patents
Microprocessor function verification apparatus and microprocessor function verification method Download PDFInfo
- Publication number
- CN105589993A CN105589993A CN201510959069.1A CN201510959069A CN105589993A CN 105589993 A CN105589993 A CN 105589993A CN 201510959069 A CN201510959069 A CN 201510959069A CN 105589993 A CN105589993 A CN 105589993A
- Authority
- CN
- China
- Prior art keywords
- verified
- design
- reference data
- unit
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012795 verification Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims description 25
- 238000013461 design Methods 0.000 claims abstract description 84
- 238000004088 simulation Methods 0.000 claims abstract description 8
- 230000006399 behavior Effects 0.000 claims description 32
- 230000006870 function Effects 0.000 claims description 30
- 230000002159 abnormal effect Effects 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 8
- 238000012546 transfer Methods 0.000 claims description 6
- 241001269238 Data Species 0.000 claims description 5
- 235000013399 edible fruits Nutrition 0.000 claims description 2
- 230000000737 periodic effect Effects 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000007689 inspection Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 241000931705 Cicada Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011019 functional design specification Methods 0.000 description 1
- 208000037805 labour Diseases 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000284 resting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a microprocessor function verification device, comprising: the system comprises an instruction set simulator, a comparator, a monitor, an input interface and an RTL model; the instruction set simulator is used for executing the test program to generate a staged reference data file; a comparator for reading a staged reference data file from the instruction set emulator; the input interface is used for loading a test program to a storage unit of a design to be verified; the monitor is used for capturing a signal to be verified in the simulation of the design to be verified and outputting the signal to be verified to the comparator; the comparator is also used for comparing whether the reference data in the periodic reference data file is consistent with the signal to be verified or not; and the RTL model is used for reading partial internal signals of the design to be verified from the design to be verified cycle by cycle so as to judge whether the behavior of the design to be verified is consistent with that of the RTL model. The technical problem that the function checking efficiency of the design to be verified is low in the prior art is effectively solved, so that efficient and quick function checking is realized, and the verifying efficiency is finally improved.
Description
Technical field
The present invention relates to lsi development technical field, relate in particular to a kind of verifying function of microprocessor equipmentAnd Microprocessor Function Verification Method.
Background technology
The level of informatization of human society improves constantly along with the develop rapidly of electronic information technology, as electricityThe integrated circuit technique of sub-Information Technology Foundation, its exponential growth trend is to promote electronic information technology to flyOne of important source power that speed increases. Point out according to the prediction address of international semiconductor technology path blueprint, from2013 to 2026, the integrated level of microprocessor and high-performance ASIC will be with the speed of doubling for 3 yearsDegree increases. But the integrated circuit verification ability that this just seriously lags behind Design and manufacture ability, will run intoUnprecedented huge challenge. Wherein, functional verification is again stage of labor intensive and material resources the most in checking.Can estimate, functional verification will be the bottleneck in the whole microprocessor Design cycle.
What the object of functional verification was the behavior of guaranteeing design to be verified with Functional Design specification is consistent. Therefore,The result checking mechanism of design to be verified is unusual the key link in functional verification. Result checking mechanism comprisesRun through the inspection of whole test program, i.e. real-time inspection, also has the directly knot of the test after test program finishesBundle checks. Rely on manual observation judgement need to expend a large amount of expert's time, and easily make mistakes, particularly rightIn the time that Output rusults is numerous, this method can not be suitable for completely. At present, use the reference mould of design to be verifiedType checking is the most convenient, and approaches the method for complete function most. But reference model complexity, base at presentQuantities in the functional verification of reference model is large, therefore low to the functional check efficiency of design to be verified.
Summary of the invention
The embodiment of the present invention is by providing a kind of verifying function of microprocessor equipment and verifying function of microprocessorMethod, has solved prior art to the inefficient technical problem of the functional check of design to be verified.
First aspect, the embodiment of the present invention provides a kind of verifying function of microprocessor equipment, comprising: instructionCollection emulator, comparator, monitor, input interface, RTL model;
Described isa simulator, produces interim reference data file for carrying out test program;
Described comparator, for reading described interim reference data file from described isa simulator;
Described input interface, for loading the memory cell of described test program to design to be verified;
Described monitor, exports to described ratio for catching the signal to be verified of described design and simulation to be verifiedCompared with device;
Described comparator, also for by the reference data of described interim reference data file and described to be testedWhether card signal contrasts consistent;
Described RTL model, reads the portion of described design to be verified from described design to be verified for Cycle by CyclePoint internal signal, with the behavior of carrying out design to be verified described in ruling whether with the behavior of described RTL modelUnanimously.
Preferably, described RTL model comprises: instruction Dispatching Unit, performance element, writes back unit, differentNormal generation unit, programmed counting generation unit, bypass model unit, register-memory model unit,Ruling unit;
Described instruction Dispatching Unit, for reading relevant signal place by described partial interior signal and instructionManage into classification instruction code and output to described performance element;
Described register-memory model unit, for simulating writing of described design to be verified based on writing back informationReturn function, the pipelining-stage information of writing register is outputed to described register bypass model unit, and will write and postThe value of storage or the value of memory write output to described performance element;
Described register bypass model unit, for reading, to write the value of read register defeated according to the constraint of pipelining-stageGo out to described performance element;
Described performance element, for simulating the execution process instruction of described design to be verified, carries out knot by instructionDescribed in outputing to, fruit writes back unit, described abnormal generation unit and described programmed counting generation unit;
The described unit that writes back, for based on writing the value of register or the value of memory write, exports current period instituteDescribed in needing, write back information described register-memory model unit and described ruling unit;
Described abnormal generation unit, for judge according to described instruction execution result current whether should produce differentOften, and by abnormal judged result output to described ruling unit;
Described programmed counting generation unit, for judging the current redirect that whether has according to described instruction execution resultOccur, and redirect judged result is outputed to described ruling unit;
Described ruling unit, for will described in write back information, described abnormal judged result, described redirect judgementResult and described partial interior signal contrast, thus whether ruling goes out the behavior of described design to be verified with describedThe behavior of RTL model is consistent.
Second aspect, the embodiment of the present invention also provides a kind of Microprocessor Function Verification Method, comprising:
S1: carry out test program by isa simulator and produce interim reference data file;
S2: starting described design to be verified and RTL model, to carry out register transfer grade simulated, by monitoringThe signal to be verified that device catches in described design and simulation to be verified outputs to described comparator;
S3: described comparator reads current group of reference data from described interim reference data file;
S4: described RTL model Cycle by Cycle reading section internal signal from described design to be verified, to enterDescribed in row ruling, whether the behavior of design to be verified consistent with the behavior of described RTL model, if carry outS5, otherwise emulation finishes;
S5: in the time arriving the interim checkpoint of comparator, the more described current group of reference number of described comparatorAccording to whether consistent with the current signal described to be verified capturing, be to carry out S6, otherwise emulation finish;
S6: judge whether emulation finishes at this point, if emulation finishes, otherwise return to S3.
Preferably, in described S4, described RTL model Cycle by Cycle reading part from described design to be verifiedPoint internal signal, with the behavior of carrying out design to be verified described in ruling whether with the behavior of described RTL modelUnanimously, comprising:
Described RTL model reads described partial interior letter from described design to be verified in each emulation cycleNumber;
Described RTL model is by described partial interior signal and the inner data that self produce of described RTL modelContrast;
The behavior that RTL model judges described design to be verified according to comparing result whether with described RTL modelBehavior consistent.
Preferably, in described S1, describedly carry out test program by isa simulator and produce interimAfter reference data file, also comprise:
Described interim reference data file is loaded into described comparator;
Described comparator is divided described interim reference data file according to whether comprising specified formatBecome many group reference datas, wherein, described specified format comprises relatively mark.
Preferably, in described S5, the more described current group of reference data of described comparator and current seizureWhether the signal described to be verified arriving is consistent, comprising:
Described comparator judges in described current group of reference data, whether there is described relatively mark;
If there is described relatively mark in described current group of reference data, show to arrive described interim inspectionPoint.
Preferably, in described S6, describedly judge that whether emulation finishes at this point, is specially:
Input described test program to described design to be verified and finish, being judged as emulation need to finish at this point.
The one or more technical schemes that provide in the embodiment of the present invention, at least have following technique effect or excellentPoint:
1, comprise isa simulator owing to having adopted, comparator, monitor, input interface, RTL modelVerifying function of microprocessor equipment, reduced the complexity of reference model, the function based on reference model is testedThe quantities of card is dwindled greatly, on the one hand: comparator is not just comparing operation less than interim test point,Therefore saved the simulation time expending when comparator does consistent inspection, on the other hand: RTL model is each imitativeTrue cycle all does real-time comparison from design reading section internal signal to be verified, and comparator the cycle reads one by oneGetting one group of signal to be verified and reference data and contrast, is all in the time that discovery is inconsistent, just to have feedback, because ofThe combination of this this two aspects has effectively ensured to find fast the mistake in design to be verified, therefore efficient solutionDetermine in prior art to the inefficient technical problem of the functional check of design to be verified, thereby realized efficientFunctional check fast, has finally improved verification efficiency.
2, because making real-time comparison and instruction collection emulator, RTL model provide reference data to do for comparatorThe consistent double shield checking, thus the degree of accuracy to the existing location of mistake of design to be verified ensured.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will be to implementingIn example or description of the Prior Art, the accompanying drawing of required use is briefly described, and apparently, the following describesIn accompanying drawing be only embodiments of the invention, for those of ordinary skill in the art, do not paying woundUnder the prerequisite of the property made work, can also obtain according to the accompanying drawing providing other accompanying drawing.
Fig. 1 is the general frame of verifying function of microprocessor equipment in the embodiment of the present invention;
Fig. 2 is the internal structure block diagram of RTL model in the embodiment of the present invention;
Fig. 3 is the flow chart of Microprocessor Function Verification Method in the embodiment of the present invention.
Detailed description of the invention
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the present inventionAccompanying drawing in embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention, obviously,Described embodiment is the present invention's part embodiment, instead of whole embodiment. In the present inventionEmbodiment, those of ordinary skill in the art do not make under creative work prerequisite, obtain all itsHis embodiment, belongs to the scope of protection of the invention.
Shown in figure 1, a kind of verifying function of microprocessor equipment that the embodiment of the present invention provides, comprising:Isa simulator (ISS, InstructionSetSimulator) 1, comparator 2, monitor 3, input interface4, RTL (RegisterTransferLevel, Method at Register Transfer Level) model 5.
Isa simulator 1, produces a stage that comprises many group reference datas for carrying out test programReference data file. Wherein, test program is inputted from outside. More specifically the test of, inputting from outsideProgram is can be for to flow by assembly instruction the assembling file forming, and isa simulator 1 is carried out this assembling fileProduce this stage reference data file. This stage reference data file is defeated by one of device 2 as a comparisonMembership is loaded into storage in comparator 2.
Comparator 2, for isa simulator 1 fetch phase reference data file. Interim referenceThe stage of data file refers to one group of reference data in each output stage reference data file, thisThe object that sample does is to save the simulation time expending when comparator 2 does interim inspection. Specifically, relativelyDevice 2 is divided into many group reference datas according to whether comprising specified format to interim reference data file,Wherein, specified format comprises the relatively mark whether sign needs comparator 2 to compare, in concrete enforcementIn process, specified format also comprises value adhering to separately by inhomogeneity register etc.
Input interface 4 is linked into design 6 to be verified (english abbreviation: DUV, English full name: designunderVerification), flow the assembling file that the forms storage list to design 6 to be verified for loading by assembly instructionUnit.
Monitor 3 is linked into design 6 to be verified, for catching the letter to be verified of design 6 emulation to be verifiedNumber export to comparator 2, comparator 2 is linked into monitor 3, and the signal to be verified that monitor 3 is exported is doneFor another input of comparator 2.
Comparator 2, for the interim reference data file reading and signal to be verified are contrasted is alsoNo consistent. One group of reference data of each stage fetch phase reference data file.
RTL model 5 is linked into design 6 to be verified, reads to be verified for Cycle by Cycle from design 6 to be verifiedDesign 6 partial interior signal, with the behavior of carrying out ruling design 6 to be verified whether with RTL model 5Behavior consistent. Concrete, the partial interior signal that reads of each emulation cycle of RTL model 5 comprises to be gotCommand signal, read-write register heap signal, bypass register signal etc.
Concrete, shown in figure 2, RTL model 5 comprises: instruction Dispatching Unit 51, performance element52, write back unit 53, abnormal generation unit 54, programmed counting generation unit 55, bypass model unit 56,Register-memory model unit 57, ruling unit 58.
Instruction Dispatching Unit 51, is processed into and returns for partial interior signal and instruction being read to relevant signalClass instruction code outputs to performance element 52. Register-memory model unit 57, for based on writing back informationSimulate the function that writes back of design 6 to be verified, the pipelining-stage information of writing register is outputed to register bypass mouldType unit 56, and will write the value of register or the value of memory write outputs to performance element 52. By registerRoad model unit 56, the value of writing read register for reading outputs to performance element according to the constraint of pipelining-stage52; Performance element 52, for simulating the execution process instruction of design 6 to be verified, instruction execution result is defeatedGo out to writing back unit 53, abnormal generation unit 54 and programmed counting generation unit 55. Write back unit 53, useIn based on writing the value of register or the value of memory write, what output current period was required writes back information register-memory model unit 57 and ruling unit 58; Abnormal generation unit 54, for carrying out knot according to instructionFruit judges current whether should generation extremely, and abnormal judged result is outputed to ruling unit 58; Program meterNumber generation units 55, for judge the current redirect generation of whether having according to instruction execution result, and sentence redirectDisconnected result outputs to ruling unit 58; Ruling unit 58, for will write back information, abnormal judged result,Redirect judged result and partial interior signal contrast, thus the behavior of ruling design 6 to be verified whether with RTLThe behavior of model 5 is consistent.
Based on same inventive concept, the embodiment of the present invention provides a kind of Microprocessor Function Verification Method, applicationIn the verifying function of microprocessor equipment shown in previous embodiment and Fig. 1, Fig. 2, in conjunction with reference to figure 1,Shown in Fig. 2 and Fig. 3, this Microprocessor Function Verification Method comprises the steps:
S1, carry out test program by isa simulator 1 and produce interim reference data file.
Concrete, before opening emulation, first isa simulator 1 is implemented as the test of assembly instruction streamProgram produces interim reference data file. The input of device 2 is as a comparison loaded into comparator by this fileStorage in 2. Stage refers to after one section of instruction of execution just exports one group of reference data, in every group of data, wrapsContain the relatively mark that whether needs comparator 2 to compare.
In specific implementation process, interim reference data file is loaded in the storage of comparator 2, soRear comparator 2 is divided into the references of many groups according to whether comprising specified format to interim reference data fileData.
S2, starting design 6 to be verified and RTL model 5, to carry out register transfer grade simulated, by monitoringThe signal to be verified that device 3 catches in design 6 emulation to be verified outputs to comparator 2.
Concrete, when register transfer is grade simulated, the test program and instruction collection of inputting design 6 to be verified is imitativeThe test program that true device 1 is carried out is identical, uses emulation tool to carry out design 6 to be verified and RTL model 5Register transfer grade simulated, thereby assembly instruction stream in design 6 to be verified, carry out, monitor 3 is caughtThe signal to be verified obtaining comprises: write data of register file or write memory etc.
S3, comparator 2 read current group of reference data from interim reference data file.
Concrete, return at every turn current group of reference data that S3 reads all with a upper emulation cycle read oneGroup reference data difference. Such as, it is first group of reference data that comparator 2 reads reference data for the first time,The reference data reading in turn is for the second time second group of reference data, and the reference data reading in turn is for the third timeThe 3rd group of reference data, reads successively with this order.
After carrying out S3, then carry out S4:RTL model 5 Cycle by Cycle and read from design 6 to be verifiedPartial interior signal, with the behavior of carrying out ruling design 6 to be verified whether with the behavior one of RTL model 5Cause, if carry out S5, otherwise emulation finishes.
Specifically, RTL model 5 is in all reading section inside from design 6 to be verified of each emulation cycleSignal, and each emulation cycle, the partial interior signal that RTL model 5 reads from design 6 to be verifiedEach signal type is all identical.
RTL model 5 enters the partial interior signal reading and the inner data that self produce of RTL model 5Row contrast, the behavior that RTL model 5 judges design 6 to be verified according to comparing result whether with RTL mouldThe behavior of type 5 is consistent, and the inconsistent mistake of having found design 6 to be verified that means, need to stop at onceEmulation.
In specific implementation process, the partial interior signal reading comprises: instruction fetch data, read-write registerHeap data and read-write bypass register data etc.
Concrete, RTL model 5 comprises: instruction Dispatching Unit 51, and performance element 52, writes back unit 53,Abnormal generation unit 54, programmed counting generation unit 55, bypass model unit 56, register-memory mouldType unit 57, ruling unit 58.
Instruction Dispatching Unit 51 by and instruction in partial interior signal read relevant signal be processed into sort out refer toOrder code outputs to performance element 52; Register-memory model unit 57 is to be verified based on writing back information simulationDesign 6 the function that writes back, the pipelining-stage information of writing register outputed to register bypass model unit 56,And will write the value of register or the value of memory write outputs to performance element 52; Register bypass model unit56 read the value of writing read register outputs to performance element 52 according to the constraint of pipelining-stage; Performance element 52 mouldsIntend the execution process instruction of design 6 to be verified, instruction execution result outputed to and write back unit 53, extremely produceRaw unit 54 and programmed counting generation unit 55; Write back value or the memory write of unit 53 based on writing registerValue, what output current period was required writes back information register-memory model unit 57 and ruling unit58; Abnormal generation unit 54, for judge current whether should generation extremely according to instruction execution result, andAbnormal judged result is outputed to ruling unit 58; Programmed counting generation unit 55 is according to instruction execution resultWhether current have redirect occur, and redirect judged result is outputed to ruling unit 58 if judging; Ruling unit58 by writing back information, the part of abnormal judged result, redirect judged result and the design to be verified 6 of readingInternal signal contrast, thus whether the behavior of ruling design 6 to be verified is consistent with the behavior of RTL model 5.
S5: in the time arriving the interim checkpoint of comparator 2,2 more current groups of reference datas of comparator withWhether the current signal to be verified capturing is consistent, be to carry out S6, otherwise emulation finishes.
In specific implementation process, current group of reference data and the current signal to be verified capturing are inconsistent,Mean the mistake of having found design 6 to be verified, need to stop at once emulation.
Specifically the detailed description of the invention that, whether arrives the interim checkpoint of comparator 2 is: comparator2 judge in current group of reference data whether exist relatively and identify; If there is relatively mark in current group of reference dataKnow and show to arrive interim checkpoint, if there is not relatively mark, not yet arrive interim checkpoint,Whether RTL model 5 is proceeded the behavior of ruling design 6 to be verified consistent with the behavior of RTL model 5.
S6: judge whether emulation finishes at this point, if emulation finishes, otherwise return to S3.
Concrete, emulation finishes to finish and the behavior decision of design 6 to be verified by whether inputting instruction stream. RatioAs, if while there is resting on all the time certain point or carry out all the time the phenomenon of certain instruction in design to be verified 6,Illustrated with the inconsistent behavior of expection and occurred, emulation needs to finish. To design 6 input test journeys to be verifiedOrder finishes, and being judged as emulation need to finish at this point.
By the one or more technical schemes that provide in the invention described above embodiment, at least there is following technologyEffect or advantage:
1, comprise isa simulator owing to having adopted, comparator, monitor, input interface, RTL modelVerifying function of microprocessor equipment, reduced the complexity of reference model, the function based on reference model is testedThe quantities of card is dwindled greatly, on the one hand: comparator is not just comparing operation less than interim test point,Therefore saved the simulation time expending when comparator does consistent inspection, on the other hand: RTL model is each imitativeTrue cycle all does real-time comparison from design reading section internal signal to be verified, and comparator the cycle reads one by oneGetting one group of signal to be verified and reference data and contrast, is all in the time that discovery is inconsistent, just to have feedback, because ofThe combination of this this two aspects has effectively ensured to find fast the mistake in design to be verified, therefore efficient solutionDetermine in prior art to the inefficient technical problem of the functional check of design to be verified, thereby realized efficientFunctional check fast, has finally improved verification efficiency.
2, because making real-time comparison and instruction collection emulator, RTL model provide reference data to do for comparatorThe consistent double shield checking, thus the degree of accuracy to the existing location of mistake of design to be verified ensured.
Although described the preferred embodiments of the present invention, once those skilled in the art obtain cicada baseThis creative concept, can make other change and amendment to these embodiment. So appended right is wantedAsk and be intended to be interpreted as comprising preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification and not depart from this present inventionBright spirit and scope. Like this, if of the present invention these amendment and modification belong to the claims in the present invention andWithin the scope of its equivalent technologies, the present invention be also intended to comprise these change and modification interior.
Claims (7)
1. a verifying function of microprocessor equipment, is characterized in that, comprising: isa simulator, thanCompared with device, monitor, input interface, RTL model;
Described isa simulator, produces interim reference data file for carrying out test program;
Described comparator, for reading described interim reference data file from described isa simulator;
Described input interface, for loading the memory cell of described test program to design to be verified;
Described monitor, exports to described ratio for catching the signal to be verified of described design and simulation to be verifiedCompared with device;
Described comparator, also for by the reference data of described interim reference data file and described to be testedWhether card signal contrasts consistent;
Described RTL model, reads the portion of described design to be verified from described design to be verified for Cycle by CyclePoint internal signal, with the behavior of carrying out design to be verified described in ruling whether with the behavior of described RTL modelUnanimously.
2. verifying function of microprocessor equipment as claimed in claim 1, is characterized in that, described RTLModel comprises: instruction Dispatching Unit, and performance element, writes back unit, abnormal generation unit, programmed counting producesRaw unit, bypass model unit, register-memory model unit, ruling unit;
Described instruction Dispatching Unit, for reading relevant signal place by described partial interior signal and instructionManage into classification instruction code and output to described performance element;
Described register-memory model unit, for simulating writing of described design to be verified based on writing back informationReturn function, the pipelining-stage information of writing register is outputed to described register bypass model unit, and will write and postThe value of storage or the value of memory write output to described performance element;
Described register bypass model unit, for reading, to write the value of read register defeated according to the constraint of pipelining-stageGo out to described performance element;
Described performance element, for simulating the execution process instruction of described design to be verified, carries out knot by instructionDescribed in outputing to, fruit writes back unit, described abnormal generation unit and described programmed counting generation unit;
The described unit that writes back, for based on writing the value of register or the value of memory write, exports current period instituteDescribed in needing, write back information described register-memory model unit and described ruling unit;
Described abnormal generation unit, for judge according to described instruction execution result current whether should produce differentOften, and by abnormal judged result output to described ruling unit;
Described programmed counting generation unit, for judging the current redirect that whether has according to described instruction execution resultOccur, and redirect judged result is outputed to described ruling unit;
Described ruling unit, for will described in write back information, described abnormal judged result, described redirect judgementResult and described partial interior signal contrast, thus whether ruling goes out the behavior of described design to be verified with describedThe behavior of RTL model is consistent.
3. a Microprocessor Function Verification Method, is characterized in that, comprising:
S1: carry out test program by isa simulator and produce interim reference data file;
S2: starting described design to be verified and RTL model, to carry out register transfer grade simulated, by monitoringThe signal to be verified that device catches in described design and simulation to be verified outputs to described comparator;
S3: described comparator reads current group of reference data from described interim reference data file;
S4: described RTL model Cycle by Cycle reading section internal signal from described design to be verified, to enterDescribed in row ruling, whether the behavior of design to be verified consistent with the behavior of described RTL model, if carry outS5, otherwise emulation finishes;
S5: in the time arriving the interim checkpoint of comparator, the more described current group of reference number of described comparatorAccording to whether consistent with the current signal described to be verified capturing, be to carry out S6, otherwise emulation finish;
S6: judge whether emulation finishes at this point, if emulation finishes, otherwise return to S3.
4. Microprocessor Function Verification Method as claimed in claim 3, is characterized in that, at described S4In, described RTL model Cycle by Cycle reading section internal signal from described design to be verified, to cut outWhether the behavior of described design to be verified of determining is consistent with the behavior of described RTL model, comprising:
Described RTL model reads described partial interior letter from described design to be verified in each emulation cycleNumber;
Described RTL model is by described partial interior signal and the inner data that self produce of described RTL modelContrast;
The behavior that RTL model judges described design to be verified according to comparing result whether with described RTL modelBehavior consistent.
5. Microprocessor Function Verification Method as claimed in claim 4, is characterized in that, at described S1In, describedly carry out after test program produces interim reference data file also bag by isa simulatorDraw together:
Described interim reference data file is loaded into described comparator;
Described comparator is divided described interim reference data file according to whether comprising specified formatBecome many group reference datas, wherein, described specified format comprises relatively mark.
6. Microprocessor Function Verification Method as claimed in claim 5, is characterized in that, at described S5In, whether the more described current group of reference data of described comparator and the current signal described to be verified capturingUnanimously, comprising:
Described comparator judges in described current group of reference data, whether there is described relatively mark;
If there is described relatively mark in described current group of reference data, show to arrive described interim inspectionPoint.
7. Microprocessor Function Verification Method as claimed in claim 6, is characterized in that, at described S6In, describedly judge that whether emulation finishes at this point, is specially:
Input described test program to described design to be verified and finish, being judged as emulation need to finish at this point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510959069.1A CN105589993B (en) | 2015-12-18 | 2015-12-18 | Microprocessor function verification apparatus and microprocessor function verification method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510959069.1A CN105589993B (en) | 2015-12-18 | 2015-12-18 | Microprocessor function verification apparatus and microprocessor function verification method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105589993A true CN105589993A (en) | 2016-05-18 |
| CN105589993B CN105589993B (en) | 2019-01-15 |
Family
ID=55929571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510959069.1A Active CN105589993B (en) | 2015-12-18 | 2015-12-18 | Microprocessor function verification apparatus and microprocessor function verification method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105589993B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106295048A (en) * | 2016-08-19 | 2017-01-04 | 西安电子科技大学 | A kind of digit chip function verification method and system |
| CN107665169A (en) * | 2016-07-29 | 2018-02-06 | 龙芯中科技术有限公司 | The method of testing and device of processor program |
| CN107704351A (en) * | 2017-10-18 | 2018-02-16 | 盛科网络（苏州）有限公司 | The verification method and device of a kind of chip |
| CN107895099A (en) * | 2017-12-30 | 2018-04-10 | 盛科网络（苏州）有限公司 | A kind of localization method and device of chip design mistake |
| CN108664368A (en) * | 2017-03-30 | 2018-10-16 | 华为技术有限公司 | Processor performance index evaluating method and equipment |
| CN109032879A (en) * | 2017-06-09 | 2018-12-18 | 展讯通信（上海）有限公司 | Multi-core processor memory access Data Detection verifies system and method |
| CN109101355A (en) * | 2018-06-26 | 2018-12-28 | 天津飞腾信息技术有限公司 | A kind of processor debugging method for extracting wrong presence feature test and excitation |
| CN109189479A (en) * | 2018-10-12 | 2019-01-11 | 西安微电子技术研究所 | A kind of parallel automatic verification method for processor instruction set |
| CN109753308A (en) * | 2017-11-06 | 2019-05-14 | 展讯通信（上海）有限公司 | Verify system and instruction path monitoring method in instruction path |
| CN109829192A (en) * | 2018-12-26 | 2019-05-31 | 苏州中晟宏芯信息科技有限公司 | A kind of the reference model construction method and device of processor computing unit |
| CN110688269A (en) * | 2019-09-12 | 2020-01-14 | 武汉极目智能技术有限公司 | RTL code automatic verification device and method adopting AXI bus interface |
| CN110727584A (en) * | 2019-09-10 | 2020-01-24 | 无锡江南计算技术研究所 | Real-time comparison method of RTL (real time language) and reference model for pre-silicon verification of processor |
| CN111797588A (en) * | 2020-07-03 | 2020-10-20 | 国微集团(深圳)有限公司 | Formal verification comparison point matching method, system, processor and memory |
| CN112540288A (en) * | 2020-11-30 | 2021-03-23 | 海光信息技术股份有限公司 | Method, system, device and storage medium for chip-after-silicon verification |
| CN115510782A (en) * | 2022-08-31 | 2022-12-23 | 芯华章科技股份有限公司 | Method for locating verification error, electronic device and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0652257A (en) * | 1992-08-03 | 1994-02-25 | Hokuriku Nippon Denki Software Kk | Logical simulation system |
| CN1684047A (en) * | 2004-12-24 | 2005-10-19 | 清华大学 | CPU restraint forming and verifying method based on boundary condition and self detection random test |
| CN101286182A (en) * | 2008-05-16 | 2008-10-15 | 浙江大学 | Dynamic simulation platform method for embedded processor function verification |
| JP2009175930A (en) * | 2008-01-23 | 2009-08-06 | Mitsubishi Electric Corp | Assertion description language generation method and device, and assertion base simulation program using it |
| CN103678114A (en) * | 2012-09-07 | 2014-03-26 | 三星电子株式会社 | Apparatus and method for generating assertion, and apparatus and method for verifying processor |
-
2015
- 2015-12-18 CN CN201510959069.1A patent/CN105589993B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0652257A (en) * | 1992-08-03 | 1994-02-25 | Hokuriku Nippon Denki Software Kk | Logical simulation system |
| CN1684047A (en) * | 2004-12-24 | 2005-10-19 | 清华大学 | CPU restraint forming and verifying method based on boundary condition and self detection random test |
| JP2009175930A (en) * | 2008-01-23 | 2009-08-06 | Mitsubishi Electric Corp | Assertion description language generation method and device, and assertion base simulation program using it |
| CN101286182A (en) * | 2008-05-16 | 2008-10-15 | 浙江大学 | Dynamic simulation platform method for embedded processor function verification |
| CN103678114A (en) * | 2012-09-07 | 2014-03-26 | 三星电子株式会社 | Apparatus and method for generating assertion, and apparatus and method for verifying processor |
Non-Patent Citations (2)
| Title |
|---|
| 沈胜宇 等: "基于指令分解的微处理器验证与RTL级错误定位", 《计算机工程与科学》 * |
| 罗汉青 等: "DSP随机测试程序自动生成技术", 《微电子学与计算机》 * |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107665169B (en) * | 2016-07-29 | 2020-07-28 | 龙芯中科技术有限公司 | Method and device for testing processor program |
| CN107665169A (en) * | 2016-07-29 | 2018-02-06 | 龙芯中科技术有限公司 | The method of testing and device of processor program |
| CN106295048A (en) * | 2016-08-19 | 2017-01-04 | 西安电子科技大学 | A kind of digit chip function verification method and system |
| CN108664368A (en) * | 2017-03-30 | 2018-10-16 | 华为技术有限公司 | Processor performance index evaluating method and equipment |
| CN109032879A (en) * | 2017-06-09 | 2018-12-18 | 展讯通信（上海）有限公司 | Multi-core processor memory access Data Detection verifies system and method |
| CN109032879B (en) * | 2017-06-09 | 2021-08-20 | 展讯通信（上海）有限公司 | Multi-core processor memory access data detection and verification system and method |
| CN107704351A (en) * | 2017-10-18 | 2018-02-16 | 盛科网络（苏州）有限公司 | The verification method and device of a kind of chip |
| CN109753308A (en) * | 2017-11-06 | 2019-05-14 | 展讯通信（上海）有限公司 | Verify system and instruction path monitoring method in instruction path |
| CN107895099A (en) * | 2017-12-30 | 2018-04-10 | 盛科网络（苏州）有限公司 | A kind of localization method and device of chip design mistake |
| CN109101355A (en) * | 2018-06-26 | 2018-12-28 | 天津飞腾信息技术有限公司 | A kind of processor debugging method for extracting wrong presence feature test and excitation |
| CN109189479B (en) * | 2018-10-12 | 2023-02-24 | 西安微电子技术研究所 | Parallel automatic verification method for processor instruction set |
| CN109189479A (en) * | 2018-10-12 | 2019-01-11 | 西安微电子技术研究所 | A kind of parallel automatic verification method for processor instruction set |
| CN109829192A (en) * | 2018-12-26 | 2019-05-31 | 苏州中晟宏芯信息科技有限公司 | A kind of the reference model construction method and device of processor computing unit |
| CN109829192B (en) * | 2018-12-26 | 2023-10-17 | 合芯科技(苏州)有限公司 | Reference model construction method and device for processor computing unit |
| CN110727584A (en) * | 2019-09-10 | 2020-01-24 | 无锡江南计算技术研究所 | Real-time comparison method of RTL (real time language) and reference model for pre-silicon verification of processor |
| CN110727584B (en) * | 2019-09-10 | 2021-04-30 | 无锡江南计算技术研究所 | Real-time comparison method of RTL (real time language) and reference model for pre-silicon verification of processor |
| CN110688269A (en) * | 2019-09-12 | 2020-01-14 | 武汉极目智能技术有限公司 | RTL code automatic verification device and method adopting AXI bus interface |
| CN110688269B (en) * | 2019-09-12 | 2023-03-14 | 武汉极目智能技术有限公司 | RTL code automatic verification device and method adopting AXI bus interface |
| CN111797588A (en) * | 2020-07-03 | 2020-10-20 | 国微集团(深圳)有限公司 | Formal verification comparison point matching method, system, processor and memory |
| CN111797588B (en) * | 2020-07-03 | 2022-11-11 | 深圳国微芯科技有限公司 | Formal verification comparison point matching method, system, processor and memory |
| CN112540288B (en) * | 2020-11-30 | 2023-02-21 | 海光信息技术股份有限公司 | Method, system, device and storage medium for chip after silicon verification |
| CN112540288A (en) * | 2020-11-30 | 2021-03-23 | 海光信息技术股份有限公司 | Method, system, device and storage medium for chip-after-silicon verification |
| CN115510782A (en) * | 2022-08-31 | 2022-12-23 | 芯华章科技股份有限公司 | Method for locating verification error, electronic device and storage medium |
| CN115510782B (en) * | 2022-08-31 | 2024-04-26 | 芯华章科技股份有限公司 | Method for locating verification errors, electronic device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105589993B (en) | 2019-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105589993A (en) | Microprocessor function verification apparatus and microprocessor function verification method | |
| US7865346B2 (en) | Instruction encoding in a hardware simulation accelerator | |
| US8560988B2 (en) | Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design | |
| US20120185669A1 (en) | Program inspection method and non-transitory, computer readable storage medium storing inspection program | |
| CN113779912B (en) | Chip verification system, method and device, electronic equipment and storage medium | |
| CN117094269B (en) | Verification method, verification device, electronic equipment and readable storage medium | |
| CN112597718B (en) | Verification method, verification device and storage medium for integrated circuit design | |
| CN107850641A (en) | The whole-system verification of on-chip system (SoC) | |
| CN111400992A (en) | Test method and system for automatically verifying boxing layout and wiring | |
| US8306802B2 (en) | Method for modeling an HDL design using symbolic simulation | |
| CN105760638A (en) | SOC-chip simulation accelerating method | |
| CN117113908B (en) | Verification method, verification device, electronic equipment and readable storage medium | |
| CN110347595A (en) | A kind of FPGA internal resource is screened and localization method and system | |
| US6725187B1 (en) | Latch inference using dataflow analysis | |
| CN117377961A (en) | Method, device and equipment for simulation | |
| US8825464B2 (en) | Method and apparatus for parallelization of sequential power simulation | |
| WO2019142266A1 (en) | Test case generation device, test case generation method, and test case generation program | |
| Petersén et al. | Fault injection and fault handling: an MPSoC demonstrator using IEEE P1687 | |
| US6813599B1 (en) | Efficient memory structure simulation for sequential circuit design verification | |
| US8560987B2 (en) | Test functionality integrity verification for integrated circuit design | |
| US6813751B2 (en) | Creating standard VHDL test environments | |
| US9946624B1 (en) | Systems and methods to capture data signals from a dynamic circuit | |
| US7051301B2 (en) | System and method for building a test case including a summary of instructions | |
| CN117077603B (en) | Verification method, chip, system, electronic device and readable storage medium | |
| Hanafy et al. | New methodology for complete properties extraction from simulation traces guided with static analysis |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |