CN105512069B - Deserializer device and its asynchronous conversion method - Google Patents
Deserializer device and its asynchronous conversion method Download PDFInfo
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- CN105512069B CN105512069B CN201510887965.1A CN201510887965A CN105512069B CN 105512069 B CN105512069 B CN 105512069B CN 201510887965 A CN201510887965 A CN 201510887965A CN 105512069 B CN105512069 B CN 105512069B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The invention discloses a kind of deserializer device, including the first PLL device, the second PLL device and flip-flop.First PLL device receives the first frequency signal of period 1, and generates the second frequency signal of second round and the third frequency signal of period 3.First PLL device generates flag signals according to first, second, and third frequency signal, and flag signals are sent to the second PLL device.Second PLL device, which synchronizes, receives first frequency signal, and generate the 4th frequency signal of period 3.Second PLL device foundation first and the 4th frequency signal sample the flag signals with phase difference to obtain reset signal, make reset signal unrelated with phase difference.Flip-flop receives reset signal and the 4th frequency signal, and corresponding generation and second frequency signal synchronization and the 5th identical frequency signal.
Description
Technical field
The invention relates to deserializer (serializer (Serializer)/deserializer (Deserializer)) dresses
It puts, in particular to the asynchronous conversion method applied between the middle different PLL devices of deserializer device.
Background technology
The invention discloses a kind of deserializer device, including the first PLL device, the second PLL device and
Flip-flop.First PLL device receives the first frequency signal of period 1, and generates the second frequency letter of second round
Number and the period 3 third frequency signal.First PLL device generates flag according to first, second, and third frequency signal
Signal is marked, and flag signals are sent to the second PLL device.Second PLL device, which synchronizes, receives first frequency letter
Number, and generate the 4th frequency signal of period 3.Second PLL device foundation first and the 4th frequency signal are to having
The flag signals of phase difference sample to obtain reset signal, make reset signal unrelated with phase difference.Flip-flop receives resetting letter
Number and the 4th frequency signal, and corresponding generate and the synchronization of second frequency signal and the 5th identical frequency signal.
Invention content
The exemplary embodiment of the present invention provides a kind of deserializer device.The deserializer device includes one the
One PLL device, one second PLL device and a flip-flop.First PLL device is receiving one
The one first frequency signal in one period, and the second frequency signal of the corresponding second round for generating less than the period 1 and
The third frequency signal of one period 3, the wherein second round are twice of the period 3.Second phase-locked loop fills
It puts and receives the first frequency signal, and corresponding one the 4th frequency signal for generating the period 3 to synchronous.The flip-flop connects
Second PLL device is connected to, to receive the reset signal and one the 4th frequency of second PLL device output
Signal, and corresponding generation and second frequency signal synchronization and one the 5th identical frequency signal, wherein first phase-locked loop
Device exports a flag signals according to the first frequency signal, the second frequency signal and the third frequency signal；The wherein flag
Mark signal has had a phase difference when being transferred to second PLL device；And wherein second PLL device according to
A sampled signal is generated, and using the sampled signal to having the phase difference according to the first frequency signal and the 4th frequency signal
The different flag signals sample to obtain the reset signal, make the reset signal unrelated with the phase difference.
The exemplary embodiment of the present invention provides a kind of asynchronous conversion method for being used for a deserializer device.This is different
It walks conversion method and includes the synchronous first frequency signal for sending a period 1 to one first lock of the deserializer device
Phase loop apparatus and one second PLL device；The one of the period 1 is generated less than through first PLL device
One second frequency signal of two cycles and the third frequency signal of a period 3, the wherein second round is the period 3
Twice；A flag signals are exported through first PLL device, the wherein flag signals are to be produced from the first lock phase
The first frequency signal, the second frequency signal and third frequency signal of loop apparatus, and the flag signals are transferred to this
There is a phase difference during the second PLL device；The one of the period 3 is generated through second PLL device
Four frequency signals；Through second PLL device generate a sampled signal, wherein the sampled signal be produced from this second
First frequency signal and the 4th frequency signal of PLL device；Using the sampled signal to having the phase difference
The flag signals sample to obtain a reset signal, make the reset signal unrelated with the phase difference；And it serially unstrings through this
One flip-flop of device device receives the reset signal and the 4th frequency signal, synchronous with the second frequency signal with corresponding generation
And one the 5th identical frequency signal.
Description of the drawings
Fig. 1 is the block diagram of first embodiment realization deserializer device 10 according to the present invention；
Fig. 2 is the frequency diagram that first embodiment illustrates each frequency signal in deserializer device 10 according to the present invention；
Fig. 3 is a circuit diagram of second embodiment realization flag circuit 30 according to the present invention；
Fig. 4 A to Fig. 4 D are the frequency diagrams that second embodiment illustrates each frequency signal in flag circuit 30 according to the present invention；
Fig. 5 A to Fig. 5 D are the frequencies that 3rd embodiment according to the present invention illustrates each frequency signal in flag circuit 30
Figure；
Fig. 6 is asynchronous conversion method of the fourth embodiment realization according to the present invention suitable for deserializer device 10
A flow chart.
Specific embodiment
The appended embodiment illustrated of this exposure or example will as described below.The scope of this exposure is not so limited.It practises
Know those skilled in the art should be able to know do not depart from this exposure spirit and framework under the premise of, when can make it is a little change, replace and displacement.
In the embodiment of this exposure, element numbers may be used repeatedly, the connection with several embodiments of this exposure may be shared identical
Element numbers, but the features component used in an embodiment is not necessarily that another embodiment uses.
Fig. 1 is the block diagram of a first embodiment one deserializer device 10 of realization according to the present invention.In the present invention
In first embodiment, deserializer device 10 include one first PLL device 11, one second PLL device 12, with
An and logic circuit 13.First PLL device 11 is each in different frequency signals to deserializer device 10 to supply
Kind low-frequency channel, for example, clock data restores (Clock Data Recovery, CDR) circuit.Second PLL device 12
Then supplying different clocks signal as high-frequency signal needed for the RX path in deserializer device 10.
In the first embodiment of the invention, the first PLL device 11 and 12 synchronous reception phase of the second PLL device
With a period 1 a reference frequency signal REF100IN, wherein the time span of aforementioned period 1 for 10 nanoseconds (also
I.e. the frequency of first frequency signal REF100IN is 100MHz).
In the first embodiment of the invention, the first PLL device 11 according to reference frequency signal REF100IN generate/
The frequency signal CK250 of a second round and the frequency signal CK500 of a period 3 are exported, wherein aforementioned second and
The time span in three periods is respectively that (that is, the frequency of frequency signal CK250 and frequency signal CK500 are distinguished for 4 nanoseconds and 2 nanoseconds
For 250MHz and 500MHz).Logic circuit 13 distinguishes receives frequency signal CK250 and frequency signal CK500, and corresponds to respectively defeated
Go out the frequency signal LP_CTSCK250 of second round and the frequency signal LP_CTSCK500 of period 3 to an Ethernet object
Manage layer transceiver 14 (ethernet physical layer transceiver 14, EPHY TX 14).In the present invention first
In embodiment, frequency signal LP_CTSCK250 and LP_CTSCK500 that ethernet PHY transceiver 14 is received are synchronized with
Reference frequency signal REF100IN.
In the first embodiment of the invention, the second PLL device 12 according to reference frequency signal REF100IN generate/
Export second round a frequency signal TPLCK250 and the frequency signal TPLCK500 of period 3 to deserializer fill
Put each drawing lines (lane) in 10.In the first embodiment of the invention, frequency signal TPLCK500, which is output to, serially unstrings
Frequency Synchronization during each drawing lines (lane) in device device 10 is in reference frequency signal REF100IN.
In the first embodiment of the invention, it's not limited to that for the time span in aforementioned first, second or third period, this
Field has usually intellectual it will be appreciated that the time span in aforementioned first, second or third period can be filled according to deserializer
It puts 10 the first PLL device 11 and the actual frequency demand of the second PLL device 12 and changes.
Fig. 2 is the frequency diagram that first embodiment illustrates each frequency signal in deserializer device 10 according to the present invention.
As shown in Fig. 2, in the first embodiment of the invention, the frequency signal LP_CTSCK500 and frequency signal of period 3
TPLCK500 has all been synchronized with reference frequency signal REF100IN.At this point, deserializer device 10 penetrates a flag circuit again
Ensure the frequency signal LP_CTSCK250 and the second PLL device 12 of 11 corresponding second round of the first PLL device
The frequency signal TPLCK250 of corresponding second round can be synchronized with reference frequency signal REF100IN each other.Finally, when
The frequency signal LP_CTSCK250 of 11 corresponding second round of first PLL device can be synchronized with reference frequency signal
REF100IN when, the rising edge that the first PLL device 11 is just capable of frequency of use signal LP_CTSCK250 correctly transmits
Data transfer signal is to ethernet PHY transceiver 14；And when 12 corresponding frequency signal of the second PLL device
TPLCK250 can be synchronized with reference frequency signal REF100IN when, the second PLL device 12 just being capable of frequency of use signal
The failing edge of TPLCK250 is properly received the data transfer signal from ethernet PHY transceiver 14.Therefore, in this hair
In bright first embodiment, aforementioned flag circuit how is designed to ensure frequency signal LP_CTSCK250 and frequency signal
TPLCK250 can be synchronized with reference frequency signal REF100IN each other becomes the subject under discussion for being badly in need of overcoming.
Fig. 3 is a circuit diagram of a second embodiment one flag circuit 30 of realization according to the present invention.In the present invention second
In embodiment, flag circuit 30 realizes that first embodiment of the invention states flag circuit in advance, to ensure frequency signal LP_
CTSCK250 and frequency signal TPLCK250 can be synchronized with reference frequency signal REF100IN each other.
In order to facilitate narration, in flag circuit 30 shown in second embodiment of the invention, the ginseng described in first embodiment
Examining frequency signal REF100IN is represented with the first frequency signal M100 (or T100) of period 1, first embodiment institute
The frequency signal LP_CTSCK250 stated is represented with the second frequency signal M250 of second round, described in first embodiment
Frequency signal LP_CTSCK500 is represented with the third frequency signal M500 of period 3, the frequency described in first embodiment
Signal TPLCTSCK500 is represented with one the 4th frequency signal T500 of period 3, and the frequency letter described in first embodiment
Number TPLCTSCK250 is represented with one the 5th frequency signal T250 of second round.
In second embodiment of the invention, flag circuit 30 include the first sub- flag circuit 31, the second sub- flag circuit 32,
And a flip-flop 33, wherein the first sub- flag circuit 31 is set in the first PLL device 11, and the second Ziqi mark
Circuit 32 and flip-flop 33 are then set in the second PLL device 12.Flip-flop 33 is a D-type flip-flop, but the present invention
It's not limited to that, other kenel flip-flops also can be used, for example, RS flip-flops etc..
In second embodiment of the invention, the first sub- flag circuit 31 of the first PLL device 11 receives the first lock phase
First frequency signal M100, the second frequency signal M250 of loop apparatus 11 and third frequency signal M500, and corresponding generation one
Flag signals flagM.Then, since the first sub- 31 and second sub- flag circuit 32 of flag circuit is located at the first phase-locked loop respectively
In 11 and second PLL device 12 of device, flag signals caused by the first sub- flag circuit 31 of flag circuit 30
FlagM need to first pass through several drawing lines (lane), and flag circuit 30 is input to for example, can just become after 4 drawing lines (lane)
The flag signals flagM ' of second sub- flag circuit 32.Therefore, in second embodiment of the invention, flag signals flagM is transmitted
It has increased/has had a phase difference during to the second PLL device 12 newly and become above-mentioned flag signals flagM '.
In second embodiment of the invention, the second sub- flag circuit 32 of flag circuit 30 receives above-mentioned flag signals
FlagM ', first frequency signal T100 and the 4th frequency signal T500, and the corresponding reset signal reset that generates is to flip-flop
33, wherein the second sub- flag circuit 32 of the second PLL device 12 is according to first frequency signal T100 and the 4th frequency signal
T500 generates a sampled signal sampleT, and using sampled signal sampleT to having the above-mentioned flag signals of the phase difference
FlagM ' samplings obtain reset signal reset, make reset signal reset unrelated with the phase difference.
In second embodiment of the invention, flip-flop 33 is connected to the second sub- flag circuit of the second PLL device 12
32.Flip-flop 33 is defeated to receive the reset signal reset of the second sub- output of flag circuit 32 and the second PLL device 12
The 4th frequency signal T500 gone out.Flip-flop 33 generates and the second frequency according to reset signal reset and the 4th frequency signal T500
Rate signal M250 synchronizations and one the 5th identical frequency signal T250.Finally, deserializer device 10 reuses the 5th frequency
The failing edge of signal T250 is properly received the data transfer signal from ethernet PHY transceiver 14, to reach the first lock
11 and second PLL device of phase loop apparatus, 12 asynchronous conversion.
Fig. 4 A to Fig. 4 D are the frequency diagrams that second embodiment illustrates each frequency signal in flag circuit 30 according to the present invention.
Fig. 4 A are the frequency diagrams that second embodiment illustrates each frequency signal in the first sub- flag circuit 31 according to the present invention.In Fig. 4 A
In, the first sub- flag circuit 31 generates a sampled signal through first frequency signal M100 and third frequency signal M500
SampleM, wherein sampled signal sampleM are to perform one to an active signal activeM by by third frequency signal M500
Logical operation " ＆ " is acquired, and the logical operation pass of wherein active signal activeM is to represent as follows：
ActiveM=！M100 rst M500/3.
Then, the first sub- flag circuit 31 reuses the failing edge triggering second frequency signal of sampled signal sampleM
M250 obtains flag signals flagM, and the logical operation pass of wherein flag signals flagM is to represent as follows：
FlagM=M250A@(negedge sampleM).
Fig. 4 B are the frequency diagrams that second embodiment illustrates each frequency signal in the second sub- flag circuit 32 according to the present invention.
In figure 4b, the second sub- flag circuit 32 is according to the above-mentioned flag signals flagM ' of reception, the frequencies of first frequency signal T100 and the 4th
Rate signal T500, and the corresponding reset signal reset that generates is to flip-flop 33, wherein sampled signal sampleT are by by the
Four frequency signal T500 perform a logical operation to an active signal activeT " ＆ " acquires, wherein active signal activeT's
Logical operation relationship represents as follows：
ActiveT=T100 rst！T500/3.
Then, the second sub- flag circuit 32 using sampled signal sampleT to have the above-mentioned flag of the phase difference believe
Number flagM ' sampling obtains reset signal reset, makes reset signal reset unrelated with the phase difference.Reset signal reset's
Logical operation relationship represents as follows：
Reset=！(sampleT&flagM’).
Fig. 4 C be according to the present invention second embodiment illustrate flip-flop 33 input/output signal frequency diagram.In Fig. 4 C
In, flip-flop 33 generates with second frequency signal M250 synchronous and phase according to reset signal reset and the 4th frequency signal T500
The 5th same frequency signal T250.
Fig. 4 D are to illustrate the phase difference in flag signals flagM ' shown in second embodiment of the invention with frequency diagram
One time sequence allowance (timing margin).Due to flag signals flagM caused by the first sub- flag circuit 31 need to first pass through it is several
The flag signals for being input to the second sub- flag circuit 32 can just be become after a drawing lines (lane) (for example, 4 drawing lines (lane))
FlagM ' becomes the phase difference in flag signals flagM ' by the phase delay caused by drawing lines (lane).In addition, string
Also there may be flag signals flagM's ' for generated shake (jitter) or deflection (skew) in row deserializer device 10
In the phase difference.In fig. 4d, two flag signals flagM ' indicate the phase difference in flag signals flagM ' and correspond to
A time sequence allowance (timing margin), wherein two flag signals flagM ' represent that a maximum of the phase difference is prolonged respectively
One maximum leading phase of slow phase and the phase difference.In second embodiment of the invention, the time of the maximum delay phase
The half that length is period 1 T1 (10 nanosecond) subtracts the half of period 3 T3 (2 nanosecond), and the leading phase of the maximum
Time span is then the half of period 1 T1 (10 nanosecond).Therefore, in second embodiment of the invention, the time of time sequence allowance
Length subtracts the half of period 3 T3 (2 nanosecond), that is, 10-0.5*2=9 nanoseconds for period 1 T1 (10 nanosecond).
In other words, in second embodiment of the invention, as long as the phase difference is above-mentioned in flag signals flagM '
The range of time sequence allowance (9 nanosecond) it is interior, flip-flop 33 can be correct according to reset signal reset and the 4th frequency signal T500
Generate the fiveth frequency signal T250 synchronous and identical with second frequency signal M250.That is, flag circuit 30 can tolerate flag
Signal flagM ' has above-mentioned time sequence allowance, and (the first frequency signal M100 corresponding period 1 subtracts third frequency signal M500
The half of corresponding period 3) in the range of the phase difference so that flip-flop 33 can be according to reset signal reset and the 4th
Frequency signal T500 correctly generates the fiveth frequency signal T250 synchronous and identical with second frequency signal M250.
Fig. 5 A to Fig. 5 D are the frequencies that a 3rd embodiment according to the present invention illustrates each frequency signal in flag circuit 30
Rate figure.Third embodiment of the invention uses same deserializer device 10 and its flag circuit with second embodiment of the invention
30, unique different being in is different from the second round described in third embodiment of the invention and the time span of period 3
Second embodiment of the invention.
Therefore, in third embodiment of the invention, the first PLL device 11 is according to reference frequency signal REF100IN
The frequency signal CK150 of one second round of the generation/output and frequency signal CK300 of a period 3, and the second lock phase
Loop apparatus 12 generates/exports the frequency signal TPLCK150 and third of second round according to reference frequency signal REF100IN
Each drawing lines (lane) in the one frequency signal TPLCK300 to deserializer device 10 in period, wherein aforementioned second and
The time span in three periods is respectively 6.66 nanoseconds and 3.33 nanoseconds (that is, the frequency of frequency signal CK150 and frequency signal CK300
Rate is respectively 150MHz and 300MHz).
Fig. 5 A are the frequency diagrams that 3rd embodiment illustrates each frequency signal in the first sub- flag circuit 31 according to the present invention.
In fig. 5, the first sub- flag circuit 31 generates a sampled signal through first frequency signal M100 and third frequency signal M300
SampleM, wherein sampled signal sampleM are to perform one to an active signal activeM by by third frequency signal M300
Logical operation " ＆ " is acquired, and the logical operation pass of wherein active signal activeM is to represent as follows：
ActiveM=！M100 rst M300/2.
Then, the first sub- flag circuit 31 reuses the failing edge triggering second frequency signal of sampled signal sampleM
M150 obtains flag signals flagM, and the logical operation relationship of wherein flag signals flagM represents as follows：
FlagM=M150A@(negedge sampleM).
Fig. 5 B are the frequency diagrams that 3rd embodiment illustrates each frequency signal in the second sub- flag circuit 32 according to the present invention.
In figure 5B, the second sub- flag circuit 32 is according to the above-mentioned flag signals flagM ' of reception, the frequencies of first frequency signal T100 and the 4th
Rate signal T300, and the corresponding reset signal reset that generates is to flip-flop 33, wherein sampled signal sampleT are by by the
Four frequency signal T300 perform a logical operation to an active signal activeT " ＆ " acquires, wherein active signal activeT's
Logical operation relationship represents as follows：
ActiveT=T100 rst！T300/2.
Then, the second sub- flag circuit 32 using sampled signal sampleT to have the above-mentioned flag of the phase difference believe
Number flagM ' sampling obtains reset signal reset, makes reset signal reset unrelated with the phase difference.Reset signal reset's
Logical operation relationship represents as follows：
Reset=！(sampleT&(！flagM’)).
Fig. 5 C be according to the present invention 3rd embodiment illustrate flip-flop 33 input/output signal frequency diagram.In Fig. 5 C
In, flip-flop 33 generates with second frequency signal M150 synchronous and phase according to reset signal reset and the 4th frequency signal T300
The 5th same frequency signal T150.
Fig. 5 D are to illustrate the phase difference in flag signals flagM ' shown in third embodiment of the invention with frequency diagram
One time sequence allowance (timing margin).In figure 5d, two flag signals flagM ' are indicated in flag signals flagM ' and are somebody's turn to do
The corresponding time sequence allowance of phase difference (timing margin), wherein two flag signals flagM ' represent the phase difference respectively
A different maximum delay phase and the one of the phase difference maximum leading phase.In third embodiment of the invention, time sequence allowance
Time span subtract the half of period 3 T3 (3.33 nanosecond), that is, 10-0.5*3.33 for period 1 T1 (10 nanosecond)
=8.33 nanoseconds.In other words, in third embodiment of the invention, as long as the phase difference is upper in flag signals flagM '
The interior of the range of time sequence allowance (8.33 nanosecond) is stated, flip-flop 33 can be according to reset signal reset and the 4th frequency signal
T300 correctly generates the fiveth frequency signal T150 synchronous and identical with second frequency signal M150.
In third embodiment of the invention, as long as the phase difference is in above-mentioned time sequence allowance in flag signals flagM '
The range of (8.33 nanosecond) it is interior, flip-flop 33 can correctly be generated according to reset signal reset and the 4th frequency signal T300
The fiveth frequency signal T150 synchronous and identical with second frequency signal M150.That is, flag circuit 30 can tolerate flag signals
FlagM ' has above-mentioned time sequence allowance, and (the first frequency signal M100 corresponding period 1 subtracts third frequency signal M300 correspondences
Period 3 half) in the range of the phase difference so that flip-flop 33 can be according to reset signal reset and the 4th frequency
Signal T300 correctly generates the fiveth frequency signal T150 synchronous and identical with second frequency signal M150.
Fig. 6 is an asynchronous conversion side of the fourth embodiment realization according to the present invention suitable for deserializer device 10
One flow chart of method.In step s 601, the synchronous reference frequency signal REF100IN (that is, first for sending a period 1
Frequency signal M100, T100) to the first PLL device 11 and the second PLL device 12 of deserializer device 10.
In step S602, the second frequency of the second round of the period 1 is generated less than through the first PLL device 11
The signal M250 and third frequency signal M500 of a period 3, the wherein second round are twice of the period 3.
In step S603, through the first PLL device 11 export a flag signals, wherein the flag signals be produced from this first
Reference frequency signal REF100IN, the second frequency signal M250 of PLL device and third frequency signal M500, and the flag
Mark signal has had a phase difference when being transferred to the second PLL device 12.In step s 604, it is returned through the second lock phase
Road device 12 generates one the 4th frequency signal T500 of the period 3.In step s 605, through the second PLL device
12 generate a sampled signal, and the wherein sampled signal is the reference frequency signal for being produced from the second PLL device 12
REF100IN and the 4th frequency signal T500.In step S606, using the sampled signal to having the flag of the phase difference
Mark sample of signal obtains a reset signal, makes the reset signal unrelated with the phase difference.In step S607, through serial solution
One flip-flop of string device device 10 receives the reset signal and the 4th frequency signal T500, is generated and second frequency signal with corresponding
M250 synchronizations and one the 5th identical frequency signal T250.
Though the present invention is disclosed above with preferred embodiment so that one skilled in the art can be more clearly understood that
Present disclosure.However, one skilled in the art will be appreciated that they can easily with the present invention as basis, if
It meter or modification process and carries out identical purpose using deserializer device and its asynchronous conversion method and/or reaches here
The same advantage of the embodiment of introduction.Therefore protection scope of the present invention when regard appended claims institute's defender as
It is accurate.
Claims (10)
1. a kind of deserializer device that asynchronous conversion can be achieved, including：
First PLL device, to receive the first frequency signal of period 1, and correspondence generates less than the period 1
The second frequency signal of second round and the third frequency signal of period 3, the wherein second round is the period 3
Twice, and wherein first PLL device is believed according to the first frequency signal, the second frequency signal and the third frequency
Number output flag signals；
Second PLL device receives the first frequency signal to synchronous, and corresponding the 4th frequency for generating the period 3
Rate signal has had phase difference when wherein the flag signals are transferred to second PLL device,
Wherein second PLL device generates sampled signal according to the first frequency signal and the 4th frequency signal, and makes
The flag signals with the phase difference are sampled to obtain reset signal with the sampled signal, make the reset signal and the phase
Difference is unrelated；And
Flip-flop is connected to second PLL device, to receive the resetting letter of second PLL device output
Number and the 4th frequency signal, and corresponding generate and second frequency signal synchronization and one the 5th identical frequency signal.
2. deserializer device as described in claim 1, the wherein time span of the time sequence allowance of the phase difference is are somebody's turn to do
Period 1 subtracts the difference obtained by the period 3 of half.
3. deserializer device as claimed in claim 2, wherein when the flip-flop can generate and the second frequency signal
During synchronous and identical five frequency signal, the time span of the maximum delay phase of the phase difference is the period 1
Half subtracts the difference obtained by the period 3 of half, and the time span of the leading phase of maximum of the phase difference is then
It is the half of the period 1.
4. deserializer device as described in claim 1, further includes：
Flag circuit, to make the second frequency signal and the 5th frequency signal that can be synchronized with first frequency letter each other
Number.
5. deserializer device as described in claim 1 further includes the 5th frequency signal energy exported when the flip-flop
When being synchronized with the first frequency signal, second PLL device using the 5th frequency signal failing edge receive come from
The too data transfer signal of networked physics layer transceiver.
6. a kind of asynchronous conversion method for deserializer device, which includes：
The synchronous first frequency signal for sending the period 1 is to the first PLL device of the deserializer device and second
PLL device；
The second frequency signal of the second round of the period 1 and third week are generated less than through first PLL device
The third frequency signal of phase, the wherein second round are twice of the period 3；
Flag signals are exported through first PLL device, the wherein flag signals are to be produced from first phase-locked loop dress
The first frequency signal, the second frequency signal and the third frequency signal put, and the flag signals are transferred to second lock
There is phase difference during phase loop apparatus；
The 4th frequency signal of the period 3 is generated through second PLL device；
Sampled signal is generated through second PLL device, the wherein sampled signal is to be produced from second phase-locked loop dress
The first frequency signal and the 4th frequency signal put；
The flag signals with the phase difference are sampled to obtain reset signal using the sampled signal, make the reset signal with
The phase difference is unrelated；And
Receive the reset signal and the 4th frequency signal through a flip-flop of the deserializer device, with it is corresponding generate with
Second frequency signal synchronization and the 5th identical frequency signal.
7. asynchronous conversion method as claimed in claim 6, the wherein time span of the time sequence allowance of the phase difference for this
One period subtracted the difference obtained by the period 3 of half.
8. asynchronous conversion method as claimed in claim 7, wherein when the flip-flop can generate it is same with the second frequency signal
When step and five identical frequency signal, the time span of the maximum delay phase of the phase difference is the one of the period 1
Difference obtained by the period 3 of half is partly subtracted, and the time span of the leading phase of maximum of the phase difference is then this
The half of period 1.
9. asynchronous conversion method as claimed in claim 6, further include makes this by the flag circuit of the deserializer device
Second frequency signal and the 5th frequency signal can be synchronized with the first frequency signal each other.
10. asynchronous conversion method as claimed in claim 6, wherein when the 5th frequency signal of flip-flop output can synchronize
In the first frequency signal when, which is received using the failing edge of the 5th frequency signal from ether
The data transfer signal of networked physics layer transceiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510887965.1A CN105512069B (en) | 2015-12-04 | 2015-12-04 | Deserializer device and its asynchronous conversion method |
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Citations (4)
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| CN102065208A (en) * | 2010-12-08 | 2011-05-18 | 南开大学 | Digital audio and video signal SerDes and realization method thereof |
| CN102340316A (en) * | 2011-09-07 | 2012-02-01 | 上海大学 | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer |
| CN104363008A (en) * | 2014-06-17 | 2015-02-18 | 上海兆芯集成电路有限公司 | Receiver |
| CN104391817A (en) * | 2014-12-03 | 2015-03-04 | 上海兆芯集成电路有限公司 | Electronic system synchronous with peripheral equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9378174B2 (en) * | 2013-11-04 | 2016-06-28 | Xilinx, Inc. | SERDES receiver oversampling rate |
| US9225324B2 (en) * | 2014-04-21 | 2015-12-29 | Qualcomm Incorporated | Circuit for generating accurate clock phase signals for high-speed SERDES |
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|---|---|---|---|---|
| CN102065208A (en) * | 2010-12-08 | 2011-05-18 | 南开大学 | Digital audio and video signal SerDes and realization method thereof |
| CN102340316A (en) * | 2011-09-07 | 2012-02-01 | 上海大学 | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer |
| CN104363008A (en) * | 2014-06-17 | 2015-02-18 | 上海兆芯集成电路有限公司 | Receiver |
| CN104391817A (en) * | 2014-12-03 | 2015-03-04 | 上海兆芯集成电路有限公司 | Electronic system synchronous with peripheral equipment |
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| 用于12.5 Gbit/s SerDes系统锁相环倍频器设计;茅俊伟 等;《半导体技术》;20121203;全文 * |
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