CN105448258A - Gate driver and display panel - Google Patents
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- CN105448258A CN105448258A CN201510992177.9A CN201510992177A CN105448258A CN 105448258 A CN105448258 A CN 105448258A CN 201510992177 A CN201510992177 A CN 201510992177A CN 105448258 A CN105448258 A CN 105448258A
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a gate driver and a display panel. The gate driver comprises at least one shift register group; the shift register group includes N stages of cascaded shift register units; the shift register units receive first input signals, second input signals and clock signals, and provide an output signal according to the first input signals, the second input signals and the clock signals; a first input signal received by the m-th stage of shift register unit is the output signal of the m-1-th stage of shift register unit; a second input signal received by the m-th stage of shift register unit is the output signal of the m+1-th stage of shift register unit, wherein m is a positive integer, and is larger than 1 and smaller than N; the first input signal received by the first stage of shift register unit is a first initial signal; the output signals of at least shift register units from the first stage of shift register unit to the N-1-th stage of shift register unit are all adopted as effective gate scanning signals; and the first initial signal is utilized to provide an effective gate scanning signal. According to the gate driver of the invention, the number of the shift register units is reduced.
Description
Technical field
The present invention relates to display technique field, be specifically related to a kind of gate drivers and apply the display panel of this gate drivers.
Background technology
Along with the development of optical technology and semiconductor technology, display panels (LiquidCrystalDisplay, and organic LED display panel (OrganicLightEmittingDiode LCD), etc. OLED) owing to having, body is more frivolous, cost and energy consumption is lower, reaction velocity is faster, excitation and brightness is more excellent and contrast more high for panel display board, has been widely used in each electronic product.But display product of the prior art still has part to be modified.Such as:
Display panel realizes display mainly through picture element matrix, and typically, each row pixel is all coupled to corresponding scanning grid line.In the display panel course of work, by gate drivers, the signals such as the clock signal of input are converted to the gated sweep signal controlling pixel on/off through shift register cell, such as, grid start signal and gate turn-off signal; Gated sweep signal is applied in turn the scanning grid line of each row pixel of display panel, gating can be carried out to each row pixel.
As shown in fig. 1, be a kind of structural representation of gate drivers.This gate drivers comprises 5 grades of shift register cell SR1 ~ SR5 of cascade, the first input end VIN1 of shift register cell SR1 receives start signal STV, the first input end VIN1 of shift register cell SR2 ~ SR5 receives the output signal of previous stage shift register cell, and the second input end VIN2 of shift register cell SR1 ~ SR4 receives the output signal of rear stage shift register cell as reset signal; In addition, each shift register cell also receives the first clock signal C K1 and second clock signal CKB1.Each shift register cell provides an output signal according to the signal received at its output terminal VOUT, and the gate drivers therefore in Fig. 1 can provide 5 row gate drive signals.
Along with the development of flat panel display, high resolving power and narrow edge frame product obtain increasing concern, in above-mentioned gate drivers, the shift register cell of One's name is legion can occupy very large chip area, and being unfavorable for increases effective display area and narrow frame design.
In addition, due to the shift register cell of the most final stage of gate drivers, namely the second input end VIN2 of shift register cell SR5 is not as reset signal input signal, and therefore its output terminal may the signal of output error.Shown in figure 2, be the analog waveform of the output signal of the shift register cell of the most final stage (such as the 5th grade) of gate drivers, obviously can find out that comparing previous stage (such as the 4th grade) has and repeatedly export.
Shown in figure 3, a solution arranges one virtual (Dummy) shift register cell DSR1 after the shift register cell of the most final stage of gate drivers, utilizes the output signal DS1 of dummy shift register cells D SR1 to provide reset signal to the shift register cell SR5 of most final stage; Simultaneously, due to when reverse scan, originally the shift register cell SR1 of the 1st grade is by becoming the shift register cell of most final stage, therefore, needs equally to arrange a dummy shift register cells D SR2 before the shift register cell SR1 of gate drivers the 1st grade.Further increase the area of gate drivers so undoubtedly; And the output signal DS1 of dummy shift register unit and DS2 cannot input to viewing area as effective gated sweep signal, be invalid gated sweep signal, therefore also need for the output signal DS1 of dummy shift register unit and DS2 additionally arranges load.
It should be noted that, dividing the information of invention only for strengthening the understanding to background of the present invention in above-mentioned background technology department, therefore can comprise the information do not formed prior art known to persons of ordinary skill in the art.
Summary of the invention
The object of the present invention is to provide a kind of gate drivers and apply the display panel of this gate drivers, for overcoming at least to a certain extent due to the restriction of correlation technique and defect and the one or more problems caused.
Other characteristics of the present invention and advantage become clear by by detailed description below, or the acquistion partially by practice of the present invention.
The one side of the embodiment of the present invention provides a kind of gate drivers, comprising:
At least one shift register group, shift register group described in each comprises the N level shift register cell of cascade, and wherein, N is positive integer, and N >=3;
Described shift register cell receives the first input signal, the second input signal and clock signal and provides an output signal according to described first input signal, the second input signal and clock signal;
Wherein, described first input signal that m level shift register cell receives is the output signal of m-1 level shift register cell, described second input signal that m level shift register cell receives is the output signal of described m+1 level shift register cell, wherein, m is positive integer, and 1<m<N;
Wherein, described first input signal of the 1st grade of shift register cell reception is one first start signal, at least the 1st grade of output signal to the described shift register cell of N-1 level is all as effective gated sweep signal, and utilizes described first start signal to provide effective gated sweep signal described in.
The another aspect of the embodiment of the present invention provides a kind of gate drivers, comprising:
At least one shift register group, shift register group described in each comprises the N level shift register cell of cascade, and wherein, N is positive integer, and N >=3;
Described shift register cell receives input signal and clock signal and provides an output signal according to described input signal and clock signal;
Wherein, the described input signal that m level shift register cell receives is the described output signal of m-1 level shift register cell, and wherein, m is positive integer, and 1<m≤N;
Wherein, the described input signal of the 1st grade of shift register cell reception is a start signal, and the output signal of all described shift register cells all as effective gated sweep signal, and utilizes described start signal to provide effective gated sweep signal described in.
The one side again of the embodiment of the present invention provides a kind of display panel, comprises any one gate drivers above-mentioned.
In sum, in example embodiment of the present invention, effective gated sweep signal is provided by utilizing start signal, effectively can reduce the quantity of shift register cell, and then the chip area of gate drivers can be made to reduce, for the display panel realizing more high resolving power and narrower frame provides technical support; Meanwhile, owing to saving the quantity of shift register cell, thus preparation technology can be simplified, compression preparation cost.
Accompanying drawing explanation
Describe its exemplary embodiment in detail by referring to accompanying drawing, above-mentioned and further feature of the present invention and advantage will become more obvious.
Fig. 1 is the structural representation of a kind of gate drivers in prior art;
Fig. 2 is the oscillogram of gate drivers part output signal in Fig. 1;
Fig. 3 is the structural representation of another kind of gate drivers in prior art;
Fig. 4 is the structural drawing of a kind of gate drivers that the embodiment of the present invention provides;
Fig. 5 is the waveform schematic diagram of gate drivers output signal in Fig. 2;
Fig. 6 is the structural representation of another gate drivers that the embodiment of the present invention provides;
Fig. 7 is the structural representation of another gate drivers that the embodiment of the present invention provides;
Fig. 8 is the structural representation of another gate drivers that the embodiment of the present invention provides;
Fig. 9 is the structural representation of another gate drivers that the embodiment of the present invention provides;
Figure 10 is the structural representation of another gate drivers that the embodiment of the present invention provides;
Figure 11 is the structural representation of another gate drivers that the embodiment of the present invention provides;
Figure 12 is the structural representation of another gate drivers that the embodiment of the present invention provides.
Embodiment
More fully exemplary embodiment is described referring now to accompanying drawing.But exemplary embodiment can be implemented in a variety of forms, and should not be understood to be limited to embodiment set forth herein; On the contrary, these embodiments are provided to make the present invention comprehensively with complete, and the design of exemplary embodiment will be conveyed to those skilled in the art all sidedly.In the drawings, in order to clear, exaggerate, be out of shape or simplify geomery.Reference numeral identical in the drawings represents same or similar structure, thus will omit their detailed description.
In addition, described feature, structure or step can be combined in one or more embodiment in any suitable manner.In the following description, provide many details thus provide fully understanding embodiments of the invention.But, one of skill in the art will appreciate that and can put into practice technical scheme of the present invention and not have in described specific detail one or more, or other method, step, structure etc. can be adopted.
A kind of gate drivers is provide firstly in this example embodiment.Gate drivers comprises at least one shift register group.With reference to the structural representation that figure 4, Fig. 4 is a kind of gate drivers that the embodiment of the present invention provides, wherein, gate drivers comprises a shift register group, and shift register group comprises the N level shift register cell of cascade, and wherein, N is positive integer, and N >=3; Equal 5 for N in Fig. 4 to be described, namely shift register group comprises the 1st grade of shift register cell SR1 of cascade to the 5th grade of shift register cell SR5; But those skilled in the art are it is easily understood that N in fact can for the positive integer being greater than arbitrarily 2.
Each above-mentioned shift register cell includes first input end VIN1, second input end VIN2, clock signal terminal CK1, clock signal terminal CKB1 and output terminal VOUT, wherein, the first input end VIN1 of each shift register cell can receive one first input signal, second input end VIN2 can receive one second input signal, clock signal terminal CK1 and clock signal terminal CKB1 may be used for reception first clock signal C K1 and second clock signal CKB1, and, each shift register cell is according to the first input signal received, second input signal and clock signal provide an output signal at its output terminal VOUT.In this example embodiment, shift register cell can be made up of elements such as multiple switching transistor and electric capacity, shift register cell can be amorphous silicon (AlphaSilica) semiconductor shift register cell, and namely switching transistor is wherein amorphous silicon type thin film transistor (TFT) (a-SiTFT); Also can be oxide (Oxide) semiconductor shift register cell, namely switching transistor be wherein oxide type thin film transistor (TFT) (oxideTFT); Or low temperature polycrystalline silicon (LTPS) semiconductor shift register cell, namely switching transistor is wherein the shift register cell of the other types such as low-temperature polysilicon thin film transistor (TFT) (LTPS-TFT), does not do particular determination in this exemplary embodiment to this.
Wherein, first input signal of the first input end VIN1 reception of m level shift register cell is the output signal of m-1 level shift register cell output terminal, second input signal of the second input end VIN2 reception of m level shift register cell is the output signal of m+1 level shift register cell output terminal VOUT, wherein, m is positive integer, and 1<m<N.Such as, first input signal of the first input end VIN1 reception of the 2nd grade of shift register cell is the output signal of the 1st grade of shift register cell output terminal VOUT, and the second input signal of the second input end VIN2 reception of the 2nd grade of shift register cell is the output signal of 3rd level shift register cell output terminal VOUT; First input signal of the first input end VIN1 reception of 3rd level shift register cell is the output signal of the 2nd grade of shift register cell output terminal VOUT, and the second input signal that the second input end VIN2 of 3rd level shift register cell receives is output signal of the 4th grade of shift register cell output terminal VOUT etc.
Continue with reference to figure 4, in this example embodiment, the first input signal that the first input end VIN1 of the 1st grade of shift register cell SR1 receives is one first start signal STV1, the 1st grade of output signal to the 5th grade of shift register cell output terminal VOUT is all as effective gated sweep signal, i.e. gated sweep signal S2 ~ S6; In this example embodiment, effective gated sweep signal refers to and is input to viewing area, for the sweep signal of the switching transistor in the pixel column that on/off is connected with gate driver circuit, is namely different from the invalid gated sweep signal in background technology.Further, the first start signal STV1 can also be utilized in this example embodiment to provide an effective gated sweep signal, therefore, with reference to figure 5, Fig. 5 is the waveform schematic diagram of gate drivers output signal in Fig. 2, as we know from the figure, the gate drivers in Fig. 4 can utilize 5 grades of shift register cells to generate 6 effective gated sweep signal S1 ~ S6.
Seen from the above description, gate drivers in this example embodiment provides effective gated sweep signal by utilizing start signal, effectively can reduce the quantity of shift register cell, and then the chip area of gate drivers can be made to reduce, for the display panel realizing more high resolving power and narrower frame provides technical support; Meanwhile, owing to saving the quantity of shift register cell, thus preparation technology can be simplified, compression preparation cost.
With reference to the structural representation that figure 6, Fig. 6 is another gate drivers that the embodiment of the present invention provides, as shown in FIG., when reverse scan, originally the shift register cell SR1 of the 1st grade will become the shift register cell of most final stage; Now, in diagram, VIN2 is first input end, and VIN1 is the second input end, and originally the shift register cell SR5 of most final stage will become the 1st grade of shift register cell, and its input end VIN2 receives the first start signal STV1.As mentioned above, the first start signal STV1 can be utilized in this example embodiment to provide effective gated sweep signal.Namely, no matter in forward scan or reverse scan, every start signal that utilizes provides effective gated sweep signal all to belong to protection scope of the present invention.
In other example embodiment of the present invention, one second start signal STV2 can also be utilized at the end of forward scan to input to most final stage, i.e. the second input end VIN2 of N level shift register cell.Such as, be the structural representation of another gate drivers that the embodiment of the present invention provides with reference to figure 7, Fig. 7, wherein, the second input signal of the 5th grade of shift register cell reception is one second start signal STV2.By utilizing the second start signal STV2 as the second input signal of most final stage shift register cell, then can provide the second input signal without the need to arranging dummy shift register unit after N level shift register cell, and then the chip area of gate drivers can be made further to reduce.
In this example embodiment, the second start signal STV2 and the first start signal STV1 interval one frame (Frame), such as, the first start signal STV1 is the start signal of X frame, and the second start signal STV2 is the start signal of X+1 frame.In this example embodiment, a frame refers to that gate drivers from the 1st grade to the whole forward scan of N level shift register cell once or revert all run-down.Picture display on, can be image refreshing once.
Further, the second start signal can also be utilized in this example embodiment to provide an effective gated sweep signal, namely except effective gated sweep signal that all shift registers itself export, the first start signal and the second start signal in this example embodiment, can also be utilized additionally to provide two effective gated sweep signals.Such as, the gate drivers in Fig. 7 can utilize 5 grades of shift register cells to generate 7 effective gated sweep signals.Compared to existing technology, while avoiding, virtual (Dummy) shifting deposit unit is set, effectively can reduce the quantity of shift register cell further, the chip area of gate drivers can be made further to reduce.
With reference to the structural representation that figure 8, Fig. 8 is another gate drivers that the embodiment of the present invention provides; In this example embodiment, each shift register cell can also comprise a reset signal end RST.Reset signal end RST is for receiving a reset signal, thus reset signal can be utilized to reset to each shift register cell, such as, can before present frame starts scanning, reset signal is utilized to remove the residual voltage signal of previous frame, avoid the gated sweep signal of gate drivers output error, and promote the waveform accuracy of the gated sweep signal exported.
In addition, gate drivers described in this example embodiment can without the need to arranging dummy shift register unit, and shift register cell at different levels all can correctly export, in the gate drivers of therefore this example embodiment, the output terminal of each shifting deposit unit can all be electrically connected with the gate line of in display panel, the pixel column connected for this gate line provides cut-in voltage, avoids the waste of the signal generated.
In the above-mentioned embodiment of this example, comprise a shift register group for gate drivers and be described.In other embodiments of this example, gate drivers also can comprise more than one shift register group.Such as, with reference to figure 9, Fig. 9 is the structural representation of another gate drivers that the embodiment of the present invention provides, wherein, gate drivers comprises the first shift register group and the second shift register group, first shift register group comprises shift register cell SR1A to SR5A, second shift register group comprises shift register cell SR1B to SR5B, shift register cell in shift register cell in first shift register group and the second shift register group is staggered to be spaced, for example, in Fig. 9, in gate drivers, putting in order of shift register cell can be SR1A, SR1B, SR2A, SR2B, SR3A, SR3B, SR4A, SR4B, SR5A, SR5B, put in order by above-mentioned, can interlock and export gated sweep signal, reduce the time interval between adjacent two gated sweep signals.But those skilled in the art it is easily understood that, when gate drivers comprises the shift register group of more than three or three, above-mentioned arrangement mode is applicable equally, such as, gate drivers can also comprise the 3rd shift register group, 3rd shift register group can comprise shift register cell SR1C to SR5C, then putting in order of shift register cell can be SR1A, SR1B, SR1C, SR2A, SR2B, SR2C etc.
Another kind of gate drivers is additionally provided in this example embodiment.This gate drivers comprises at least one shift register group.With reference to the structural representation that Figure 10, Figure 10 are another gate drivers that the embodiment of the present invention provides, wherein, gate drivers can comprise a shift register group, and shift register group can comprise the N level shift register cell of cascade, wherein, N is positive integer, and N >=2; Equal 5 for N in Figure 10 to be described, namely shift register group can comprise the 1st grade of shift register cell SR1 of cascade to the 5th grade of shift register cell SR5; But those skilled in the art are it is easily understood that N in fact can for the positive integer being greater than arbitrarily 1.
Each shift register cell includes input end VIN, clock signal terminal CK1, clock signal terminal CKB1 and output terminal VOUT, wherein, the input end VIN of each shift register cell can receive an input signal, clock signal terminal CK1 and clock signal terminal CKB1 may be used for reception first clock signal C K1 and second clock signal CKB1, further, each shift register cell provides an output signal according to the input signal received and clock signal at its output terminal VOUT.In this example embodiment, shift register cell can be made up of elements such as multiple switching transistor and electric capacity, shift register cell can be amorphous silicon (AlphaSilica) semiconductor shift register cell, also can be the shift register cell of the other types such as oxide semiconductor shift register cell, low temperature polycrystalline silicon shift register cell, in this exemplary embodiment, particular determination not done to this.
Wherein, the first input signal of the input end VIN reception of m level shift register cell is the output signal of m-1 level shift register cell output terminal VOUT, and wherein, m is positive integer, and 1<m<N.Such as, the input signal of the input end VIN reception of the 2nd grade of shift register cell is the output signal of the 1st grade of shift register cell output terminal VOUT, and the input signal that the input end VIN of 3rd level shift register cell receives is output signal of the 2nd grade of shift register cell output terminal VOUT etc.
Continue with reference to Figure 10, in this example embodiment, the input signal that the first input end VIN of the 1st grade of shift register cell SR1 receives is a start signal STV, the 1st grade of output signal to the 5th grade of shift register cell output terminal VOUT is all as effective gated sweep signal, i.e. gated sweep signal S2 ~ S6.Further, also utilize start signal STV to provide an effective gated sweep signal in this example embodiment, therefore, the gate drivers in Figure 10 can utilize 5 grades of shift register cells to generate 6 effective gated sweep signals.
Seen from the above description, gate drivers in this example embodiment provides effective gated sweep signal by utilizing start signal STV, effectively can reduce the quantity of shift register cell, and then the chip area of gate drivers can be made to reduce, for the display panel realizing more high resolving power and narrower frame provides technical support; Meanwhile, owing to saving the quantity of shift register cell, thus preparation technology can be simplified, compression preparation cost.
With reference to the structural representation that Figure 11, Figure 11 are another gate drivers that the embodiment of the present invention provides, wherein, in this example embodiment, each shift register cell can also comprise a reset signal end RST.Reset signal end RST is for receiving a reset signal, thus reset signal can be utilized to reset to each shift register cell, thus can before current frame signal starts scanning, utilize reset signal to remove the residual voltage signal of previous frame signal, avoid the gated sweep signal of gate drivers output error and promote the waveform accuracy of the gated sweep signal exported.
In addition, gate drivers described in this example embodiment can without the need to arranging dummy shift register unit, and shift register cell at different levels all can correctly export, in the gate drivers of therefore this example embodiment, the output terminal of each shifting deposit unit can all be electrically connected with the gate line of in display panel, the pixel column connected for this gate line provides cut-in voltage, avoids the waste of the signal generated.
In the above-mentioned embodiment of this example, comprise a shift register group for gate drivers and be described.In other embodiments of this example, gate drivers also can comprise more than one shift register group.Such as, with reference to Figure 12, Figure 12 is the structural representation of another gate drivers that the embodiment of the present invention provides, wherein, gate drivers can comprise the first shift register group and the second shift register group, first shift register group can comprise shift register cell SR1A to SR5A, second shift register group can comprise shift register cell SR1B to SR5B, shift register cell in shift register cell in first shift register group and the second shift register group is staggered to be spaced, for example, in Figure 12, in gate drivers, putting in order of shift register cell can be SR1A, SR1B, SR2A, SR2B, SR3A, SR3B, SR4A, SR4B, SR5A, SR5B, put in order by above-mentioned, can interlock and export gated sweep signal, reduce the time interval between adjacent two gated sweep signals.But those skilled in the art it is easily understood that, when gate drivers comprises the shift register group of more than three or three, above-mentioned arrangement mode is applicable equally, such as, gate drivers can also comprise the 3rd shift register group, 3rd shift register group can comprise shift register cell SR1C to SR5C, then putting in order of shift register cell can be SR1A, SR1B, SR1C, SR2A, SR2B, SR2C etc.
Further, this example embodiment additionally provides a kind of display panel, and this display panel comprises any one above-mentioned gate drivers, but is not limited thereto.Because the gate drivers used has less chip area, therefore the effective display area of this display panel is increased, and is conducive to the resolution promoting display panel; Meanwhile, what the frame of this display panel can do is narrower.In this exemplary embodiment, this display panel can be display panels or OLED display panel, in other exemplary embodiment of the present invention, this display panel also may be PLED (PolymerLight-EmittingDiode, polymer LED) display panel, PDP (PlasmaDisplayPanel, plasma shows) other panel display boards such as display panel, namely do not limit to the scope of application in this example embodiment especially.
In sum, in example embodiment of the present invention, effective gated sweep signal is provided by utilizing start signal, effectively can reduce the quantity of shift register cell, and then the chip area of gate drivers can be made to reduce, for the display panel realizing more high resolving power and narrower frame provides technical support; Meanwhile, owing to saving the quantity of shift register cell, thus preparation technology can be simplified, compression preparation cost.
The present invention is described by above-mentioned related embodiment, but above-described embodiment is only enforcement example of the present invention.Must it is noted that the embodiment disclosed limit the scope of the invention.On the contrary, change done without departing from the spirit and scope of the present invention and retouching, all belong to scope of patent protection of the present invention.
Claims (12)
1. a gate drivers, is characterized in that, comprising:
At least one shift register group, shift register group described in each comprises the N level shift register cell of cascade, and wherein, N is positive integer, and N >=3;
Described shift register cell receives the first input signal, the second input signal and clock signal and provides an output signal according to described first input signal, the second input signal and clock signal;
Wherein, described first input signal that m level shift register cell receives is the output signal of m-1 level shift register cell, described second input signal that m level shift register cell receives is the output signal of m+1 level shift register cell, wherein, m is positive integer, and 1<m<N;
Wherein, described first input signal of the 1st grade of shift register cell reception is one first start signal, at least the 1st grade of output signal to the described shift register cell of N-1 level is all as effective gated sweep signal, and utilizes described first start signal to provide effective gated sweep signal described in.
2. gate drivers according to claim 1, it is characterized in that, wherein, described second input signal that N level shift register cell receives is one second start signal, and the output signal of all described shift register cells is all as effective gated sweep signal.
3. gate drivers according to claim 2, is characterized in that, utilizes described second start signal to provide effective gated sweep signal described in.
4. gate drivers according to claim 2, is characterized in that, described second start signal and described first initial sigtnal interval one frame.
5. gate drivers according to claim 1, is characterized in that, described shift register cell also receives a reset signal, and described reset signal resets to described shift register cell.
6. gate drivers according to claim 1, is characterized in that, described gate drivers comprises the first shift register group and the second shift register group; Shift register cell in shift register cell in described first shift register group and described second shift register group is staggered to be spaced.
7. the gate drivers according to claim 1-6 any one, is characterized in that, does not comprise dummy shift register unit in described gate drivers.
8. a gate drivers, is characterized in that, comprising:
At least one shift register group, shift register group described in each comprises the N level shift register cell of cascade, and wherein, N is positive integer, and N >=3;
Described shift register cell receives input signal and clock signal and provides an output signal according to described input signal and clock signal;
Wherein, the described input signal that m level shift register cell receives is the described output signal of m-1 level shift register cell, and wherein, m is positive integer, and 1<m≤N;
Wherein, the described input signal of the 1st grade of shift register cell reception is a start signal, and the output signal of all described shift register cells all as effective gated sweep signal, and utilizes described start signal to provide effective gated sweep signal described in.
9. gate drivers according to claim 8, is characterized in that, described shift register cell also receives a reset signal, and described reset signal resets to described shift register cell.
10. gate drivers according to claim 8, is characterized in that, described gate drivers comprises the first shift register group and the second shift register group; Shift register cell in shift register cell in described first shift register group and described second shift register group is staggered to be spaced.
11. gate drivers according to Claim 8 described in-10 any one, is characterized in that, not comprise dummy shift register unit in described gate drivers.
12. 1 kinds of display panels, is characterized in that, comprise the gate drivers described in claim 1-11 any one.
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