CN105432020A - Quantization noise coupling delta sigma ADC with a delay in the main DAC feedback - Google Patents
Quantization noise coupling delta sigma ADC with a delay in the main DAC feedback Download PDFInfo
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- CN105432020A CN105432020A CN201480039179.XA CN201480039179A CN105432020A CN 105432020 A CN105432020 A CN 105432020A CN 201480039179 A CN201480039179 A CN 201480039179A CN 105432020 A CN105432020 A CN 105432020A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
- H03M3/496—Details of sampling arrangements or methods
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Abstract
A delta-sigma modulator has a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function, a second summing point adding an output signal from said transfer function to the input signal and subtracting a second feedback signal, a first integrator receiving an output signal from the second summing point, a quantizer receiving an output signal from the integrator and generating an output bitstream, and a digital-to-analog converter receiving the bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay.
Description
related application
Subject application advocates the apply on June 12nd, 2013 the own together the 61/834th, the priority of No. 207 U.S. Provisional Patent Application cases; And described temporary patent application case is hereby in order to all objects are incorporated herein by reference.
Technical field
The present invention relates to delta-sigma modulator, particularly relate to quantizing noise coupling delta-sigma ADC.
Background technology
At IEEEJSSC paper with reference in (" there is 8.1mW, 82dB delta-sigma ADC (An8.1mW; 82dBDelta-SigmaADCwith1.9MHzBWand-98dBTHD) of 1.9MHzBW and-98dBTHD; author K.Lee, M.R.Miller and G.C.Temes "), introduce the delta-sigma A/D converter (ADC) with quantizing noise coupling (QNC).Quantizing noise is coupled as the main analog domain transposition by truncated error feedback in the digital domain.Its thought is that the quantizing noise error produced by the quantizer of ADC is remembered and feeds back to quantizer input, makes this error be integrated to next sample process.Fig. 1 shows the block diagram how realizing the respective instance of this kind of situation.For example, Fig. 1 shows and is used for next sample (wherein deducting this error from input value) and difference between treatment of simulated sample and the numeral sample of reality through changing by analog sample and the analog value of the numeral sample of reality through changing being subtracted each other and being stored.This just causes the truncated error feedback be used in digital filtering to be shifted to analog domain.Therefore, quantization error stores in memory, not lose any information and to guarantee this information to be integrated to next sample rightly.This means further the noise shaping of quantizing noise and therefore means that better signal is to quantizing noise ratio (SNQR).Cause the reason of much better signal to quantizing noise ratio to be that the error produced by quantizer is not lost at each sample, but be again integrated to signal at each sample place to quantize.Table 1 show depend on through select over-sampling rate (OSR) conventional sigma-delta ADC with use quantize noise coupling (QNC) through improving the difference between sigma-delta ADC.
Table 1
In aforesaid articles of reference, described the embodiment of this quantizing noise coupling, and described embodiment uses feedforward summing amplifier (using feedforward summing amplifier to provide low distortion transfer function in the delta-sigma ADC that is everlasting).By adding the multiple capacitors being in ping pong scheme in the feedback of amplifier, and controlling these capacitors by adding phase place, realizing quantization error feedback.This embodiment needs additional capacitor and control phase and extra D/A converter (DAC) (having extra delay at the signal of the input of this extra DAC) (Fig. 2 see articles of reference).
This embodiment can be loaded down with trivial details and is unsuitable for needs two phase places to the DAC embodiment processing DAC and export (as the own together the 7th, 102,5 grades of DAC described in No. 558 United States Patent (USP)s, described patent is hereby in order to all objects are incorporated herein by reference).Fig. 8 shows according to the DAC relevant portion of the the 7th, 102, No. 558 United States Patent (USP) and the circuit diagram of integrator (it can produce 5 different voltage levels).As demonstrated in Figure 8, describe to be used for the capacitor switching-over array of Pyatyi feedback D/A converter (DAC) and the schematic circuit of differential amplifier.Described Pyatyi feedback DAC (usually being represented by numeral 100) comprises switching sequence, and two phase places (precharge+transfer) period that described switching sequence shifts in differential charge produces five equally spaced quantities of electric charge.Therefore, five charge levels be equally spaced can be C*VREF, C*VREF/2,0 ,-C*VREF/2 and-C*VREF.Reference voltage (VREF=VREFP-VREFM) charging circuit is represented by numeral 102 usually, and comprises transfer reference capacitors 132a and 132b and switch 112,114 and 116.The remainder of particular exemplary embodiment comprises voltage input capacitors 130a and 130b, switch 104,106,108 and 110 and differential operational amplifier 150 (it has feed-back sampling capacitors 134a and 134b).Switch 108a and 108b can relate to common mode operation, and switch 108c can relate to differential signal operation.
VREFP and VREFM represents the voltage at differential reference input terminal place.Reference voltage VREF=VREFP-VREFM.VINP and VINM represents the voltage at differential input signal terminal place.Applied signal voltage VIN=VINP-VINM.Transfer reference capacitors 132a and 132b can equal C/2.Input sample capacitor 130a and 130b can equal A*C/2.Feedback condenser 134a and 134b can equal C.Input voltage is: VIN=VINP-VINM, and output voltage is VOUT=VOUTP-VOUTM.The gain of the circuit shown is A.
The switching sequence for these five level is shown in Fig. 9 a to 9e.The switching sequence of switch 104 to 116 in order to obtain particular exemplary circuit illustrated in fig. 8 five charge level C*VREF, C*VREF/2 be equally spaced, 0 ,-C*VREF/2 and-C*VREF." 1 " logic level is depicted in the respective switch in make position, and " 0 " logic level is depicted in the respective switch in open position.Fig. 9 a to 9e further illustrates the non-overlapping delays between switch 104 to 116 so that the short circuit between preventing from inputting and guarantee to be connected to the always the first one disconnection of switch of summing junction.Switch 104 to 116 all disconnects between time 202 and time 204 (closedown-logical zero).Time 202 represents the end of the charge phase of transfer reference capacitors 132a and 132b, and on input capacitor 130a and 130b through sampling VIN electric charge.Time 204 represents the beginning of the transfer phase place of the electric charge on transfer reference capacitors 132a and 132b.
For realizing better readability, Fig. 2 shows the single-ended embodiment according to above-mentioned article.But actual embodiment will be fully differential.As visible, this embodiment needs extra D/A converter (DAC), for the extra delayed signal of DAC input and the table tennis feedback condenser network of complexity in summing amplifier, it implements loaded down with trivial details as mentioned, and this is because it needs extra phase and the many extra switch in the feedback of operational amplifier.Fig. 2 shows that described phase place is divided into odd number phase place and even phase.
As in the circuit diagram in Fig. 2 and the table that is associated in this conventional embodiment of showing, quantize the end occurring in phase place P1, quantize feedback DAC and sample in next phase place P1 and shift in next phase place P2, there is a sample delay; And main DAC samples and shifts in the phase place P1 of next sample in the phase place P2 of same sample, not there is delay.Therefore, this conventional conception needs worthless complicated embodiment.
Summary of the invention
Therefore there are the needs of simpler embodiment to quantizing noise coupling, cost revises signal transfer function a little, if use large over-sampling rate (OSR) in delta-sigma ADC, so signal transfer function be revised as very little.
According to embodiment, delta-sigma modulator can comprise: the first summing junction, and it deducts the first feedback signal from input signal and result is forwarded to transfer function; Second summing junction, it adds the output signal from described transfer function to described input signal and deducts the second feedback signal; First integrator, it receives output signal from described second summing junction; Quantizer, it receives output signal from described integrator and produces output bit stream; And D/A converter, it receives described bit stream, and first and second feedback signal wherein said is the output signal from described D/A converter postponed by single sample delay.
According to another embodiment of delta-sigma modulator, described delta-sigma modulator can use charge phase and transfer phase place to operate, and performs quantification in described transfer phase place.According to another embodiment of delta-sigma modulator, described D/A converter (DAC) can be implemented by two Charger transfer DAC, and described two Charger transfer DAC are configured to produced analog feedback signal to postpone a sample separately.According to another embodiment of delta-sigma modulator, described delta-sigma modulator can be optionally oversampled.According to another embodiment of delta-sigma modulator, described delta-sigma modulator can be n rank, multiloop or multidigit modulator.According to another embodiment of delta-sigma modulator, described transfer function can be provided by second integral device, described second integral device produces output signal, described output signal is fed to the first amplifier to be fed to third integral device via the second amplifier, the output signal of wherein said third integral device is amplified by the 3rd amplifier, and the output signal of described 3rd amplifier is added to the output signal of described first amplifier.According to another embodiment of delta-sigma modulator, described quantizer can be n level multidigit variable resolution quantisation device.According to another embodiment of delta-sigma modulator, charge phase can be not overlapping with transfer phase place subsequently.According to another embodiment of delta-sigma modulator, the end that described delta-sigma modulator can be included in described transfer phase place further produces and in order to latch for the latch signal of the signal of described quantizer.According to another embodiment of delta-sigma modulator, summing junction can be implemented by the node be connected with the first terminal of at least the first capacitor and the second capacitor, and the second terminal reception of first and second capacitor wherein said treats the electric charge added via respective switch.According to another embodiment of delta-sigma modulator, follow the univoltage DAC of single sample delay after described D/A converter (DAC) can be, the output of wherein said single sample delay is coupled with first and second summing junction described.
According to another embodiment, a kind of method for operating delta-sigma modulator can comprise: deduct the first feedback signal from input signal and result is forwarded to transfer function; Add the output signal from described transfer function to described input signal and deduct the second feedback signal and integration gained output signal; Quantize the described signal through integration and produce output bit stream; And described bit stream translation become analog signal and by single sample delay to postpone described analog signal to provide first and second feedback signal described.
According to another embodiment of described method, charge phase and transfer phase place can be used to perform described method, and perform quantification in described transfer phase place.According to another embodiment of described method, D/A switch can be implemented by two Charger transfer D/A converters (DAC), and described two Charger transfer D/A converters (DAC) are configured to produced analog feedback signal to postpone a sample separately.According to another embodiment of described method, described delta-sigma modulator can be optionally oversampled.According to another embodiment of described method, quantizer can be n level multidigit variable resolution quantisation device.According to another embodiment of described method, described transfer function can be provided by second integral device, described second integral device produces output signal, described output signal is fed to the first amplifier to be fed to third integral device via the second amplifier, the output signal of wherein said third integral device is amplified by the 3rd amplifier, and the output signal of described 3rd amplifier is added to the output signal of described first amplifier.According to another embodiment of described method, described quantization step can be performed by n level multidigit variable resolution quantisation device.According to another embodiment of described method, charge phase can be not overlapping with transfer phase place subsequently.According to another embodiment of described method, the end that described method can be included in described transfer phase place further produces and in order to latch for the latch signal of the signal of described quantizer.According to another embodiment of described method, described interpolation step can be implemented by the node be connected with the first terminal of at least the first capacitor and the second capacitor, and the second terminal reception of first and second capacitor wherein said treats the electric charge added via respective switch.According to another embodiment of described method, change described bit stream and perform by following the univoltage DAC of single sample delay below, the output of wherein said single sample delay is coupled with first and second summing junction.
Accompanying drawing explanation
Can obtain more complete understanding of the present invention by reference to following description by reference to the accompanying drawings, in the accompanying drawings:
Fig. 1 illustrates the schematic block diagram of the conventional sigma-delta ADC using QNC,
Fig. 2 illustrates the example according to the embodiment of the sigma-delta ADC of Fig. 1;
Fig. 3 illustrates the schematic block diagram of delta-sigma ADC according to various embodiments of the present invention;
Fig. 4 a and b illustrates another schematic block diagram of delta-sigma ADC according to various embodiments of the present invention;
Fig. 5 illustrates the embodiment about the block diagram of Fig. 4 b.
Fig. 6 shows the transfer function of the sigma-delta ADC of use QNC according to various embodiments of the present invention;
Fig. 7 shows the transfer function convergent-divergent of the bandwidth paid close attention to;
Fig. 8 shows conventional 5 grades of DAC; And
Fig. 9 a to e shows the possible switching sequence of circuit demonstrated in Figure 8.
Embodiment
With reference now to graphic (especially Fig. 3 and 4a and b), the schematically block diagram of illustrated example embodiment.Similar components in graphic will by similar numeral.
According to various embodiment, quantizing noise as show in Figure 3 can be used to be coupled delta-sigma ADC embodiment is provided.Input signal is fed to the first summing junction 310 and the second summing junction 330.The output of the first summing junction 310 is forwarded to transfer function 320, and the output of transfer function 320 adds input signal to by the second summing junction 330.The output of the second summing junction 330 is by integrator 340 integration, and the output of integrator 340 is fed to A/D converter 350 (ADC).ADC350 provides the output bit stream being fed back to D/A converter 360 (DAC).The output of DAC360 is fed to the second summing junction 330 by first delay element 370 with negative sign (subtracting) and is fed to the first summing junction 310 by second delay element 380 with negative sign (subtracting).
Simplified embodiment is carried out by adding the second delay 380 in primary feedback DAC signal path.According to an embodiment, realize this delay 380 by performing quantification during phase place P2.Therefore, the end of the P2 during feedforward (FF) phase place quantizes, and applies DAC signal at next phase place P1 and P2 place.Concept is contrary therewith, and in article mentioned above, in the conventional system, to quantize to occur in phase place P1 and main DAC gives it in phase place P2 exports, in other words, DAC samples in phase place P2.
As shown in fig. 3, when DAC produces voltage, only single DAC360 is necessary.But, as modal, when using Charger transfer DAC, the independent DAC generally for each path is necessary, one (primary feedback DAC) is for the first summing junction 310, and one (quantization error feedback DAC) is for the second summing junction 330.Fig. 4 a and b shows the block diagram of this type of embodiment using Charger transfer DAC.
Fig. 4 a and 4b is illustrated in the embodiment of the embodiment according to some embodiments when the second order single loop modulator using feedforward integrator cascade (CIFF) topology.Other topologys many can be used for embodiment and the present invention does not limit by this one exemplary embodiment.Quantizer is also not limited to any specific embodiment (such as, 5 grades of quantizers).
As Fig. 4 a, b one exemplary embodiment shown, analog input signal is that the amplifier/driver 405 by having COEFFICIENT K is fed to the driver 410 with coefficient b1 and the amplifier/driver 435 with coefficient b3.The coefficient of various amplifier/driver provides to double the factor of input signal, and the described factor can be greater than, be equal to or less than 1.The output of driver 410 is forwarded to adder 415, and the output of adder 415 is fed to integrator 420.The output signal x1 of integrator 420 is forwarded to the amplifier/driver 425 with coefficient c2 and the amplifier/driver 445 with coefficient a1.The output of driver 425 is fed to integrator 430, and the output signal x2 of integrator 430 is fed to the amplifier/driver 440 with coefficient a2.The output of amplifier/driver 435,440 and 445 is added up by adder 450, and the output of adder 450 is carried signal y and is fed to quantizer 455.Quantizer 455 can be implemented by any way, such as (but being not limited to) multiple position quantizer.In particular, as in Fig. 4 a and 4b show, multidigit variable resolution quantisation device can be used.This quantizer can be depending on control signal and provides variable-resolution, for example, and 2,3 or 5 different stages.Described control signal (such as) can provide automatic shake by quasi-random sequence generator, and as known from the 7th, 961, No. 126 United States Patent (USP)s transferring applicant, and described patent is incorporated herein by reference hereby.But, other quantizer can be used according to various embodiment.
The output of quantizer 455 provides bit stream, and described bit stream is forwarded to decimation filter of digital (displaying) subsequently.In addition, when QNC without activation time (as in Fig. 4 a show), signal is fed back to multidigit DAC460, and the output of multidigit DAC460 is connected with the amplifier/driver 465 with coefficient c1, and the output signal of amplifier/driver 465 is deducted by the output signal from driver 410.
Fig. 4 b shows the same structure of QNC through activating.Now, the digital output signal of quantizer 455 is fed to quantization error feedback DAC480 and primary feedback DAC460.There is provided extra summing junction 470, it receives from the output signal of summing junction 450 and the output signal of multidigit DAC480.The output signal of adder 470 is subsequently by integrator 475 integration, and integrator 475 produces output signal y now, and output signal y is forwarded to quantizer 455 again.
Added this postpone as in Fig. 4 b helpful effect in the embodiment of showing, this is because quantization error feedback DAC480 can use input identical with primary feedback DAC460, so without the need to the extra delay of possibility necessity in other situation between two DAC.Other simplifies is can use feedforward (FF) amplifier in the very simple integrator stage configuration that citing is shown in such as Fig. 5.
Fig. 5 represents the summation junction point in all feedforwards (FF) path in difference embodiment.Forward path comprises the output of the driver 435,440 and 445 with coefficient b3, a2 and a1, is represented by differential signal VinP, VinN, x1P, x1N, x2P, x2N at this.Capacitor 526 is respectively by switch 502 or 514 Received signal strength VinN or common-mode signal VCM.Similarly, for capacitor 528, provide switch 504 and 516 for Received signal strength x1N; For capacitor 530, provide switch 506 and 518 for Received signal strength x2N; For capacitor 540, provide switch 508 and 520 for Received signal strength x2P; For capacitor 542, provide switch 510 and 522 for Received signal strength x1P; And for capacitor 544, provide switch 512 and 524 for Received signal strength VinP.Summing junction is by being represented by the node that capacitor 526,528,530,546,548,540,542,544 is connected with integrator by switch 550 and 552 respectively.
Integrator 475 is implemented by operational amplifier 570 and capacitor 560 and 562 and the switch 554,556 and 558 for P-branch and the switch 564,566 and 568 for R-branch.Second Charger transfer multidigit DAC480 is formed by unit 580 and for the sampling capacitor 546,548 of DAC480, and unit 580 comprises the set for the input switch of DAC480 and receives bit stream and reference voltage VREFP and VREFN.The embodiment of unit 580 (for example) can be similar to the embodiment of showing by means of the unit 102 in Fig. 8.Summing junction can be coupled with common-mode voltage VCM by switch 526 and 528.
Output OP, OM of the schematic diagram shown in Fig. 5 in the figure as Fig. 4 b the node y that shows, it is forwarded to multiple position quantizer 455 subsequently.Direct FF path in Fig. 4 a and 4b is the path that b3 represents gain, and it is from the input of sigma-delta modulator.First integrator 420 exports the x1 for being represented by differential signal x1P, x1N, and second integral device 430 exports the x2 for being represented by differential signal x2P, x2N.
As mentioned above, this embodiment uses two DAC460 and 480, and both receive identical input and synchronously work.Because according to this particular, DAC at two different some transfer charges, so need two DAC460 and 480.But other embodiment can only need univoltage DAC.
Circuit demonstrated in Figure 5 is controlled by two phase place P1 and P2, and it is typical for charge transfer system.Exemplary control signal P1, P2 and FF is shown in the lower right of Fig. 5.Table subsequently shows which switch which signal P1 or P2 controls, and wherein P1d and P2d represents the switching signal corresponding to signal P1 and P2, but described switching signal is slightly delayed with respect to the direct path dl to avoid charge injection problem.FF is the latch phase place of quantizer (not showing in Fig. 5) and occurs in the end of P2.In addition, corresponding reset signal " reset " controls switch 554 and 568 in operational amplifier feedback path and reseting logic reverse signal " reset_n " control switch 556,558,564,568 (as known in the art).Mentioned by above, export and sampled in P1 in P2 by quantizer ADC, therefore quantize to occur in P2.P1 is the maintenance phase place of integrator.It keeps the memory of previous sample, and therefore it keeps quantization error and DAC feedback.P2 shifts new sample data.After quantification in FF phase place, DAC input is latched.During next P1, DAC (for example, its can be as in US7102558 5 grades of DAC disclosing, such as, also shown in fig. 8, there is reference number 102) sample reference voltage VrefP, VrefN or common-mode voltage VCM=0, and in next P2, another reference voltage of DAC resampling or 0 and the difference of two phase places is transferred on feedback condenser 560,562.According to some embodiments, common-mode voltage can be not equal to 0, but differentially gives zero charge transfer.Two capacitors of its short circuit on N and P side.This brings out the delay of a sample in the process of DAC input.When not revising anything in DAC and use simple integral device level to perform QNC.Without the need to revising the coefficient in loop.
Reset switch (if being activated during P1) also easily can forbid integrator configuration and erasing memory between each sample.On this and DAC constant 0 inputs (it easily can implement in the combinational logic of DAC numeral input) combines and fully can forbid QNC and configure, and open embodiment and QNC close switching (switching such as, between Fig. 4 a and 4b) between embodiment as needed easily to realize QNC.
Table 2
| Switch | Control signal |
| 502,504,506,508,510,512 | P2d |
| 514,516,518,520,522,524, | P1d |
| 526,528 | P1 |
| 550,552 | P2 |
| 556,558,564,566 | reset_n |
| 554,568 | reset |
According to another embodiment, if VCM signal is substituted by the x1P for switch 516, substituted by the x1N for switch 522, substituted by the x2P for switch 518, substituted by the x2P for switch 520, substituted by the VinM for switch 524, substituted by the VinP for switch 514, so can realize the two samplings in each branch, thus cause the possible improvement of the signal to noise ratio of feed-forward block.Capacitor also can be reduced half by two sampling plan.This is applicable herein, because described piece is integrator stage and it can comprise all known improvement (such as, two sampling) in integrator stage to improve its signal to noise ratio.
No longer there are the needs to additional feedback capacitor and complicated table tennis configuration.Only there is a simple feedback capacitor (capacitor 560,562) and standard integral device level 475, wherein in phase place P1, realize sampling and be implemented in phase place P2 feedback condenser 560,562 transfer (as with reference to exemplary embodiment demonstrated in Figure 5 by clear).As mentioned above, this situation reason in the cards realizes quantizing during phase place P2.In phase place P2, perform quantification, it provides two DAC input of (primary feedback DAC460 and quantization error DAC480).At next phase place P1 place, in identical P1 phase place, it is provided first to export by sample new input signal and DAC of feedforward adder 470 (in integrator configuration).In phase place P2, DAC provides its second output (it needs two phase places to process described input) and meanwhile, described input is transferred to feedback condenser 560,562.DAC has the delay of a sample naturally, owing to its mode processed at this (its input is latched in the end of P2, and it spends next P1 and P2 to process input, thus provides single sample delay).Be nature like this herein, to such an extent as to can realize when not adding additional capacitor and phase place blocking/quantization error feedback needed for necessity postpone, it causes simpler framework to keep quantizing the benefit of noise coupling simultaneously.
As long as feedforward (FF) path is present in system (be simple integrator configuration to allow feedforward adder), and needs to realize in the end of phase place P2 quantizing, this better simply embodiment just can be used.Because of embodiment for this reason with there is the Charger transfer DAC compatibility of sample and shifting two phase places, therefore it is very useful.Minor defect with the addition of postpone and therefore revise transfer function compared with articles of reference in main DAC feedback.But, for enough large over-sampling rate (OSR), or enough little bandwidth, this amendment can be left in the basket (if the delay added is less, if or sample frequency is large compared with paid close attention to bandwidth, normally like this in over-sampled converter) and cause the pole slight perturbations of output spectrum (have in the current embodiment of second order single loop modulator of the OSR of 256 in use, be about less than 0.01dB).
Fig. 6 show for typical second order single loop modulator have QNC embodiment as Fig. 3 and 4b the signal transfer function of sigma-delta ADC shown.In classical case, single transfer function=1.Fig. 7 shows transfer function convergent-divergent, and for the bandwidth paid close attention to of OSR=256, deviation is less than 0.0002dB.
In sum, the better SNQR of delta-sigma modulator can be realized when not adding remarkable circuit.For example, according to an embodiment, an extra DAC and switch thereof is only needed, and without the need to active circuit.In addition, described embodiment is simplified compared with conventional delta-sigma modulator.
Although describe by reference to example embodiment of the present invention, describe and define embodiments of the invention, this type of with reference to not meaning that limitation of the present invention, and should not infer that this limits.Benefit from one of ordinary skill in the art of the present invention and should be understood that disclosed subject matter in form and can functionally have considerable amendment, change and equivalent.Of the present invention the embodiment described and describe is only example, and not limit scope of the present invention.
Claims (22)
1. a delta-sigma modulator, it comprises:
First summing junction, it deducts the first feedback signal from input signal and result is forwarded to transfer function;
Second summing junction, it adds the output signal from described transfer function to described input signal and deducts the second feedback signal;
First integrator, it receives output signal from described second summing junction;
Quantizer, it receives output signal from described integrator and produces output bit stream;
D/A converter, it receives described bit stream, and first and second feedback signal wherein said is the output signal from described D/A converter postponed by single sample delay.
2. delta-sigma modulator according to claim 1, wherein said delta-sigma modulator uses charge phase and transfer phase place to operate, and performs quantification in described transfer phase place.
3. delta-sigma modulator according to claim 2, wherein said D/A converter DAC is implemented by two Charger transfer DAC, and described two Charger transfer DAC are configured to produced analog feedback signal to postpone a sample separately.
4. delta-sigma modulator according to claim 1, wherein said delta-sigma modulator is optionally oversampled.
5. delta-sigma modulator according to claim 1, wherein said delta-sigma modulator is n rank, multiloop or multidigit modulator.
6. delta-sigma modulator according to claim 5, wherein said transfer function is provided by second integral device, described second integral device produces output signal, described output signal is fed to the first amplifier to be fed to third integral device via the second amplifier, the output signal of wherein said third integral device is amplified by the 3rd amplifier, and the output signal of described 3rd amplifier is added to the output signal of described first amplifier.
7. delta-sigma modulator according to claim 1, wherein said quantizer is n level multidigit variable resolution quantisation device.
8. delta-sigma modulator according to claim 3, wherein charge phase is not overlapping with transfer phase place subsequently.
9. delta-sigma modulator according to claim 9, its end being included in described transfer phase place further produces and in order to latch for the latch signal of the signal of described quantizer.
10. delta-sigma modulator according to claim 5, wherein summing junction is implemented by the node be connected with the first terminal of at least the first capacitor and the second capacitor, and the second terminal reception of first and second capacitor wherein said treats the electric charge added via respective switch.
11. delta-sigma modulators according to claim 1, wherein said D/A converter DAC follows the univoltage DAC of single sample delay after being, the output of wherein said single sample delay is coupled with first and second summing junction described.
12. 1 kinds for operating the method for delta-sigma modulator, it comprises:
Deduct the first feedback signal from input signal and result is forwarded to transfer function;
Add the output signal from described transfer function to described input signal and deduct the second feedback signal and integration gained output signal;
Quantize the described signal through integration and produce output bit stream;
Described bit stream translation is become analog signal, and postpones described analog signal to provide first and second feedback signal described by single sample delay.
13. methods according to claim 12, wherein use charge phase and transfer phase place to perform described method, and perform quantification in described transfer phase places.
14. methods according to claim 13, wherein D/A switch is implemented by two Charger transfer D/A converter DAC, and described two Charger transfer D/A converter DAC are configured to produced analog feedback signal to postpone a sample separately.
15. methods according to claim 12, wherein said delta-sigma modulator is optionally oversampled.
16. methods according to claim 14, wherein quantizer is n level multidigit variable resolution quantisation device.
17. methods according to claim 16, wherein said transfer function is provided by second integral device, described second integral device produces output signal, described output signal is fed to the first amplifier to be fed to third integral device via the second amplifier, the output signal of wherein said third integral device is amplified by the 3rd amplifier, and the output signal of described 3rd amplifier is added to the output signal of described first amplifier.
18. methods according to claim 12, wherein said quantization step is performed by n level multidigit variable resolution quantisation device.
19. methods according to claim 14, wherein charge phase is not overlapping with transfer phase place subsequently.
20. methods according to claim 19, its end being included in described transfer phase place further produces and in order to latch for the latch signal of the signal of described quantizer.
21. methods according to claim 17, wherein said interpolation step is implemented by the node be connected with the first terminal of at least the first capacitor and the second capacitor, and the second terminal reception of first and second capacitor wherein said treats the electric charge added via respective switch.
22. methods according to claim 12, wherein changing described bit stream is that the output of wherein said single sample delay is coupled with first and second summing junction by following the univoltage DAC of single sample delay to perform below.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| US14/301,948 US9054733B2 (en) | 2013-06-12 | 2014-06-11 | Quantization noise coupling delta sigma ADC with a delay in the main DAC feedback |
| US14/301,948 | 2014-06-11 | ||
| PCT/US2014/042069 WO2014201215A1 (en) | 2013-06-12 | 2014-06-12 | Quantization noise coupling delta sigma adc with a delay in the main dac feedback |
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Also Published As
| Publication number | Publication date |
|---|---|
| EP3008825A1 (en) | 2016-04-20 |
| EP3008825B1 (en) | 2021-04-07 |
| US9054733B2 (en) | 2015-06-09 |
| US20140368365A1 (en) | 2014-12-18 |
| CN105432020B (en) | 2019-01-22 |
| WO2014201215A1 (en) | 2014-12-18 |
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