CN105406864A - Wide-band high-speed frequency hopping frequency synthesizer and working method thereof - Google Patents

Abstract

The invention belongs to the wireless communication equipment field and discloses a wide-band high-speed frequency hopping frequency synthesizer and a working method thereof. The output end of a first oscillator is connected with the reference frequency input end of a phase-locked loop circuit, the input end of a first DDS and the input end of a second DDS; the output end of the phase-locked loop circuit is connected with the input end of an active loop filter; the output end of the active loop filter is connected with the input end of a voltage-controlled oscillator; the output end of the voltage-controlled oscillator is connected with the local frequency input end of an IQ modulator; the output end of the first DDS is connected with the input end of a first filter; the output end of the first filter is connected with the I-path signal input end of the IQ modulator; the output end of the second DDS is connected with the input end of a second filter; the output end of the second filter is connected with the Q-path signal input end of the IQ modulator; and the output end of the IQ modulator is connected with the radio frequency input end of the phase locked loop circuit.

Description

A kind of broadband high-speed Frequency Hopping Synthesizer and method of work thereof

Technical field

The present invention relates to radio communication equipment technical field, particularly relate to a kind of broadband high-speed Frequency Hopping Synthesizer and method of work thereof.

Background technology

The output frequency of broadband high-speed Frequency Hopping Synthesizer generally can reach hundreds of MHz to several GHz, and frequency switching time is within 100 μ s.

In order to realize 100 μ s frequency switching times, phase demodulation frequency will reach a few MHz or tens MHz, but output frequency interval is generally at 25kHz, for the contradiction of the phase demodulation frequency and 25kHz output frequency interval that solve a few MHz or tens MHz, the general technical method adopted has monocycle fractional frequency division, DDS (Direct Digital Synthesizer at present, DirectDigitalSynthesizer) single phase-locked loop or DDS interpolation phase-locked loop is driven, the method also having many rings mixing chain comparatively early.

Monocycle fractional frequency division circuit is simple, the available phase-locked loop chip with fractional frequency division a lot (as ADF4153, ADF4157, LM2485 etc.), apply more in the less demanding occasion of Frequency spectrum quality (as mobile phone etc.), because fractional frequency division exists residual modulation, especially when divide ratio (MOD) is larger, when the figure place of fractional frequency division is more, spuious distribution and abundant, limits monocycle fractional frequency division in the applications higher to Frequency spectrum quality requirement such as broadband radio.

It is more rich spuious that DDS drives the method for single phase-locked loop can produce equally, and simultaneously because the ground noise index of DDS device is not high, the noise that DDS can export by this frequency multiplication ring is delivered to local oscillator with the multiple of 20logN and exports, and causes local oscillator near-end noise to worsen.

DDS interpolation phase-locked loop can produce more rich spuious equally.The method of many rings mixing chain needs fractional frequency division equally, realize the frequency switching time of 100 μ s, and each loop will realize the frequency switching time of 100 μ s in principle, simultaneously due to complex circuit, applies less.

Summary of the invention

For the problems referred to above, the object of the present invention is to provide a kind of broadband high-speed Frequency Hopping Synthesizer and method of work thereof, the frequency switching time of 100 μ s can either be realized, inhibit again that fractional frequency division and DDS's is spuious, simultaneously owing to adopting hybrid, phase noise does not also worsen.

For achieving the above object, embodiments of the invention adopt following technical scheme to be achieved.

Technical scheme one:

A kind of broadband high-speed Frequency Hopping Synthesizer, described frequency synthesizer comprises: the first oscillator, phase-locked loop circuit, active loop filter, voltage controlled oscillator, the first Direct Digital Synthesizer, the first filter, the second Direct Digital Synthesizer, the second filter and I/Q modulator, wherein, the signal that described voltage controlled oscillator exports is the local oscillation frequency signal that described frequency synthesizer exports; Phase-locked loop circuit has rf inputs, output, reference frequency input;

The output of described first oscillator is connected with the input of the reference frequency input of described phase-locked loop circuit, described first Direct Digital Synthesizer, the input of described second Direct Digital Synthesizer respectively;

The output of described phase-locked loop circuit is connected with the input of described active loop filter, the output of described active loop filter is connected with the input of described voltage controlled oscillator, and the output of described voltage controlled oscillator is connected with the local frequency input of described I/Q modulator;

The output of described first Direct Digital Synthesizer is connected with the input of described first filter, and the output of described first filter is connected with the I road signal input part of described I/Q modulator;

The output of described second Direct Digital Synthesizer is connected with the input of described second filter, and the output of described second filter is connected with the Q road signal input part of described I/Q modulator;

The output of described I/Q modulator is connected with the rf inputs of described phase-locked loop circuit.

The feature of technical solution of the present invention one and being further improved to:

(1) the Serial Control clock output signal of described first Direct Digital Synthesizer is as the clock input signal of described second Direct Digital Synthesizer;

Described first oscillator, for generation of reference frequency signal;

Described first Direct Digital Synthesizer, for producing first frequency signal according to described reference frequency signal, described second Direct Digital Synthesizer, for producing second frequency signal according to described reference frequency signal, the phase difference of described first frequency signal and described second frequency signal is 90 degree;

Described first filter, for carrying out filtering to described first frequency signal, obtains the I road input signal inputting described I/Q modulator; Described second filter, for carrying out filtering to described second frequency signal, obtains the Q road input signal inputting described I/Q modulator;

Described voltage controlled oscillator, for exporting local oscillation frequency signal;

Described I/Q modulator, for according to described I road input signal, described Q road input signal and described local oscillation frequency signal, produces the radio-frequency input signals of the described phase-locked loop circuit of input;

Described phase-locked loop circuit, for according to described reference frequency signal and described radio-frequency input signals, carries out fractional frequency division to described radio-frequency input signals, and exports the control voltage producing local oscillation signal;

Described active loop filter, carries out filtering and amplification for the control voltage exported described phase-locked loop circuit, thus controls described voltage controlled oscillator output local oscillation frequency signal.

(2) described first oscillator is compensation crystal oscillator.

(3) described phase-locked loop circuit adopts monocycle fractional frequency division to realize.

Technical scheme two:

A method of work for broadband high-speed Frequency Hopping Synthesizer, described method of work is applied to the frequency synthesizer as described in technical scheme one, and described method of work comprises:

First oscillator produces reference frequency signal;

First Direct Digital Synthesizer produces first frequency signal according to described reference frequency signal, second direct digital signal synthesizing device produces second frequency signal according to described reference frequency signal, wherein, the Serial Control clock output signal of described first Direct Digital Synthesizer is as the clock input signal of described second Direct Digital Synthesizer, and the phase difference of described first frequency signal and described second frequency signal is 90 degree;

The I road input signal that filtering obtains I/Q modulator is carried out to described first frequency signal, the Q road input signal that filtering obtains described I/Q modulator is carried out to described second frequency signal;

Obtain the local oscillation frequency signal that voltage controlled oscillator exports, according to described local oscillation frequency signal, described I road input signal and described Q road input signal, produce the radio-frequency input signals of input phase-locked loop circuit;

Described phase-locked loop circuit, according to described reference frequency signal and described radio-frequency input signals, carries out fractional frequency division to described radio-frequency input signals, and exports the control voltage producing local oscillation signal;

Filtering and amplification are carried out to described control voltage, controls voltage controlled oscillator according to filtering and the control voltage after amplifying and export local oscillation frequency signal.

Monocycle fractional frequency division, hybrid, DDS and I/Q modulator combine by the present invention, have both achieved the frequency switching time of 100 μ s, inhibit again that fractional frequency division and DDS's is spuious, and simultaneously owing to adopting hybrid, phase noise does not worsen; And the present invention has general applicability, can be applicable to any band Frequency Synthesizers, circuit is simple, and integrated level is high, is easy to debugging; Frequency switching time is short, phase noise and spuious index high.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 provides a kind of structural representation of broadband high-speed Frequency Hopping Synthesizer for the embodiment of the present invention;

Fig. 2 is the schematic flow sheet that the embodiment of the present invention additionally provides a kind of method of work of broadband high-speed Frequency Hopping Synthesizer;

The output of the employing DDS that Fig. 3 provides for the embodiment of the present invention and local oscillator export the hybrid structural representation by the mixing of I/Q modulator phase.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

The embodiment of the present invention provides a kind of broadband high-speed Frequency Hopping Synthesizer, as shown in Figure 1, described frequency synthesizer comprises: the first oscillator 1, phase-locked loop circuit 2, active loop filter 3, voltage controlled oscillator 4, first Direct Digital Synthesizer 5, first filter 6, second Direct Digital Synthesizer 7, second filter 8 and I/Q modulator 9.

Wherein, the signal that described voltage controlled oscillator 4 exports is the local oscillation frequency signal that described frequency synthesizer exports.Phase-locked loop circuit has rf inputs, output, reference frequency input.

The output of described first oscillator 1 is connected with the input of the reference frequency input of described phase-locked loop circuit 2, described first Direct Digital Synthesizer 5, the input of described second Direct Digital Synthesizer 7 respectively.

The output of described phase-locked loop circuit 2 is connected with the input of described active loop filter 3, the output of described active loop filter 3 is connected with the input of described voltage controlled oscillator 4, and the output of described voltage controlled oscillator 4 is connected with the local frequency input of described I/Q modulator 9.

The output of described first Direct Digital Synthesizer 5 is connected with the input of described first filter 6, and the output of described first filter 6 is connected with the I road signal input part of described I/Q modulator 9.

The output of described second Direct Digital Synthesizer 7 is connected with the input of described second filter 8, and the output of described second filter 8 is connected with the Q road signal input part of described I/Q modulator 9.

The output of described I/Q modulator 9 is connected with the rf inputs of described phase-locked loop circuit 2.

The Serial Control clock output signal of described first Direct Digital Synthesizer 5 is as the clock input signal of described second Direct Digital Synthesizer 7.

Described first oscillator 1, for generation of reference frequency signal.

Described first Direct Digital Synthesizer 5, for producing first frequency signal according to described reference frequency signal, described second Direct Digital Synthesizer 7, for producing second frequency signal according to described reference frequency signal, the phase difference of described first frequency signal and described second frequency signal is 90 degree.

Described first filter 6, for carrying out filtering to described first frequency signal, obtains the I road input signal inputting described I/Q modulator 9; Described second filter 8, for carrying out filtering to described second frequency signal, obtains the Q road input signal inputting described I/Q modulator 9.

Described voltage controlled oscillator 4, for exporting local oscillation frequency signal.

Described I/Q modulator 9, for according to described I road input signal, described Q road input signal and described local oscillation frequency signal, produces the radio-frequency input signals of the described phase-locked loop circuit 2 of input.

Described phase-locked loop circuit 2, for according to described reference frequency signal and described radio-frequency input signals, carries out fractional frequency division to described radio-frequency input signals, and exports the control voltage producing local oscillation signal.

Described active loop filter 3, carries out filtering and amplification for the control voltage exported described phase-locked loop circuit, thus controls described voltage controlled oscillator output local oscillation frequency signal.

Described first oscillator is compensation crystal oscillator.

Described phase-locked loop circuit adopts monocycle fractional frequency division to realize.

Monocycle fractional frequency division, hybrid, DDS and I/Q modulator combine by the present invention, have both achieved the frequency switching time of 100 μ s, inhibit again that fractional frequency division and DDS's is spuious, and simultaneously owing to adopting hybrid, phase noise does not worsen; And the present invention has general applicability, can be applicable to any band Frequency Synthesizers, circuit is simple, and integrated level is high, is easy to debugging; Frequency switching time is short, phase noise and spuious index high.

The embodiment of the present invention additionally provides a kind of method of work of broadband high-speed Frequency Hopping Synthesizer, and described method of work is applied to the frequency synthesizer described in above-described embodiment, and as shown in Figure 2, described method of work comprises:

Step 1, the first oscillator produces reference frequency signal.

Step 2, the first Direct Digital Synthesizer produces first frequency signal according to described reference frequency signal, and the second direct digital signal synthesizing device produces second frequency signal according to described reference frequency signal.

Wherein, the Serial Control clock output signal of described first Direct Digital Synthesizer is as the clock input signal of described second Direct Digital Synthesizer, and the phase difference of described first frequency signal and described second frequency signal is 90 degree.

Step 3, carries out to described first frequency signal the I road input signal that filtering obtains I/Q modulator, carries out to described second frequency signal the Q road input signal that filtering obtains described I/Q modulator.

Step 4, obtains the local oscillation frequency signal that voltage controlled oscillator exports, and according to described local oscillation frequency signal, described I road input signal and described Q road input signal, produces the radio-frequency input signals of input phase-locked loop circuit.

Step 5, described phase-locked loop circuit, according to described reference frequency signal and described radio-frequency input signals, carries out fractional frequency division to described radio-frequency input signals, and exports the control voltage producing local oscillation signal.

Step 6, carries out filtering and amplification to described control voltage, controls voltage controlled oscillator export local oscillation frequency signal according to filtering and the control voltage after amplifying.

A kind of broadband high-speed Frequency Hopping Synthesizer that the embodiment of the present invention provides, pass through fractional frequency division, the integrated application of DDS and IQ modulation, under guarantee 25kHz frequency interval prerequisite, phase demodulation frequency is risen to more than 20MHz, meet the demand of high-speed frequency-hopping, adopt the fractional frequency division of two, spuious the falling of the residual modulation of fractional frequency division is made to depart from beyond dominant frequency spectrum 1MHz, well by loop filter filtering, reduce the frequency range that DDS exports simultaneously, fractional frequency division realizes the many frequency intervals of 1MHz, frequency interval is reduced to 25kHz by DDS further, DDS is exported and is subtracted each other by I/Q modulator and local frequency, inside insert in phase-locked loop, local oscillator output spectrum is not affected by DDS output spectrum substantially, and the frequency synthesizer that the embodiment of the present invention provides is applicable to the frequency synthesizer of any frequency range.

Exemplary, when Practical Project realizes, phase-locked loop circuit part can adopt on a large scale with the integrated phase lock chip (for ADF4157) of fractional frequency division, because the MOD of the integrated phase lock chip of fractional frequency division can be very large, so under the phase demodulation frequency (i.e. reference frequency) of more than 20MHz, the frequency interval of 25kHz can be realized.

Concrete, the frequency computation part according to monocycle fractional frequency division: MOD represents divide ratio, f _rrepresent reference frequency (also known as phase demodulation frequency), N represents the value of integral frequency divisioil, and F represents the value of fractional frequency division).

MOD=f _r÷ 25kHz; Work as f _rduring=19.2MHz, MOD=19200 ÷ 25=768, the frequency of local oscillator output signal, i.e. local oscillator output frequency f ₀=19.2 (N+F ÷ MOD) MHz.

In embodiments of the present invention, the spuious recently position f departing from dominant frequency spectrum of fractional frequency division residual modulation is: f=(19.2 × F ÷ MOD) MHz and f=(19.2-19.2 × F ÷ MOD) MHz place, as F=1,2,3,4,5 ... 763,764,765,766,767 time, f=25kHz, 50kHz, 75kHz, 100kHz, 125kHz ... 125kHz, 100kHz, 75kHz, 50kHz, 25kHz.

As f>1MHz, first MOD by the spuious filtering of fractional frequency division residual modulation, therefore can be taken as double figures (for MOD=16) by active loop filter, now:

The frequency f of local oscillator output signal ₀=19.2 (N+F ÷ 16) MHz, the fractional frequency division namely in phase-locked loop circuit only achieves the frequency interval of 1.2MHz, and the frequency interval of below 1.2MHz is realized by DDS.

The embodiment of the present invention adopts the output of DDS and local oscillator to export and realizes hybrid by the way of I/Q modulator phase mixing, as shown in Figure 3, in the phase-locked loop reflect DDS output frequency.

Two DDS, by Synchronization Control, obtain sin2 π f _dDSt and signal, local oscillator output signal splits into sin (2 π f by I/Q modulator ₀t) with-cos (2 π f ₀t), 4 signals by exporting after multiplier and adder are in I/Q modulator:

$\begin{array}{c}\sin \left(2{\mathrm{\πf}}_{0}t\right)\×\sin (2{\mathrm{\πf}}_{DDS}t+\frac{\mathrm{\π}}{2})-\sin 2{\mathrm{\πf}}_{DDS}t\×\cos \left(2{\mathrm{\πf}}_{0}t\right)\\ =\sin 2\mathrm{\π}(f_O-f_{DDS})t\end{array}$

Further, phase demodulation frequency (i.e. reference frequency), for 19.2MHz, adopts the fractional frequency division of, when namely the frequency interval of phase-locked loop circuit part is Δ f=1.2MHz, and MOD=16.

f ₀＝N.F×19.2+f _DDS

f _DDS＝(f ₀÷Δf-INT(f ₀÷Δf))×Δf+f _a

As (f ₀÷ 1.2-INT (f ₀÷ 1.2)) × 1.2>=0.6 time, get f _a=2.4 (Δ f=1.2)

As (f ₀÷ 1.2-INT (f ₀÷ 1.2)) × 1.2 < 0.6 time, get f _a=3.6

F _dDSafter determining, N=INT ((f ₀-f _dDS) ÷ 19.2),

F＝((f ₀-f _DDS)÷19.2-INT((f ₀-f _DDS)÷19.2))×16

Namely N is (f ₀-f _dDS) integer part of ÷ 19.2, F is (f ₀-f _dDS) fractional part of ÷ 19.2.

F _dDS, after N and F determine, according to phase-locked loop circuit and data format corresponding to DDS, phase-locked loop circuit and DDS are controlled, export corresponding frequency.

Below do not consider that DDS exports spuious, the spuious position that DDS exports and clock CLK, DDS output frequency f _dDSthere is following relation:

When $|\left(\frac{CLK}{f_{DDS}}\right)-INT\left(\frac{CLK}{f_{DDS}}\right)|<0.06$ Or $|\left(\frac{CLK}{f_{DDS}}\right)-INT\left(\frac{CLK}{f_{DDS}}\right)|>0.94$ Time

Spuious comparatively horn of plenty, spuious position of departing from dominant frequency spectrum exists: integral multiple on, now change MOD, as MOD=7, recalculate f as follows _dDS, phase demodulation frequency is for 19.2MHz, and adopt the fractional frequency division of, namely the frequency interval of phase-locked loop circuit part is during MHz, MOD=7.

f ₀＝N.F×19.2+f _DDS

$f_{DDS}=(f_0\&divide;(\frac{19.2}{7})-INT(f_0\&divide;\left(\frac{19.2}{7}\right)\left)\right)\&times;\frac{19.2}{7}+f_a$

When $(f_0\&divide;(\frac{19.2}{7})-INT(f_0\&divide;\left(\frac{19.2}{7}\right)\left)\right)\&times;\frac{19.2}{7}\&GreaterEqual;\frac{19.2}{14}$ Time, get f _a=0

When $(f_0\&divide;(\frac{19.2}{7})-INT(f_0\&divide;\left(\frac{19.2}{7}\right)\left)\right)\&times;\frac{19.2}{7}<\frac{19.2}{14}$ Time, get $f_a=\frac{19.2}{7}$

F _dDSafter determining, N=INT ((f ₀-f _dDS) ÷ 19.2)

F＝((f ₀-f _DDS)÷19.2-INT((f ₀-f _DDS)÷19.2))×5

Namely N is (f ₀-f _dDS) integer part of ÷ 19.2, F is (f ₀-f _dDS) fractional part of ÷ 19.2.

F _dDS, after N and F determine, according to phase-locked loop circuit and data format corresponding to DDS, phase-locked loop circuit and DDS are controlled, export corresponding frequency.

If the f calculated during M=7 _dDSalso meet:

$|\left(\frac{CLK}{f_{DDS}}\right)-INT\left(\frac{CLK}{f_{DDS}}\right)|<0.06$ Or $|\left(\frac{CLK}{f_{DDS}}\right)-INT\left(\frac{CLK}{f_{DDS}}\right)|>0.94$

Now change MOD again, MOD=5, phase demodulation frequency is for 19.2MHz, and adopt the fractional frequency division of, namely the frequency interval of phase-locked loop circuit part is during MHz, recalculate f as follows _dDS.

f ₀＝N.F×19.2+f _DDS

f _DDS＝(f ₀÷3.84-INT(f ₀÷3.84))×3.84+f _a

As (f ₀÷ 1.2-INT (f ₀÷ 1.2)) × 1.2>=1.92 time, get f _a=0

As (f ₀÷ 1.2-INT (f ₀÷ 1.2)) × 1.2 < 1.92 time, get f _a=3.84

F _dDSafter determining, N=INT ((f ₀-f _dDS) ÷ 19.2),

F＝((f ₀-f _DDS)÷19.2-INT((f ₀-f _DDS)÷19.2))×5

Namely N is (f ₀-f _dDS) integer part of ÷ 19.2, F is (f ₀-f _dDS) fractional part of ÷ 19.2.

F _dDS, after N and F determine, according to phase-locked loop and data format corresponding to DDS, phase-locked loop and DDS are controlled, export corresponding frequency.

The spuious of DDS is essentially eliminated by above method.If it is spuious also to there is indivedual point, can also get MOD and 9 or 11 etc. continue to optimize, the principle choosing MOD does not exceed 20, and the MOD value at every turn chosen does not exist common divisor.

In the embodiment of the present invention, the figure place of monocycle fractional frequency division is less, MOD is less than 20, ensure that the spuious distribution of fractional frequency division is far away, can by phase-locked loop filtering, reduce DDS output frequency bandwidth simultaneously, also IQ modulation is conducive to, DDS effect is supplementary fractional frequency division, realizes 25kHz frequency interval, and the effect of I/Q modulator is subtracted each other DDS output frequency and local frequency, balance out mantissa, I/Q modulator is exported to be divided exactly by the phase-locked loop with less figure place fractional frequency division, simultaneously because I/Q modulator is applied to hybrid, DDS exports the impact of local oscillator output noise very little.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.

Claims (5)

1. a broadband high-speed Frequency Hopping Synthesizer, it is characterized in that, described frequency synthesizer comprises: the first oscillator, phase-locked loop circuit, active loop filter, voltage controlled oscillator, the first Direct Digital Synthesizer, the first filter, the second Direct Digital Synthesizer, the second filter and I/Q modulator, wherein, the signal that described voltage controlled oscillator exports is the local oscillation frequency signal that described frequency synthesizer exports; Phase-locked loop circuit has rf inputs, reference frequency input, output;

The output of described first oscillator is connected with the input of the reference frequency input of described phase-locked loop circuit, described first Direct Digital Synthesizer, the input of described second Direct Digital Synthesizer respectively;

The output of described phase-locked loop circuit is connected with the input of described active loop filter, the output of described active loop filter is connected with the input of described voltage controlled oscillator, and the output of described voltage controlled oscillator is connected with the local frequency input of described I/Q modulator;

The output of described first Direct Digital Synthesizer is connected with the input of described first filter, and the output of described first filter is connected with the I road signal input part of described I/Q modulator;

The output of described second Direct Digital Synthesizer is connected with the input of described second filter, and the output of described second filter is connected with the Q road signal input part of described I/Q modulator;

The output of described I/Q modulator is connected with the rf inputs of described phase-locked loop circuit.

2. a kind of broadband high-speed Frequency Hopping Synthesizer according to claim 1, is characterized in that, the Serial Control clock output signal of described first Direct Digital Synthesizer is as the clock input signal of described second Direct Digital Synthesizer;

Described first oscillator, for generation of reference frequency signal;

Described first Direct Digital Synthesizer, for producing first frequency signal according to described reference frequency signal, described second Direct Digital Synthesizer, for producing second frequency signal according to described reference frequency signal, the phase difference of described first frequency signal and described second frequency signal is 90 degree;

Described first filter, for carrying out filtering to described first frequency signal, obtains the I road input signal inputting described I/Q modulator; Described second filter, for carrying out filtering to described second frequency signal, obtains the Q road input signal inputting described I/Q modulator;

Described voltage controlled oscillator, for exporting local oscillation frequency signal;

Described I/Q modulator, for according to described I road input signal, described Q road input signal and described local oscillation frequency signal, produces the radio-frequency input signals of the described phase-locked loop circuit of input;

Described phase-locked loop circuit, for according to described reference frequency signal and described radio-frequency input signals, carries out fractional frequency division to described radio-frequency input signals, and exports the control voltage producing local oscillation signal;

Described active loop filter, carries out filtering and amplification for the control voltage exported described phase-locked loop circuit, thus controls described voltage controlled oscillator output local oscillation frequency signal.

3. a kind of broadband high-speed Frequency Hopping Synthesizer according to claim 1, is characterized in that, described first oscillator is compensation crystal oscillator.

4. a kind of broadband high-speed Frequency Hopping Synthesizer according to claim 1, is characterized in that, described phase-locked loop circuit adopts monocycle fractional frequency division to realize.

5. a method of work for broadband high-speed Frequency Hopping Synthesizer, is characterized in that, described method of work is applied to frequency synthesizer as claimed in claim 1, and described method of work comprises:

First oscillator produces reference frequency signal;

First Direct Digital Synthesizer produces first frequency signal according to described reference frequency signal, second direct digital signal synthesizing device produces second frequency signal according to described reference frequency signal, wherein, the Serial Control clock output signal of described first Direct Digital Synthesizer is as the clock input signal of described second Direct Digital Synthesizer, and the phase difference of described first frequency signal and described second frequency signal is 90 degree;

The I road input signal that filtering obtains I/Q modulator is carried out to described first frequency signal, the Q road input signal that filtering obtains described I/Q modulator is carried out to described second frequency signal;

Obtain the local oscillation frequency signal that voltage controlled oscillator exports, according to described local oscillation frequency signal, described I road input signal and described Q road input signal, produce the radio-frequency input signals of input phase-locked loop circuit;

Described phase-locked loop circuit, according to described reference frequency signal and described radio-frequency input signals, carries out fractional frequency division to described radio-frequency input signals, and exports the control voltage producing local oscillation signal;

Filtering and amplification are carried out to described control voltage, controls voltage controlled oscillator according to filtering and the control voltage after amplifying and export local oscillation frequency signal.