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CN105355610A - Circuit device and manufacturing method - Google Patents

Circuit device and manufacturing method Download PDF

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Publication number
CN105355610A
CN105355610A CN201510535388.XA CN201510535388A CN105355610A CN 105355610 A CN105355610 A CN 105355610A CN 201510535388 A CN201510535388 A CN 201510535388A CN 105355610 A CN105355610 A CN 105355610A
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China
Prior art keywords
layer
metal particle
nano
alloy
sintering
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Granted
Application number
CN201510535388.XA
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Chinese (zh)
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CN105355610B (en
Inventor
符会利
林志荣
蔡树杰
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201510535388.XA priority Critical patent/CN105355610B/en
Publication of CN105355610A publication Critical patent/CN105355610A/en
Priority to EP16838559.9A priority patent/EP3327769B1/en
Priority to SG11201801027SA priority patent/SG11201801027SA/en
Priority to PCT/CN2016/096373 priority patent/WO2017032301A1/en
Priority to TW105127108A priority patent/TWI644367B/en
Priority to US15/905,044 priority patent/US10784181B2/en
Application granted granted Critical
Publication of CN105355610B publication Critical patent/CN105355610B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Powder Metallurgy (AREA)

Abstract

The invention provides a device, which comprises a circuit device, a cooling fin and a thermal interface material layer, wherein the thermal interface material layer is thermally coupled to the circuit device and the cooling fin; the thermal interface material layer comprises a first alloy layer, a nanometal particle layer and a second alloy layer; the first alloy layer is thermally coupled to the circuit device; the nanometal particle layer is thermally coupled to the first alloy layer; and the nanometal particle layer comprises nanometal particles and an intermediate mixture.

Description

A kind of circuit arrangement and manufacture method
Technical field
The present invention relates to circuit field, particularly relate to a kind of circuit arrangement and manufacture method.
Background technology
Figure 1A is depicted as the cross section exemplary plot of integrated circuit (IC) chip and partial encapsulation structure thereof in prior art.This structure comprises integrated circuit (IC) chip 1A02, thermal interface material layer 1A04 and radiator 1A06.The heat that integrated circuit (IC) chip 1A02 produces in the course of work pours radiator 1A06 into by the thermal interface material layer 1A04 of chip back, and thus, the capacity of heat transmission of thermal interface material layer 1A04 itself has material impact to chip cooling.Existing thermal interface material layer comprises elargol class material.In elargol class material, hybrid metal Argent grain 1A08 is to improve heat-conducting effect, but continuous phase that is main or that formed based on elargol class material.Elargol class material conducts heat rate is lower, has been difficult to the radiating requirements meeting high-power chip.
Summary of the invention
The embodiment of the present invention provides a kind of device and manufacture method.In this device, the thermal interfacial material between circuit devcie and fin has high thermal conductivity, has increased substantially the thermal conductance usefulness of integral thermal via, can meet the radiating requirements of large power digital circuit device better.
First aspect, embodiments provides, a kind of device, comprising: circuit devcie; Fin; And thermal interface material layer, with described circuit devcie and described fin thermal coupling, comprising: the first alloy-layer, with described circuit devcie thermal coupling; Nano-metal particle layer, with described first alloy-layer thermal coupling, described nano-metal particle layer comprises the multiple nano-metal particle and intermediate blend that intercouple, and described intermediate blend is filled between described multiple nano-metal particle; And second alloy-layer, with described nano-metal particle layer and described fin thermal coupling.
In the first possible implementation of first aspect, the contact position of described first alloy-layer and described nano-metal particle layer is formed and sinters continuous phase structure, contact position between described multiple nano-metal particle forms sintering continuous phase structure, and the contact position of described second alloy-layer and described nano-metal particle layer is formed and sinters continuous phase structure.
In conjunction with first aspect, or the first possible implementation of first aspect, in the implementation that the second is possible, described nano-metal particle comprises silver.
In conjunction with first aspect, or any one possible implementation of first aspect the first to the second, in the implementation that the third is possible, the diameter of described nano-metal particle is between 50-200 nanometer.
In conjunction with first aspect, or first aspect first is to the third any one possible implementation, in the 4th kind of possible implementation, for flip chip ball grid lattice array structure.
In conjunction with first aspect, or any one possible implementation of first aspect first to fourth kind, in the 5th kind of possible implementation, first alloy-layer comprises the first following layer and the first co-sintering layer, described first following layer and described circuit devcie thermal coupling, described first co-sintering layer is coupled with described nano-metal particle layer, and the contact position of described first co-sintering layer and described nano-metal particle layer is formed and sinters continuous phase structure.
In conjunction with first aspect the 5th kind of possible implementation, in the 6th kind of possible implementation, described first following layer comprises any one in following material: titanium, chromium, nickel or nickel-vanadium alloy, and described first co-sintering layer comprises any one in following material: silver, gold or copper.
In conjunction with any one the possible implementation in first aspect the 5th kind of possible implementation and the 6th kind of possible implementation, in the 7th kind of possible implementation, described first alloy-layer also comprises the first resilient coating, between described first following layer and described first co-sintering layer, described first resilient coating comprises any one in following material: aluminium, copper, nickel or nickel-vanadium alloy.
In conjunction with first aspect, or first aspect first is to the 7th kind of any one possible implementation, in the 8th kind of possible implementation, described second alloy-layer comprises the second following layer and the second co-sintering layer, described second following layer and described fin thermal coupling, described second co-sintering layer and the thermal coupling of described nano-metal particle layer, and the contact position of described second co-sintering layer and described nano-metal particle layer is formed and sinters continuous phase structure.
In conjunction with first aspect the 8th kind of possible implementation, in the 9th kind of possible implementation, described second following layer comprises any one in following material: titanium, chromium, nickel or nickel-vanadium alloy, and described second co-sintering layer comprises any one in following material: silver, gold or copper.
In conjunction with any one the possible implementation in first aspect the 8th kind of possible implementation and the 9th kind of possible implementation, in the tenth kind of possible implementation, described second alloy-layer also comprises the second resilient coating, between described second following layer and described second co-sintering layer, described second resilient coating comprises any one in following material: aluminium, copper, nickel or nickel-vanadium alloy.
In conjunction with first aspect, or first aspect first is to the tenth kind of any one possible implementation, and in the 11 kind of possible implementation, the diameter of described nano-metal particle is not more than 1 micron.
In conjunction with first aspect, or first aspect first is to the 11 kind of any one possible implementation, and in the 12 kind of possible implementation, described intermediate blend comprises any one in following material: air or resin.
In conjunction with first aspect, or first aspect first is to the 12 kind of any one possible implementation, in the 13 kind of possible implementation, described circuit devcie comprises integrated circuit lead, the substrate in described integrated circuit lead and described thermal interface material layer thermal coupling.
Second aspect, embodiments provides, a kind of method of manufacturing installation, comprising: generate the first alloy-layer; Generate nano-metal particle layer by the multiple nano-metal particle intercoupled and intermediate blend, make described intermediate blend be filled between described multiple nano-metal particle; And generate the second alloy-layer, wherein, make described first alloy-layer and circuit devcie thermal coupling, make described nano-metal particle layer and described first alloy-layer thermal coupling, and make described second alloy-layer and described nano-metal particle layer and fin thermal coupling.
In the first possible implementation of second aspect, the contact position of described first alloy-layer and described nano-metal particle layer is formed and sinters continuous phase structure, make contact position between described nano-metal particle form sintering continuous phase structure, and the contact position of described second alloy-layer and described nano-metal particle layer is formed sinter continuous phase structure.
In conjunction with second aspect, or the first possible implementation of second aspect, in the implementation that the second is possible, the diameter of described nano-metal particle is not more than 1 micron.
In conjunction with second aspect, or any one possible implementation of second aspect the first to the second, in the implementation that the third is possible, described intermediate blend comprises any one in following material: air or resin.
In conjunction with second aspect, or second aspect first is to the third any one possible implementation, in the 4th kind of possible implementation, described generation first alloy-layer comprises: generate the first following layer and the first co-sintering layer, and make described first following layer and described circuit devcie thermal coupling, described first co-sintering layer is coupled with described nano-metal particle layer, and the contact position of described first co-sintering layer and described nano-metal particle layer is formed sinter continuous phase structure.
In conjunction with second aspect, or any one possible implementation of second aspect first to fourth kind, in the 5th kind of possible implementation, described generation second alloy-layer comprises: generate the second following layer and the second co-sintering layer, and make described second following layer and described fin thermal coupling, make described second co-sintering layer and the thermal coupling of described nano-metal particle layer, and the contact position of described second co-sintering layer and described nano-metal particle layer is formed sinter continuous phase structure.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Figure 1A is the cross section exemplary plot that prior art comprises the encapsulating structure of device.
Fig. 1 is the cross section exemplary plot comprising the encapsulating structure of device of first embodiment of the invention.
Fig. 2 comprises the cross section exemplary plot of the first embodiment of the thermal interface material layer in Fig. 1.
Fig. 3 is the cross section exemplary plot of the first embodiment of the first alloy-layer in Fig. 2.
Fig. 4 is the cross section exemplary plot of the second embodiment of the first alloy-layer in Fig. 2.
Fig. 5 is the cross section exemplary plot of the first embodiment of the second alloy-layer in Fig. 2.
Fig. 6 is the cross section exemplary plot of the second embodiment of the second alloy-layer in Fig. 2.
Fig. 7 is the flow chart of the method for a kind of manufacturing installation of second embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the cross section exemplary plot of the encapsulating structure 100 comprising device of first embodiment of the invention.This flip chip ball grid lattice array encapsulation structure comprises soldered ball 108, substrate 107, bonded adhesives 106, metal coupling (BUMP) 102, circuit devcie (as integrated circuit lead) 103, thermal interface material layer 104 and fin 105.Integrated circuit lead 103 is coupled with substrate 107 by metal coupling 102.Metal coupling 102 is protected by bottom filler 101.Fin 105 is fixed on substrate 107 by bonded adhesives 106.Thermal interface material layer 104 and integrated circuit lead 103 and fin 105 thermal coupling.Herein, thermal coupling comprises different levels, different structure, or has heat conducting situation between different device.In more detail, thermal interface material layer 104 can between integrated circuit lead 103 and fin 105.Substrate in integrated circuit lead 103 and thermal interface material layer 104 thermal coupling.The heat of integrated circuit lead 103 reaches fin 105 by thermal interface material layer 104.
Wherein, integrated circuit lead 103, thermal interface material layer 104 and fin 105 can be used as a kind of part or all of assembly of device, and this device can be used for but is not limited to flip chip ball grid lattice array encapsulation structure as shown in the figure.
Fig. 2 comprises the cross section exemplary plot of the first embodiment of the thermal interface material layer 104 in Fig. 1.Thermal interface material layer 104 and tube core 103 and fin 105 thermal coupling, comprise the first alloy-layer 109, nano-metal particle layer 110 and the second alloy-layer 112.
First alloy-layer 109 and integrated circuit lead 103 and nano-metal particle layer 110 thermal coupling.More specifically, as shown in the figure, the first alloy-layer 109 can be positioned on integrated circuit lead 103, under nano-metal particle layer 110.That is, the first alloy-layer 109 can between integrated circuit lead 103 and nano-metal particle layer 110.First alloy-layer 109 increases the Bonding strength between integrated circuit lead 103 and nano-metal particle layer 110.
Nano-metal particle layer 110 comprises nano-metal particle and intermediate blend.Intermediate blend includes but not limited to any one in following material: air or resin.Intermediate blend is used for being filled between multiple nano-metal particle, makes multiple nano-metal particle form entirety.Nano-metal particle includes but not limited to silver.The diameter of nano-metal particle is not more than 1 micron.In one embodiment, the diameter of nano-metal particle is between 50-200 nanometer.Nano-metal particle layer 110 thermal resistance is lower, forms good thermal conducting path.
Second alloy-layer 112 and nano-metal particle layer 110 and fin 105 thermal coupling.More specifically, as shown in the figure, the second alloy-layer 112 can be positioned on nano-metal particle layer 110, under fin 105.That is, the second alloy-layer 112 can between nano-metal particle layer 110 and fin 105.Second alloy-layer 112 increases the Bonding strength between nano-metal particle layer 110 and fin 105.
In one embodiment, first alloy-layer 109 is formed with the contact position of nano-metal particle layer 110 and sinters continuous phase structure, contact position between nano-metal particle forms sintering continuous phase structure, and the second alloy-layer 112 is formed with the contact position of nano-metal particle layer 110 and sinters continuous phase structure.Sintering continuous phase structure herein includes but not limited to: because metallic particles produces sintering behavior, the metallic atom near metallic particles interface diffuses to metallic particles interface fusion together, makes metallic particles form an overall structure.
Fig. 3 is the cross section exemplary plot of the first embodiment of the first alloy-layer 109 in Fig. 2.As shown in the figure, the first alloy-layer 109 comprises the first following layer 114 and the first co-sintering layer 115.Co-sintering layer herein includes but not limited to: the metal level melted mutually with thermal interface material layer produced in encapsulation process process, and the particle in this metal level and thermal interface material layer sinters formation heat flow path jointly.First following layer 114 and integrated circuit lead 103 thermal coupling.First co-sintering layer 115 and nano-metal particle layer 110 thermal coupling.First co-sintering layer 115 is formed with the contact position of nano-metal particle layer 110 and sinters continuous phase structure.Particularly, the first following layer 114 can be positioned on integrated circuit lead 103, and the first co-sintering layer 115 can be positioned on the first following layer 114, under nano-metal particle layer 110.First following layer 114 includes but not limited to any one in following material: titanium, chromium, nickel or nickel/vanadium.First following layer 114 increases the bond strength between integrated circuit lead 103 and the first co-sintering layer 115.First co-sintering layer 115 includes but not limited to any one in following material: silver, gold or copper.
Fig. 4 is the cross section exemplary plot of the second embodiment of the first alloy-layer 109 in Fig. 2.Compared with Fig. 3, the first alloy-layer 109 in Fig. 4 also comprises the first resilient coating 116, between described first following layer 114 and the first co-sintering layer 115.First resilient coating 116 includes but not limited to any one in following material: aluminium, copper or nickel.First resilient coating 116 provides stress buffer function in the deformation produced because of heat treatment, reduces the risk producing crack between integrated circuit lead 103 and thermal interface material layer 114 or in the middle of thermal interface material layer 114, increases the reliability of this device.
Fig. 5 is the cross section exemplary plot of the first embodiment of the second alloy-layer 112 in Fig. 2.As shown in the figure, the second alloy-layer 112 comprises the second co-sintering layer 118 and the second following layer 117.Second co-sintering layer 118 and nano-metal particle layer 110 thermal coupling.Second co-sintering layer 118 is formed with the contact position of nano-metal particle layer 110 and sinters continuous phase structure.Second following layer 117 and fin 105 thermal coupling.Particularly, the second co-sintering layer 118 can be positioned on nano-metal particle layer 110, and the second following layer 117 can be positioned on the second co-sintering layer 118, under fin 105.Second co-sintering layer 118 includes but not limited to any one in following material: silver, gold or copper.Second following layer 117 includes but not limited to any one in following material: titanium, chromium, nickel or nickel/vanadium.Second following layer 117 increases the bond strength between the second co-sintering layer 115 and fin 105.
Fig. 6 is the cross section exemplary plot of the second embodiment of the second alloy-layer 112 in Fig. 2.Compared with Fig. 5, the second alloy-layer 112 in Fig. 6 also comprises the second resilient coating 119, between the second following layer 117 and the second co-sintering layer 118.Second resilient coating 119 includes but not limited to any one in following material: aluminium, copper, nickel or nickel/vanadium.Second resilient coating 119 provides pooling feature in the deformation produced because of heat treatment, reduces the risk producing crack between thermal interface material layer and fin 105 or in the middle of thermal interface material layer 114, increases the reliability of this device.
To sum up, owing to no longer comprising the lower thermal conducting material of high score subclass in elargol class material in the thermal interface material layer in the embodiment of the present invention, but comprise nano-metal particle, thermal interfacial material in the embodiment of the present invention has high thermal conductivity, increase substantially the thermal conductance usefulness of integral thermal via, the radiating requirements of large power dissipating chip can have been met better.
Fig. 7 is the flow chart 700 of the method for a kind of manufacturing installation of second embodiment of the invention.As shown in the figure, in a step 702, the first alloy-layer is generated.In step 704, nano-metal particle layer is generated by nano-metal particle and intermediate blend.The diameter of nano-metal particle is not more than 1 micron, and such as, the diameter of nano-metal particle is between 50-200 nanometer.Intermediate blend includes but not limited to any one in following material: air or resin.In one embodiment, nano-metal particle includes but not limited to silver.In step 706, the second alloy-layer is generated.In step 708, the first alloy-layer and nano-metal particle layer and circuit devcie thermal coupling is made.In step 720, the second alloy-layer and nano-metal particle layer and fin thermal coupling is made.
In one embodiment, the contact position of the first alloy-layer and nano-metal particle layer is formed and sinters continuous phase structure, make contact position between nano-metal particle form sintering continuous phase structure, and the contact position of the second alloy-layer and nano-metal particle layer is formed sinter continuous phase structure.
In one embodiment, the method can be used for but is not limited to flip chip ball grid lattice array structure.
In one embodiment, generate the first alloy-layer and comprise generation first following layer and the first co-sintering layer, and make the first following layer and circuit devcie thermal coupling, first co-sintering layer is coupled with nano-metal particle layer, and the contact position of the first co-sintering layer and nano-metal particle layer is formed sinter continuous phase structure.First following layer includes but not limited to any one in following material: titanium, chromium, nickel or nickel/vanadium.First co-sintering layer includes but not limited to any one in following material: silver, gold or copper.In another embodiment, generate the first alloy-layer to be also included between the first following layer and the first co-sintering layer and to generate the first resilient coating.First resilient coating includes but not limited to any one in following material: aluminium, copper, nickel or nickel/vanadium.
In one embodiment, generate the second alloy-layer and comprise generation second following layer and the second co-sintering layer, and make the second following layer and fin thermal coupling, make the second co-sintering layer and the thermal coupling of nano-metal particle layer, and the contact position of described second co-sintering layer and described nano-metal particle layer is formed sinter continuous phase structure.Second following layer includes but not limited to any one in following material: titanium, chromium, nickel or nickel/vanadium.Second co-sintering layer includes but not limited to any one in following material: silver, gold or copper.In another embodiment, generate the second alloy-layer to be also included between the second following layer and the second co-sintering layer and to generate the second resilient coating.Second resilient coating includes but not limited to any one in following material: aluminium, copper, nickel or nickel/vanadium.
Circuit devcie can comprise integrated circuit lead.The first alloy-layer and circuit devcie thermal coupling is made to comprise the substrate thermal coupling made in the first alloy-layer and integrated circuit lead.
Above disclosedly be only present pre-ferred embodiments, certainly can not limit the interest field of the present invention with this, therefore according to the equivalent variations that the claims in the present invention are done, still belong to the scope that the present invention is contained.

Claims (19)

1. a circuit arrangement, is characterized in that, comprising:
Circuit devcie;
Fin; And
Thermal interface material layer, with described circuit devcie and described fin thermal coupling, comprising:
First alloy-layer, with described circuit devcie thermal coupling;
Nano-metal particle layer, with described first alloy-layer thermal coupling, described nano-metal particle layer comprises the multiple nano-metal particle and intermediate blend that intercouple, and described intermediate blend is filled between described multiple nano-metal particle; And
Second alloy-layer, with described nano-metal particle layer and described fin thermal coupling.
2. circuit arrangement as claimed in claim 1, it is characterized in that, the contact position of described first alloy-layer and described nano-metal particle layer is formed and sinters continuous phase structure, contact position between described multiple nano-metal particle forms sintering continuous phase structure, and the contact position of described second alloy-layer and described nano-metal particle layer is formed and sinters continuous phase structure.
3. circuit arrangement as claimed in claim 1 or 2, it is characterized in that, described multiple nano-metal particle comprises silver.
4. the circuit arrangement according to any one of claim 1-3, is characterized in that, the diameter of described multiple nano-metal particle is between 50-200 nanometer.
5. the circuit arrangement according to any one of claim 1-4, is characterized in that, for flip chip ball grid lattice array structure.
6. the circuit arrangement according to any one of claim 1-5, it is characterized in that, first alloy-layer comprises the first following layer and the first co-sintering layer, described first following layer and described circuit devcie thermal coupling, described first co-sintering layer is coupled with described nano-metal particle layer, and the contact position of described first co-sintering layer and described nano-metal particle layer is formed and sinters continuous phase structure.
7. circuit arrangement as claimed in claim 6, it is characterized in that, described first following layer comprises any one in following material: titanium, chromium, nickel or nickel-vanadium alloy, and described first co-sintering layer comprises any one in following material: silver, gold or copper.
8. circuit arrangement as claimed in claims 6 or 7, it is characterized in that, described first alloy-layer also comprises the first resilient coating, and between described first following layer and described first co-sintering layer, described first resilient coating comprises any one in following material: aluminium, copper, nickel or nickel-vanadium alloy.
9. the circuit arrangement according to any one of claim 1-8, it is characterized in that, described second alloy-layer comprises the second following layer and the second co-sintering layer, described second following layer and described fin thermal coupling, described second co-sintering layer and the thermal coupling of described nano-metal particle layer, and the contact position of described second co-sintering layer and described nano-metal particle layer is formed and sinters continuous phase structure.
10. circuit arrangement as claimed in claim 9, it is characterized in that, described second following layer comprises any one in following material: titanium, chromium, nickel or nickel-vanadium alloy, and described second co-sintering layer comprises any one in following material: silver, gold or copper.
11. circuit arrangements as described in claim 9 or 10, it is characterized in that, described second alloy-layer also comprises the second resilient coating, and between described second following layer and described second co-sintering layer, described second resilient coating comprises any one in following material: aluminium, copper, nickel or nickel-vanadium alloy.
12. as the circuit arrangement as described in arbitrary in claim 1-11, and it is characterized in that, described intermediate blend comprises any one in following material: air or resin.
13. circuit arrangements according to any one of claim 1-12, it is characterized in that, described circuit devcie comprises integrated circuit lead, the substrate in described integrated circuit lead and described thermal interface material layer thermal coupling.
14. 1 kinds of methods manufacturing circuit arrangement, is characterized in that, comprising:
Generate the first alloy-layer;
Generate nano-metal particle layer by the multiple nano-metal particle intercoupled and intermediate blend, make described intermediate blend be filled between described multiple nano-metal particle; And
Generate the second alloy-layer,
Wherein, make described first alloy-layer and circuit devcie thermal coupling, make described nano-metal particle layer and described first alloy-layer thermal coupling, and make described second alloy-layer and described nano-metal particle layer and fin thermal coupling.
15. methods as claimed in claim 14, it is characterized in that, also comprise and the contact position of described first alloy-layer and described nano-metal particle layer is formed sinter continuous phase structure, make contact position between described nano-metal particle form sintering continuous phase structure, and the contact position of described second alloy-layer and described nano-metal particle layer is formed sinter continuous phase structure.
16. methods as described in claims 14 or 15, it is characterized in that, the diameter of described multiple nano-metal particle is not more than 1 micron.
17. as the method as described in arbitrary in claim 14-16, and it is characterized in that, described intermediate blend comprises any one in following material: air or resin.
18. as the method as described in arbitrary in claim 14-17, it is characterized in that, described generation first alloy-layer comprises: generate the first following layer and the first co-sintering layer, and make described first following layer and described circuit devcie thermal coupling, described first co-sintering layer is coupled with described nano-metal particle layer, and the contact position of described first co-sintering layer and described nano-metal particle layer is formed sinter continuous phase structure.
19. as the method as described in arbitrary in claim 14-18, it is characterized in that, described generation second alloy-layer comprises: generate the second following layer and the second co-sintering layer, and make described second following layer and described fin thermal coupling, make described second co-sintering layer and the thermal coupling of described nano-metal particle layer, and the contact position of described second co-sintering layer and described nano-metal particle layer is formed sinter continuous phase structure.
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US10784181B2 (en) 2020-09-22

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