CN105355592B - Array substrate and preparation method thereof - Google Patents
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- CN105355592B CN105355592B CN201510670975.XA CN201510670975A CN105355592B CN 105355592 B CN105355592 B CN 105355592B CN 201510670975 A CN201510670975 A CN 201510670975A CN 105355592 B CN105355592 B CN 105355592B
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- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 238000009413 insulation Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 18
- 230000008021 deposition Effects 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 claims abstract description 11
- 238000002425 crystallisation Methods 0.000 claims abstract description 9
- 230000008025 crystallization Effects 0.000 claims abstract description 9
- -1 phosphonium ion Chemical class 0.000 claims description 9
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 65
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005034 decoration Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of array substrate and preparation method thereof, comprising: buffer layer on the glass substrate；The deposition of amorphous silicon layers on the buffer layer, and crystallization processing and patterned process are carried out to the amorphous silicon layer, to form polysilicon graphics；Conductiving doping is carried out to the polysilicon graphics；Gate electrode and N lightly doped district are formed using gate electrode light shield；Insulation patterns and N heavily doped region are formed using insulating film light shield；Source electrode and drain electrode is prepared above N heavily doped region.Gate electrode and N are lightly doped a shared light shield, insulating film and N heavily doped region are shared a light shield by the present invention, are made simple process, are reduced preparation cost while improving production efficiency.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of array substrate and preparation method thereof.
Background technique
In recent years, low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) technology continues to develop.Using
The liquid crystal display panel of low temperature polysilicon process technology production is conducive to improve panel aperture ratio, promotes display brightness, power consumption drop
It is low, it is suitable for producing more frivolous, low power consumption, high-resolution product.However, low temperature polycrystalline silicon is improving carrier mobility
While, also due to hot carrier's effect and detrimental effect is produced to the performance of device.Specifically, in forceful electric power field action
Under, carrier constantly drifts about along direction of an electric field, constantly accelerates, and then obtain very big kinetic energy and form hot carrier, in small ruler
Hot carrier described in very little device or large scale integrated circuit can generate damage to device performance, and this effect is known as hot carrier
Effect.
In order to solve the influence of hot carrier's effect, the prior art is mainly by avoiding the generation of local strong electrical field.Such as: adopting
With the method for ion implantation, one section of symmetrical lightly doped drain is done between the two sides gate electrode (Gate) n+ ɑ-Si and poly-Si
The structure of (Lightly Doped Drain, LDD).This means that individual mask plate (Mask) design and primary light
(Photo) processing procedure needs to spend a large amount of cost.
Summary of the invention
In view of this, the present invention is intended to provide a kind of array substrate and preparation method thereof, is prepared in the prior art with solution
The problem of complex process, higher cost.
To solve the above problems, technical solution provided by the invention is as follows:
A kind of production method of array substrate, comprising:
(1) buffer layer on the glass substrate；
(2) deposition of amorphous silicon layers on the buffer layer, and crystallization processing and patterning are carried out to the amorphous silicon layer
Processing, to form polysilicon graphics；
(3) conductiving doping is carried out to the polysilicon graphics；
(4) gate insulation layer and gate electrode layer are deposited, with gate electrode light shield to the gate electrode layer carry out patterned process with
Gate electrode is formed, while N is carried out to corresponding polysilicon graphics with the gate electrode light shield and is lightly doped, to form N lightly doped district；
(5) sputter insulating film is etched to form insulation patterns the insulating film with insulating film light shield, while using institute
It states insulating film light shield and N heavy doping is carried out to corresponding polysilicon graphics, to form N heavily doped region；And
(6) source electrode and drain electrode is prepared above the N heavily doped region.
Preferably, N is carried out to corresponding polysilicon graphics with the gate electrode light shield simultaneously in step (4) to be lightly doped, with
N lightly doped district is formed, is specifically included:
Processing is exposed to corresponding polysilicon graphics using the gate electrode light shield, ditch is lightly doped to generate the first N
Road and the 2nd N lightly doped channel；And
It carries out N in the first N lightly doped channel and the 2nd N lightly doped channel to be lightly doped, wherein the N gently mixes
It collects widely with phosphonium ion or arsenic ion.
Preferably, deposition gate insulation layer and gate electrode layer in step (4), carry out the gate electrode layer with gate electrode light shield
Patterned process is specifically included with forming gate electrode:
Deposit gate insulation layer；
The depositing gate electrode layer on the grid electrode insulating layer；And
Processing is patterned using gate electrode light shield to the gate insulation layer and the gate electrode layer, to form gate electrode
Insulation patterns and gate electrode, wherein the grid electrode insulating figure, the gate electrode are opposite with the position of the polysilicon graphics
It answers.
Preferably, insulating film light shield described in step (5) carries out N heavy doping to corresponding polysilicon graphics, to form N weight
Doped region specifically includes:
Processing is exposed to corresponding polysilicon graphics using the insulating film light shield, to generate the first N heavy doping ditch
Road and the 2nd N heavy doping channel；And
N heavy doping is carried out, in the first N heavy doping channel and the 2nd N heavy doping channel to generate the first N weight
Doped region and the 2nd N heavily doped region, wherein the N is lightly doped using phosphonium ion or arsenic ion.
Preferably, the N heavily doped region is formed between the N lightly doped district.
Preferably, sputter insulating film in step (5) is etched the insulating film with insulating film light shield to form insulation
Figure specifically includes:
Sputter insulating film, wherein the dielectric constant of the insulating film material is less than or equal to 3.9；
Photoresist layer is deposited on the insulating film；And
It is etched according to the insulating pattern on insulating film light shield, to form insulation patterns.
Preferably, step (3) carries out conductiving doping to the polysilicon graphics, specifically includes:
P-type ion is selected to carry out conductiving doping to the polysilicon graphics, wherein the P-type ion is boron ion.
Preferably, step (2) deposition of amorphous silicon layers on the buffer layer, and the amorphous silicon layer is carried out at crystallization
Reason and patterned process are specifically included with forming polysilicon graphics:
In 450 DEG C of temperature environments below on the buffer layer deposition of amorphous silicon layers；
Crystallization processing is carried out to the amorphous silicon layer using laser annealing processing, to form polysilicon layer；And
Patterned process is carried out to the polysilicon layer according to preset pattern, to form polysilicon graphics.
Preferably, the step (6) prepares source electrode and drain electrode above the N heavily doped region, before further include:
The first contact hole is formed, and is conducted to the gate electrode；
The step (6) prepares source electrode and drain electrode above the N heavily doped region, later further include:
The depositing insulating layer in the source electrode and drain electrode；
It opens up to form the second contact hole on the source electrode drain electrode insulating layer；And
Pixel deposition electrode, and the pixel electrode is connect by second contact hole with drain electrode.
To solve the above problems, technical solution provided by the invention is as follows:
A kind of array substrate, comprising:
Glass substrate；
Buffer layer is deposited on the glass substrate；
Polysilicon layer, comprising: polysilicon graphics, the side of the polysilicon graphics is successively are as follows: the first N lightly doped district,
One N heavily doped region and the first N lightly doped district, the other side of the polysilicon graphics is successively are as follows: the 2nd N of the 2nd N lightly doped district weight
Doped region and the 2nd N lightly doped district；
Grid electrode insulating layer；
Gate electrode, the gate electrode are corresponding with the polysilicon graphics；
Insulating film, including insulation patterns, the insulation patterns and the first N heavily doped region and the 2nd N heavy doping
Area is corresponding；And
Source electrode and drain electrode is deposited on the insulating film, and is located at the first N heavily doped region and the 2nd N
The top of heavily doped region.
Array substrate provided in an embodiment of the present invention and preparation method thereof, by gate electrode and N be lightly doped a shared light shield,
Insulating film and N heavily doped region are shared into a light shield, reduce the preparation step of low temperature polycrystalline silicon array substrate, to make technique
It is simpler, reduce preparation cost while improving production efficiency.
Detailed description of the invention
For above content of the invention can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's accompanying drawings, makees
Detailed description are as follows:
Fig. 1 is the flow diagram of the production method of the array substrate of the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram that the N-type of the embodiment of the present invention one is lightly doped；
Fig. 3 is the structural schematic diagram of the N-type heavy doping of the embodiment of the present invention one；
Fig. 4 is the structural schematic diagram of the array substrate of the embodiment of the present invention two.
Specific embodiment
Array substrate provided by the invention and preparation method thereof, suitable for semiconductor field magnetron sputtering apparatus design and
Production.Vacuum coating (Physical Vapor Deposition, the PVD) equipment for being particularly applicable to liquid crystal display panel industry is set
Meter, can equally be well applied to the Magnetic Field Design of other magnetron sputtering apparatus such as solar energy.
Embodiment one
Fig. 1 is please referred to, the flow diagram of the production method of the array substrate of the embodiment of the present invention is shown.
The production method of the array substrate, comprising:
In step s101, buffer layer on the glass substrate.
Referring to Fig. 2, such as buffer layer 20 on the glass substrate 10.
In step s 102, the deposition of amorphous silicon layers on the buffer layer, and the amorphous silicon layer is carried out at crystallization
Reason and patterned process, to form polysilicon graphics.
It is understood that the step of formation polysilicon graphics, specifically includes:
(1) in 450 DEG C of temperature environments below on the buffer layer deposition of amorphous silicon layers；
(2) crystallization processing is carried out to the amorphous silicon layer using laser annealing processing, to form polysilicon layer, such as Fig. 2
Polysilicon layer 30；And
(3) patterned process is carried out to the polysilicon layer according to preset pattern, to form polysilicon graphics, such as Fig. 2
Polysilicon graphics 35.
In step s 103, conductiving doping is carried out to the polysilicon graphics.
It is understood that the step of conductiving doping, specifically includes:
P-type ion is selected to carry out conductiving doping to the polysilicon graphics, wherein the P-type ion is boron ion.
In step S104, gate insulation layer and gate electrode layer are deposited, and carried out to the gate electrode layer with gate electrode light shield
Patterned process carries out N to corresponding polysilicon graphics with the gate electrode light shield and is lightly doped with shape to form gate electrode
At N lightly doped district.
It is understood that formed gate electrode this step specifically includes:
(1) gate insulation layer is deposited；
(2) the depositing gate electrode layer on the grid electrode insulating layer；And
(3) processing is patterned to the gate insulation layer and the gate electrode layer, to form gate electrode as shown in Figure 2
Insulation patterns 40 and gate electrode 50, wherein the position of the grid electrode insulating figure, the gate electrode and the polysilicon graphics
It is corresponding.
Shown in the structural schematic diagram being lightly doped such as the N-type of Fig. 2, forms the step of N is lightly doped and specifically includes:
(1) when carrying out patterned process to the gate electrode layer using gate electrode light shield, the gate electrode light shield is simultaneously
N is carried out to corresponding polysilicon graphics to be lightly doped, and is exposed processing and is lightly doped with generating the first N lightly doped channel and the 2nd N
Channel.I.e. in the present embodiment, the patterned process of gate electrode layer is lightly doped with the N of polysilicon using the light shield progress with along with.
(2) it carries out N in the first N lightly doped channel and the 2nd N lightly doped channel to be lightly doped, to form first
N lightly doped district 31 and the 2nd N lightly doped district 32.Wherein the N is lightly doped using phosphonium ion or arsenic ion.
It is understood that the first N lightly doped district 31 and the 2nd N lightly doped district 32, can effectively prevent short ditch
Channel effect and facilitate reduce source-drain electrode between channel leakage effect.
In step s105, sputter insulating film is etched the insulating film with insulating film light shield to form insulation figure
Shape, while N heavy doping is carried out to polysilicon graphics using the insulating film light shield, to form N heavily doped region.
It is understood that the step of formation insulation patterns, specifically includes:
(1) sputter insulating film, wherein the dielectric constant of the insulating film material is less than or equal to 3.9；
(2) photoresist layer is deposited on the insulating film；And
(3) it is etched according to the insulating pattern on the insulating film light shield, to form insulation patterns 60.
As shown in the structural schematic diagram of the N-type heavy doping of Fig. 3, the step of formation N heavily doped region, is specifically included:
(1) when carrying out patterned process to the insulating film using insulating film light shield, the insulating film light shield is right simultaneously
Corresponding polysilicon graphics carry out N heavy doping, and carry out exposure-processed, to generate the first N heavy doping channel and the 2nd N heavy doping
Channel；And
(2) N heavy doping is carried out, in the first N heavy doping channel and the 2nd N heavy doping channel to generate first
N heavily doped region 33 and the 2nd N heavily doped region 34.Wherein the N is lightly doped using phosphonium ion or arsenic ion.I.e. in the present embodiment,
The light shield with along with is used to carry out with the N heavy doping of polysilicon the patterned process of insulating film.
In step S 106, source electrode and drain electrode is prepared in the top of the N heavily doped region.
Preferably, in the production method, the preparation source electrode and drain electrode the step of before further include:
(1) interlayer dielectric；
(2) the first contact hole is formed on the inter-level dielectric, wherein first contact hole is for being conducted to grid electricity
Pole, and when preparing source electrode and drain electrode, it is electrically connected the gate electrode, source electrode and drain electrode.
Preferably, in the production method, the preparation source electrode and drain electrode the step of after further include:
(1) depositing insulating layer in the source electrode and drain electrode；
(2) the second contact hole of the formation is opened up on the source electrode drain electrode insulating layer；And
(3) pixel deposition electrode, and the pixel electrode is connect by second contact hole with drain electrode.
Gate electrode and N are lightly doped a shared light shield, incited somebody to action by the production method of array substrate provided in an embodiment of the present invention
Insulating film and N heavily doped region share a light shield, reduce the preparation step of low temperature polycrystalline silicon array substrate, to make technique more
Add it is simple, reduce preparation cost while improving production efficiency.
Embodiment two
Referring to Fig. 4, the structural schematic diagram for the array substrate showing in the embodiment of the present invention.
A kind of array substrate, comprising: glass substrate 10, buffer layer 20, polysilicon layer 30, grid electrode insulating layer 40, grid electricity
Pole 50, insulating film 60, source electrode 71 and drain electrode 72, source electrode and drain electrode insulating layer 80 and pixel electrode 90.
Wherein, buffer layer 20 are deposited on the glass substrate 10.
Polysilicon layer 30, comprising: polysilicon graphics 35, the side of the polysilicon graphics 35 is successively are as follows: the first N is lightly doped
Area 31, the first N heavily doped region 33 and the first N lightly doped district 31, the other side of the polysilicon graphics 35 is successively are as follows: the 2nd N is light
Doped region 32, the 2nd N heavily doped region 34 and the 2nd N lightly doped district 32.
It is understood that the N heavily doped region is formed between the N lightly doped district, it may be assumed that the first N heavily doped region 33
In the first N lightly doped district 31, the 2nd N heavily doped region 34 is located in the 2nd N lightly doped district 32.
Gate electrode 50, the figure of the gate electrode 50 are corresponding with the polysilicon graphics 35.
Insulating film 60, also known as inter-level dielectric (Inter Layer D, ILD), including insulation patterns and the first contact hole.
Wherein, the insulation patterns are corresponding with the first N heavily doped region and the 2nd N heavily doped region.Insulating film
The dielectric constant of material be less than or equal to 3.9, i.e. low-dielectric (low-k), the low-dielectric is non-conductive, but can support electric field
Presence, and the distribution capacity between interconnection line can be effectively reduced.
First contact hole makes described for being conducted to gate electrode 50, and when preparing source electrode 71 and drain electrode 72
Gate electrode 71, source electrode 72 and drain electrode 73 are electrically connected.
Source electrode 71 and drain electrode 72 are deposited on the insulating film 60, and are located at the first N heavily doped region and described second
The top of N heavily doped region.And one layer of organic photoresist flatness layer 73 is deposited in the source electrode 71 and drain electrode 72.
Source electrode and drain electrode insulating layer 80, i.e. passivation protection layer, and on the source electrode and drain electrode insulating layer 80
Open up the second contact hole.
Pixel electrode 90 is deposited on the source electrode and drain electrode insulating layer 80, and the pixel electrode 90 is described in
Second contact hole is connect with drain electrode 72.
A shared light shield is lightly doped, by insulating film and N in gate electrode and N by array substrate provided in an embodiment of the present invention
Heavily doped region shares a light shield, reduces the preparation step of low temperature polycrystalline silicon array substrate, thus make technique it is simpler, drop
Low preparation cost improves production efficiency simultaneously.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (9)
1. a kind of production method of array substrate characterized by comprising
(1) buffer layer on the glass substrate；
(2) deposition of amorphous silicon layers on the buffer layer, and the amorphous silicon layer is carried out at crystallization processing and patterning
Reason, to form polysilicon graphics；
(3) conductiving doping is carried out to the polysilicon graphics；
(4) gate insulation layer and gate electrode layer are deposited, patterned process is carried out to be formed to the gate electrode layer with gate electrode light shield
Gate electrode, while N is carried out to corresponding polysilicon graphics with the gate electrode light shield and is lightly doped, to form N lightly doped district, specifically
Include:
When carrying out patterned process to the gate electrode layer using the gate electrode light shield, the gate electrode light shield is simultaneously to correspondence
Polysilicon graphics be exposed processing, to generate the first N lightly doped channel and the 2nd N lightly doped channel；And
It carries out N in the first N lightly doped channel and the 2nd N lightly doped channel to be lightly doped, wherein the N is lightly doped and adopts
With phosphonium ion or arsenic ion；
(5) sputter insulating film is etched the insulating film with insulating film light shield to form insulation patterns, at the same with it is described absolutely
Velum light shield carries out N heavy doping to corresponding polysilicon graphics, to form N heavily doped region；And
(6) source electrode and drain electrode is prepared above the N heavily doped region.
2. production method as described in claim 1, which is characterized in that deposition gate insulation layer and gate electrode layer in step (4) are used
Gate electrode light shield carries out patterned process to the gate electrode layer to form gate electrode, specifically includes:
Deposit gate insulation layer；
The depositing gate electrode layer on the grid electrode insulating layer；And
Processing is patterned using gate electrode light shield to the gate insulation layer and the gate electrode layer, to form grid electrode insulating
Figure and gate electrode, wherein the grid electrode insulating figure, the gate electrode are corresponding with the position of the polysilicon graphics.
3. production method as described in claim 1, which is characterized in that insulating film light shield described in step (5) is to corresponding more
Crystal silicon figure carries out N heavy doping and is specifically included with forming N heavily doped region:
When carrying out patterned process to the insulating film using insulating film light shield, using the insulating film light shield to corresponding more
Crystal silicon figure is exposed processing, to generate the first N heavy doping channel and the 2nd N heavy doping channel；And
N heavy doping is carried out, in the first N heavy doping channel and the 2nd N heavy doping channel to generate the first N heavy doping
Area and the 2nd N heavily doped region, wherein the N heavy doping uses phosphonium ion or arsenic ion.
4. production method as claimed any one in claims 1 to 3, which is characterized in that the N heavily doped region is formed in described
Between N lightly doped district.
5. production method as described in claim 1, which is characterized in that sputter insulating film in step (5), with insulating film light shield pair
The insulating film is etched to form insulation patterns, is specifically included:
Sputter insulating film, wherein the dielectric constant of the insulating film material is less than or equal to 3.9；
Photoresist layer is deposited on the insulating film；And
It is etched according to the insulating pattern on insulating film light shield, to form insulation patterns.
6. production method as described in claim 1, which is characterized in that step (3) carries out conduction to the polysilicon graphics and mixes
It is miscellaneous, it specifically includes:
P-type ion is selected to carry out conductiving doping to the polysilicon graphics, wherein the P-type ion is boron ion.
7. production method as described in claim 1, which is characterized in that step (2) deposition of amorphous silicon layers on the buffer layer,
And crystallization processing and patterned process are carried out to the amorphous silicon layer, to form polysilicon graphics, specifically include:
In 450 DEG C of temperature environments below on the buffer layer deposition of amorphous silicon layers；
Crystallization processing is carried out to the amorphous silicon layer using laser annealing processing, to form polysilicon layer；And
Patterned process is carried out to the polysilicon layer according to preset pattern, to form polysilicon graphics.
8. production method as described in claim 1, it is characterised in that:
The step (6) prepares source electrode and drain electrode above the N heavily doped region, before further include:
The first contact hole is formed, and is conducted to the gate electrode；
The step (6) prepares source electrode and drain electrode above the N heavily doped region, later further include:
The depositing insulating layer in the source electrode and drain electrode；
It opens up to form the second contact hole on the source electrode drain electrode insulating layer；And
Pixel deposition electrode, and the pixel electrode is connect by second contact hole with drain electrode.
9. production method as described in claim 1, which is characterized in that the array substrate includes:
Glass substrate；
Buffer layer is deposited on the glass substrate；
Polysilicon layer, comprising: polysilicon graphics, the side of the polysilicon graphics is successively are as follows: the first N lightly doped district, the first N weight
Doped region and the first N lightly doped district, the other side of the polysilicon graphics is successively are as follows: the 2nd N heavy doping of the 2nd N lightly doped district
Area and the 2nd N lightly doped district；
Grid electrode insulating layer；
Gate electrode, the gate electrode are corresponding with the polysilicon graphics；
Insulating film, including insulation patterns, the insulation patterns and the first N heavily doped region and the 2nd N heavily doped region phase
It is corresponding；And
Source electrode and drain electrode is deposited on the insulating film, and heavily doped positioned at the first N heavily doped region and the 2nd N
The top in miscellaneous area.
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| CN109643657B (en) * | 2017-06-22 | 2022-08-16 | 深圳市柔宇科技股份有限公司 | Manufacturing equipment and manufacturing method of array substrate |
| CN111223877A (en) * | 2019-11-28 | 2020-06-02 | 云谷（固安）科技有限公司 | Array substrate, manufacturing method of array substrate and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996716A (en) * | 2014-04-25 | 2014-08-20 | 京东方科技集团股份有限公司 | Poly-silicon thin film transistor and preparation method thereof, and array substrate |
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| TW480733B (en) * | 2001-04-10 | 2002-03-21 | Ind Tech Res Inst | Self-aligned lightly doped drain polysilicon thin film transistor |
| KR100966420B1 (en) * | 2003-06-30 | 2010-06-28 | 엘지디스플레이 주식회사 | Polycrystalline liquid crystal display device and fabrication method therof |
| TWI336951B (en) * | 2005-05-19 | 2011-02-01 | Au Optronics Corp | Method of forming thin film transistor |
| TW200913269A (en) * | 2007-09-03 | 2009-03-16 | Chunghwa Picture Tubes Ltd | Thin film transistor and manufacturing method thereof |
-
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| CN103996716A (en) * | 2014-04-25 | 2014-08-20 | 京东方科技集团股份有限公司 | Poly-silicon thin film transistor and preparation method thereof, and array substrate |
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