CN105337535A - Self-inspection circuit for brushless DC motor of anesthesia machine - Google Patents
Self-inspection circuit for brushless DC motor of anesthesia machine Download PDFInfo
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- CN105337535A CN105337535A CN201410389408.2A CN201410389408A CN105337535A CN 105337535 A CN105337535 A CN 105337535A CN 201410389408 A CN201410389408 A CN 201410389408A CN 105337535 A CN105337535 A CN 105337535A
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Abstract
The invention relates to the field of an anesthesia machine, in particular to a self-inspection circuit of a brushless DC motor of the anesthesia machine. The self-inspection circuit comprises a master control central processing unit (CPU), a field programmable gate array, a three-phase full-bridge driving circuit and a signal conditioning circuit, wherein the master control CPU is connected with the field programmable gate array; the three-phase full-bridge driving circuit is connected with the master control CPU and the field programmable gate array respectively; when the brushless DC motor is in self inspection, the master control CPU simulates driving signals of the three-phase full-bridge driving circuit in various rotation speed conditions, and the three-phase full-bridge driving circuit can work in various working frequencies by means of the capability of processing pin signals at a high speed by the field programmable gate array; the three-phase full-bridge driving circuit is directly connected with the brushless DC motor; and the field programmable gate array is connected with the brushless DC motor via the signal conditioning circuit and used for detecting a self-inspection signal of the brushless DC motor and sending a self-inspection result to the master control CPU, and therefore, the rotational speed of the brushless DC motor can be accurately regulated.
Description
Technical field
The present invention relates to Anesthesia machine field, particularly relate to a kind of brshless DC motor self-checking circuit of Anesthesia machine.
Background technology
Brshless DC motor (BLDC, BrushlessDCMotor) many fields have been widely used in, BLDC motor is not with commutator, thus more reliable than direct current machine, BLDC motor is also better than AC induction motor in many aspects, BLDC motor generates rotating magnetic flux by rotor magnet, has very high efficiency, and thus they are generally used in the equipment of higher reliability and efficiency.The use of BLDC motor does not need complicated control algolithm.Its maximum feature instead of with electronic commutation circuit the mechanical switching structure be made up of commutator and brush.Thus make brshless DC motor both have the advantage such as simple, reliable, easy to maintenance of alternating current machine, have again that direct current machine operational efficiency is high, the advantage of good speed adjustment features, thus obtain in every respect and apply widely.Be the turbine feed gas of body with brshless DC motor in medical industry use, not only significantly can reduce the volume of source of the gas, save the energy, reduce costs, can also control accurately and reliably turbine, thus obtain stable air-flow and pressure.
Brshless DC motor, in transport, installation and long use procedure, is all likely subject to the damage from external factor, such as, vibrates, electrostatic and overvoltage etc.Because brshless DC motor majority all works at high speeds, during ventilation, be about more than 10000r/min, these potential infringements can be inspired gradually, cause electrical fault, but accurately can not regulate the rotating speed of brshless DC motor in prior art.
Summary of the invention
The object of the invention is to the brshless DC motor self-checking circuit proposing a kind of Anesthesia machine, accurately can regulate the rotating speed of brshless DC motor, to make brshless DC motor safe operation.
For reaching this object, the present invention by the following technical solutions:
A kind of brshless DC motor self-checking circuit of Anesthesia machine, comprise: master cpu, field programmable gate array, three phase full bridge drive circuit and signal conditioning circuit, described master cpu is connected with field programmable gate array, described three phase full bridge drive circuit respectively with master cpu, field programmable gate array connects, when brshless DC motor self-inspection, master cpu simulates the drive singal of three phase full bridge drive circuit under various speed conditions, utilize the ability of the high speed processing pin signal of field programmable gate array, three phase full bridge drive circuit is worked under various operating frequency, described three phase full bridge drive circuit is directly connected with brshless DC motor, described field programmable gate array is connected with brshless DC motor by signal conditioning circuit, in order to record the self-test signal of described brshless DC motor, and self-detection result is sent to master cpu.
Wherein, also comprise and control switching interface circuit, described three phase full bridge drive circuit is connected with master cpu, field programmable gate array respectively by described control switching interface circuit, when brshless DC motor normally runs, master cpu directly controls three phase full bridge drive circuit by described control switching interface circuit, and then controls the running of brshless DC motor; When brshless DC motor self-inspection, master cpu is worked under various operating frequency by field programmable gate array and described control switching interface control circui three phase full bridge drive circuit successively.
Wherein, described control switching interface circuit comprises: level shifting circuit and optocoupler protective circuit; described level shifting circuit is connected with optocoupler protective circuit; described level shifting circuit is used for described drive singal to carry out level conversion, and described optocoupler protective circuit is used for the drive singal after to conversion and carries out light-coupled isolation protection.
Wherein, described level shifting circuit comprises: level transferring chip U1, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C1 and electric capacity C2, wherein, the model of level transferring chip U1 is TSSOP24, the pin one of level transferring chip U1 connects 3.3VD power interface, one end of the pin two contact resistance R4 of level transferring chip U1, the other end of resistance R4 is connected to 3.3VD power interface together with one end of electric capacity C1, the other end ground connection of electric capacity C2, pin 3 ground connection together with pin 4 of level transferring chip U1, the pin 5 of level transferring chip U1 is connected with one end of resistance R1 and ARM-M-Hall-3 node, the pin 7 of level transferring chip U1 is connected with one end of resistance R2 and ARM-M-Hall-2 node, the pin 9 of level transferring chip U1 is connected with one end of resistance R3 and ARM-M-Hall-1 node, 3.3VD power interface is connected to together with the other end of the other end of resistance R1 and the other end of resistance R2 and resistance R3, pin one 1 ground connection together with pin one 2 of level transferring chip U1, pin one 3 ground connection together with pin two 2 of level transferring chip U1, the pin one 5 of level transferring chip U1 links together with one end of Hall-1 node and resistance R7, the pin one 7 of level transferring chip U1 links together with one end of Hall-2 node and resistance R6, the pin one 9 of level transferring chip U1 links together with one end of Hall-3 node and resistance R5, + 5V power interface is connected to together with the other end of the other end of resistance R5 and the other end of resistance R6 and resistance R7, the pin two 4 of level transferring chip U1 is connected to+5V power interface with one end of electric capacity C2, the other end ground connection of electric capacity C2, other pins of level transferring chip U1 are unsettled.
Wherein, described optocoupler protective circuit comprises: optocoupler U2, optocoupler U3, optocoupler U4, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15 and resistance R16, wherein, optocoupler U2, U3, the model of U4 is all TLP521, one end connected node Hall-3 of resistance R8, the other end of resistance R8 connects the pin two of optocoupler U2, the pin one of optocoupler U2 connects 3.3VD power interface, one end of the pin 3 contact resistance R14 of optocoupler U2, the pin 4 of optocoupler U2 is connected with one end of resistance R11 and M-Hall-3 node, the other end of resistance R11 connects+5V power interface, one end connected node Hall-2 of resistance R9, the other end of resistance R9 connects the pin two of optocoupler U3, the pin one of optocoupler U3 connects 3.3VD power interface, one end of the pin 3 contact resistance R15 of optocoupler U3, the pin 4 of optocoupler U3 is connected with one end of resistance R12 and M-Hall-2 node, the other end of resistance R12 connects+5V power interface, one end connected node Hall-1 of resistance R10, the other end of resistance R10 connects the pin two of optocoupler U4, the pin one of optocoupler U4 connects 3.3VD power interface, one end of the pin 3 contact resistance R16 of optocoupler U4, the pin 4 of optocoupler U4 is connected with one end of resistance R13 and M-Hall-1 node, the other end of resistance R13 connects+5V power interface, ground connection together with the other end of the other end of resistance R14 and the other end of resistance R15 and resistance R16.
Wherein, be provided with: synchronous acquisition circuit between described signal conditioning circuit and field programmable gate array, described synchronous acquisition circuit is connected with described field programmable gate array, and described synchronous acquisition circuit is used for the synchronous acquisition of rotating speed and flow velocity.
Wherein, described synchronous acquisition circuit comprises: the SPI interface AD converter, rotating speed level shifter interface and the active crystal oscillator that are connected with field programmable gate array respectively, described SPI interface AD converter is also connected with described signal conditioning circuit, the first frequency division of the frequency of described active crystal oscillator makes an excuse the clock signal of AD converter again after frequency multiplication as SPI, the collection moment of synchronous acquisition circuit for trigger instants, realizes the synchronous acquisition of rotating speed and flow velocity with the rising edge of tach signal.
Wherein, also comprise: power supply chip, field programmable gate array configuring chip and UI interface, described power supply chip and field programmable gate array configuring chip are connected with field programmable gate array respectively, and described UI interface is connected with master cpu.
Wherein, described three phase full bridge drive circuit comprises: P channel mosfet pipe V1, N-channel MOS FET pipe V2, P channel mosfet pipe V3, N-channel MOS FET pipe V4, P channel mosfet pipe V5, N-channel MOS FET pipe V6, direct voltage source Ui, diode VD1, diode VD2, diode VD3, diode VD4, diode VD5, diode VD6, resistance Ra, resistance Rb, resistance Rc, inductance L a, inductance L b, inductance L c, back electromotive force Ea, back electromotive force Eb, back electromotive force Ec, mid point Un is connected with the winding Y type of brshless DC motor, wherein, the source electrode of P channel mosfet pipe V1 and the source electrode of P channel mosfet pipe V3, the source electrode of P channel mosfet pipe V5, the negative pole of diode VD1, the negative pole of diode VD3, the negative pole of diode VD5 and one end of direct voltage source Ui link together, the source electrode of N-channel MOS FET pipe V2 and the source electrode of N-channel MOS FET pipe V4, the source electrode of N-channel MOS FET pipe V6, the positive pole of diode VD2, the positive pole of diode VD4, the positive pole of diode VD6 and the other end of direct voltage source Ui link together, the drain electrode of P channel mosfet pipe V1 and the drain electrode of N-channel MOS FET pipe V2, the positive pole of diode VD1, the negative pole of diode VD2 and one end of resistance Ra link together, the drain electrode of P channel mosfet pipe V3 and the drain electrode of N-channel MOS FET pipe V4, the positive pole of diode VD3, the negative pole of diode VD4 and one end of resistance Rb link together, the drain electrode of P channel mosfet pipe V5 and the drain electrode of N-channel MOS FET pipe V6, the positive pole of diode VD5, the negative pole of diode VD6 and one end of resistance Rc link together, the grid of P channel mosfet pipe V1 is unsettled, the grid of N-channel MOS FET pipe V2 is unsettled, the grid of P channel mosfet pipe V3 is unsettled, the grid of N-channel MOS FET pipe V4 is unsettled, the grid of P channel mosfet pipe V5 is unsettled, the grid of N-channel MOS FET pipe V6 is unsettled, the other end of resistance Ra connects one end of inductance L a, the other end of inductance L a connects one end of back electromotive force Ea, the other end of resistance Rb connects one end of inductance L b, the other end of inductance L b connects one end of back electromotive force Eb, the other end of resistance Rc connects one end of inductance L c, and the other end of inductance L c connects one end of back electromotive force Ec, the other end of back electromotive force Ea and the other end of back electromotive force Eb, the other end of back electromotive force Ec is connected to the winding Y type connection mid point Un of brshless DC motor together.
Beneficial effect of the present invention is: a kind of brshless DC motor self-checking circuit of Anesthesia machine, comprise: master cpu, field programmable gate array, three phase full bridge drive circuit and signal conditioning circuit, described master cpu is connected with field programmable gate array, described three phase full bridge drive circuit respectively with master cpu, field programmable gate array connects, when brshless DC motor self-inspection, master cpu simulates the drive singal of three phase full bridge drive circuit under various speed conditions, utilize the ability of the high speed processing pin signal of field programmable gate array, three phase full bridge drive circuit is worked under various operating frequency, described three phase full bridge drive circuit is directly connected with brshless DC motor, described field programmable gate array is connected with brshless DC motor by signal conditioning circuit, in order to record the self-test signal of described brshless DC motor, and self-detection result is sent to master cpu, accurately can regulate the rotating speed of brshless DC motor accordingly.
Accompanying drawing explanation
Fig. 1 is the brshless DC motor self-checking circuit functional structure chart of a kind of Anesthesia machine that the specific embodiment of the invention provides.
Fig. 2 is the circuit diagram of the level shifting circuit that the specific embodiment of the invention provides.
Fig. 3 is the circuit diagram of the optocoupler protective circuit that the specific embodiment of the invention provides.
Fig. 4 is the circuit diagram of the three phase full bridge drive circuit that the specific embodiment of the invention provides.
Embodiment
Technical scheme of the present invention is further illustrated by embodiment below in conjunction with Fig. 1-Fig. 4.
Fig. 1 is the brshless DC motor self-checking circuit functional structure chart of a kind of Anesthesia machine that the specific embodiment of the invention provides.
A kind of brshless DC motor self-checking circuit of Anesthesia machine, comprise: master cpu, field programmable gate array, three phase full bridge drive circuit and signal conditioning circuit, described master cpu is connected with field programmable gate array, described three phase full bridge drive circuit respectively with master cpu, field programmable gate array connects, when brshless DC motor self-inspection, master cpu simulates the drive singal of three phase full bridge drive circuit under various speed conditions, utilize the ability of the high speed processing pin signal of field programmable gate array, three phase full bridge drive circuit is worked under various operating frequency, described three phase full bridge drive circuit is directly connected with brshless DC motor, described field programmable gate array is connected with brshless DC motor by signal conditioning circuit, in order to record the self-test signal of described brshless DC motor, and self-detection result is sent to master cpu.
In the present embodiment, also comprise and control switching interface circuit, described three phase full bridge drive circuit is connected with master cpu, field programmable gate array respectively by described control switching interface circuit, when brshless DC motor normally runs, master cpu directly controls three phase full bridge drive circuit by described control switching interface circuit, and then controls the running of brshless DC motor; When brshless DC motor self-inspection, master cpu is worked under various operating frequency by field programmable gate array and described control switching interface control circui three phase full bridge drive circuit successively.
In the present embodiment; described control switching interface circuit comprises: level shifting circuit and optocoupler protective circuit; described level shifting circuit is connected with optocoupler protective circuit; described level shifting circuit is used for described drive singal to carry out level conversion, and described optocoupler protective circuit is used for the drive singal after to conversion and carries out light-coupled isolation protection.
As shown in Figure 2, in the present embodiment, described level shifting circuit comprises: level transferring chip U1, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C1 and electric capacity C2, wherein, the model of level transferring chip U1 is TSSOP24, the pin one of level transferring chip U1 connects 3.3VD power interface, one end of the pin two contact resistance R4 of level transferring chip U1, the other end of resistance R4 is connected to 3.3VD power interface together with one end of electric capacity C1, the other end ground connection of electric capacity C2, pin 3 ground connection together with pin 4 of level transferring chip U1, the pin 5 of level transferring chip U1 is connected with one end of resistance R1 and ARM-M-Hall-3 node, the pin 7 of level transferring chip U1 is connected with one end of resistance R2 and ARM-M-Hall-2 node, the pin 9 of level transferring chip U1 is connected with one end of resistance R3 and ARM-M-Hall-1 node, 3.3VD power interface is connected to together with the other end of the other end of resistance R1 and the other end of resistance R2 and resistance R3, pin one 1 ground connection together with pin one 2 of level transferring chip U1, pin one 3 ground connection together with pin two 2 of level transferring chip U1, the pin one 5 of level transferring chip U1 links together with one end of Hall-1 node and resistance R7, the pin one 7 of level transferring chip U1 links together with one end of Hall-2 node and resistance R6, the pin one 9 of level transferring chip U1 links together with one end of Hall-3 node and resistance R5, + 5V power interface is connected to together with the other end of the other end of resistance R5 and the other end of resistance R6 and resistance R7, the pin two 4 of level transferring chip U1 is connected to+5V power interface with one end of electric capacity C2, the other end ground connection of electric capacity C2, other pins of level transferring chip U1 are unsettled.
In the present embodiment, described drive singal is hall signal (Hall).
As shown in Figure 3, in the present embodiment, described optocoupler protective circuit comprises: optocoupler U2, optocoupler U3, optocoupler U4, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15 and resistance R16, wherein, optocoupler U2, U3, the model of U4 is all TLP521, one end connected node Hall-3 of resistance R8, the other end of resistance R8 connects the pin two of optocoupler U2, the pin one of optocoupler U2 connects 3.3VD power interface, one end of the pin 3 contact resistance R14 of optocoupler U2, the pin 4 of optocoupler U2 is connected with one end of resistance R11 and M-Hall-3 node, the other end of resistance R11 connects+5V power interface, one end connected node Hall-2 of resistance R9, the other end of resistance R9 connects the pin two of optocoupler U3, the pin one of optocoupler U3 connects 3.3VD power interface, one end of the pin 3 contact resistance R15 of optocoupler U3, the pin 4 of optocoupler U3 is connected with one end of resistance R12 and M-Hall-2 node, the other end of resistance R12 connects+5V power interface, one end connected node Hall-1 of resistance R10, the other end of resistance R10 connects the pin two of optocoupler U4, the pin one of optocoupler U4 connects 3.3VD power interface, one end of the pin 3 contact resistance R16 of optocoupler U4, the pin 4 of optocoupler U4 is connected with one end of resistance R13 and M-Hall-1 node, the other end of resistance R13 connects+5V power interface, ground connection together with the other end of the other end of resistance R14 and the other end of resistance R15 and resistance R16.
In the present embodiment, be provided with: synchronous acquisition circuit between described signal conditioning circuit and field programmable gate array, described synchronous acquisition circuit is connected with described field programmable gate array, and described synchronous acquisition circuit is used for the synchronous acquisition of rotating speed and flow velocity.
In the present embodiment, described synchronous acquisition circuit comprises: the SPI interface AD converter, rotating speed level shifter interface and the active crystal oscillator that are connected with field programmable gate array respectively, described SPI interface AD converter is also connected with described signal conditioning circuit, the first frequency division of the frequency of described active crystal oscillator makes an excuse the clock signal of AD converter again after frequency multiplication as SPI, the collection moment of synchronous acquisition circuit for trigger instants, realizes the synchronous acquisition of rotating speed and flow velocity with the rising edge of tach signal.
In the present embodiment, also comprise: power supply chip, field programmable gate array configuring chip and UI interface, described power supply chip and field programmable gate array configuring chip are connected with field programmable gate array respectively, described UI interface is connected with master cpu, described power supply chip is used for providing power supply to self-checking circuit, and described UI interface is used for man-machine interaction.
As shown in Figure 4, in the present embodiment, described three phase full bridge drive circuit comprises: P channel mosfet pipe V1, N-channel MOS FET pipe V2, P channel mosfet pipe V3, N-channel MOS FET pipe V4, P channel mosfet pipe V5, N-channel MOS FET pipe V6, direct voltage source Ui, diode VD1, diode VD2, diode VD3, diode VD4, diode VD5, diode VD6, resistance Ra, resistance Rb, resistance Rc, inductance L a, inductance L b, inductance L c, back electromotive force Ea, back electromotive force Eb, back electromotive force Ec, mid point Un is connected with the winding Y type of brshless DC motor, wherein, the source electrode of P channel mosfet pipe V1 and the source electrode of P channel mosfet pipe V3, the source electrode of P channel mosfet pipe V5, the negative pole of diode VD1, the negative pole of diode VD3, the negative pole of diode VD5 and one end of direct voltage source Ui link together, the source electrode of N-channel MOS FET pipe V2 and the source electrode of N-channel MOS FET pipe V4, the source electrode of N-channel MOS FET pipe V6, the positive pole of diode VD2, the positive pole of diode VD4, the positive pole of diode VD6 and the other end of direct voltage source Ui link together, the drain electrode of P channel mosfet pipe V1 and the drain electrode of N-channel MOS FET pipe V2, the positive pole of diode VD1, the negative pole of diode VD2 and one end of resistance Ra link together, the drain electrode of P channel mosfet pipe V3 and the drain electrode of N-channel MOS FET pipe V4, the positive pole of diode VD3, the negative pole of diode VD4 and one end of resistance Rb link together, the drain electrode of P channel mosfet pipe V5 and the drain electrode of N-channel MOS FET pipe V6, the positive pole of diode VD5, the negative pole of diode VD6 and one end of resistance Rc link together, the grid of P channel mosfet pipe V1 is unsettled, the grid of N-channel MOS FET pipe V2 is unsettled, the grid of P channel mosfet pipe V3 is unsettled, the grid of N-channel MOS FET pipe V4 is unsettled, the grid of P channel mosfet pipe V5 is unsettled, the grid of N-channel MOS FET pipe V6 is unsettled, the other end of resistance Ra connects one end of inductance L a, the other end of inductance L a connects one end of back electromotive force Ea, the other end of resistance Rb connects one end of inductance L b, the other end of inductance L b connects one end of back electromotive force Eb, the other end of resistance Rc connects one end of inductance L c, and the other end of inductance L c connects one end of back electromotive force Ec, the other end of back electromotive force Ea and the other end of back electromotive force Eb, the other end of back electromotive force Ec is connected to the winding Y type connection mid point Un of brshless DC motor together.
In the present embodiment, the parameter of above-mentioned various components and parts is a preferred embodiment of the present invention, and those skilled in the art can realize similar effect by the parameter adjusting above-mentioned components and parts, and these are all within protection scope of the present invention.
The foregoing is only the specific embodiment of the present invention, these describe just in order to explain principle of the present invention, and can not be interpreted as limiting the scope of the invention by any way.Based on explanation herein, those skilled in the art does not need to pay performing creative labour can associate other specific implementation method of the present invention, and these modes all will fall within protection scope of the present invention.
Claims (9)
1. the brshless DC motor self-checking circuit of an Anesthesia machine, it is characterized in that, comprise: master cpu, field programmable gate array, three phase full bridge drive circuit and signal conditioning circuit, described master cpu is connected with field programmable gate array, described three phase full bridge drive circuit respectively with master cpu, field programmable gate array connects, when brshless DC motor self-inspection, master cpu simulates the drive singal of three phase full bridge drive circuit under various speed conditions, utilize the ability of the high speed processing pin signal of field programmable gate array, three phase full bridge drive circuit is worked under various operating frequency, described three phase full bridge drive circuit is directly connected with brshless DC motor, described field programmable gate array is connected with brshless DC motor by signal conditioning circuit, in order to record the self-test signal of described brshless DC motor, and self-detection result is sent to master cpu.
2. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 1, it is characterized in that, also comprise and control switching interface circuit, described three phase full bridge drive circuit is connected with master cpu, field programmable gate array respectively by described control switching interface circuit, when brshless DC motor normally runs, master cpu directly controls three phase full bridge drive circuit by described control switching interface circuit, and then controls the running of brshless DC motor; When brshless DC motor self-inspection, master cpu is worked under various operating frequency by field programmable gate array and described control switching interface control circui three phase full bridge drive circuit successively.
3. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 2; it is characterized in that; described control switching interface circuit comprises: level shifting circuit and optocoupler protective circuit; described level shifting circuit is connected with optocoupler protective circuit; described level shifting circuit is used for described drive singal to carry out level conversion, and described optocoupler protective circuit is used for the drive singal after to conversion and carries out light-coupled isolation protection.
4. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 3, it is characterized in that, described level shifting circuit comprises: level transferring chip U1, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C1 and electric capacity C2, wherein, the model of level transferring chip U1 is TSSOP24, the pin one of level transferring chip U1 connects 3.3VD power interface, one end of the pin two contact resistance R4 of level transferring chip U1, the other end of resistance R4 is connected to 3.3VD power interface together with one end of electric capacity C1, the other end ground connection of electric capacity C2, pin 3 ground connection together with pin 4 of level transferring chip U1, the pin 5 of level transferring chip U1 is connected with one end of resistance R1 and ARM-M-Hall-3 node, the pin 7 of level transferring chip U1 is connected with one end of resistance R2 and ARM-M-Hall-2 node, the pin 9 of level transferring chip U1 is connected with one end of resistance R3 and ARM-M-Hall-1 node, 3.3VD power interface is connected to together with the other end of the other end of resistance R1 and the other end of resistance R2 and resistance R3, pin one 1 ground connection together with pin one 2 of level transferring chip U1, pin one 3 ground connection together with pin two 2 of level transferring chip U1, the pin one 5 of level transferring chip U1 links together with one end of Hall-1 node and resistance R7, the pin one 7 of level transferring chip U1 links together with one end of Hall-2 node and resistance R6, the pin one 9 of level transferring chip U1 links together with one end of Hall-3 node and resistance R5, + 5V power interface is connected to together with the other end of the other end of resistance R5 and the other end of resistance R6 and resistance R7, the pin two 4 of level transferring chip U1 is connected to+5V power interface with one end of electric capacity C2, the other end ground connection of electric capacity C2, other pins of level transferring chip U1 are unsettled.
5. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 4, it is characterized in that, described optocoupler protective circuit comprises: optocoupler U2, optocoupler U3, optocoupler U4, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15 and resistance R16, wherein, optocoupler U2, U3, the model of U4 is all TLP521, one end connected node Hall-3 of resistance R8, the other end of resistance R8 connects the pin two of optocoupler U2, the pin one of optocoupler U2 connects 3.3VD power interface, one end of the pin 3 contact resistance R14 of optocoupler U2, the pin 4 of optocoupler U2 is connected with one end of resistance R11 and M-Hall-3 node, the other end of resistance R11 connects+5V power interface, one end connected node Hall-2 of resistance R9, the other end of resistance R9 connects the pin two of optocoupler U3, the pin one of optocoupler U3 connects 3.3VD power interface, one end of the pin 3 contact resistance R15 of optocoupler U3, the pin 4 of optocoupler U3 is connected with one end of resistance R12 and M-Hall-2 node, the other end of resistance R12 connects+5V power interface, one end connected node Hall-1 of resistance R10, the other end of resistance R10 connects the pin two of optocoupler U4, the pin one of optocoupler U4 connects 3.3VD power interface, one end of the pin 3 contact resistance R16 of optocoupler U4, the pin 4 of optocoupler U4 is connected with one end of resistance R13 and M-Hall-1 node, the other end of resistance R13 connects+5V power interface, ground connection together with the other end of the other end of resistance R14 and the other end of resistance R15 and resistance R16.
6. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 1, it is characterized in that, be provided with between described signal conditioning circuit and field programmable gate array: synchronous acquisition circuit, described synchronous acquisition circuit is connected with described field programmable gate array, and described synchronous acquisition circuit is used for the synchronous acquisition of rotating speed and flow velocity.
7. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 6, it is characterized in that, described synchronous acquisition circuit comprises: the SPI interface AD converter, rotating speed level shifter interface and the active crystal oscillator that are connected with field programmable gate array respectively, described SPI interface AD converter is also connected with described signal conditioning circuit, the first frequency division of the frequency of described active crystal oscillator makes an excuse the clock signal of AD converter again after frequency multiplication as SPI, the collection moment of synchronous acquisition circuit for trigger instants, realizes the synchronous acquisition of rotating speed and flow velocity with the rising edge of tach signal.
8. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 1, it is characterized in that, also comprise: power supply chip, field programmable gate array configuring chip and UI interface, described power supply chip and field programmable gate array configuring chip are connected with field programmable gate array respectively, and described UI interface is connected with master cpu.
9. the brshless DC motor self-checking circuit of a kind of Anesthesia machine according to claim 1, is characterized in that, described three phase full bridge drive circuit comprises: P channel mosfet pipe V1, N-channel MOS FET pipe V2, P channel mosfet pipe V3, N-channel MOS FET pipe V4, P channel mosfet pipe V5, N-channel MOS FET pipe V6, direct voltage source Ui, diode VD1, diode VD2, diode VD3, diode VD4, diode VD5, diode VD6, resistance Ra, resistance Rb, resistance Rc, inductance L a, inductance L b, inductance L c, back electromotive force Ea, back electromotive force Eb, back electromotive force Ec, mid point Un is connected with the winding Y type of brshless DC motor, wherein, the source electrode of P channel mosfet pipe V1 and the source electrode of P channel mosfet pipe V3, the source electrode of P channel mosfet pipe V5, the negative pole of diode VD1, the negative pole of diode VD3, the negative pole of diode VD5 and one end of direct voltage source Ui link together, the source electrode of N-channel MOS FET pipe V2 and the source electrode of N-channel MOS FET pipe V4, the source electrode of N-channel MOS FET pipe V6, the positive pole of diode VD2, the positive pole of diode VD4, the positive pole of diode VD6 and the other end of direct voltage source Ui link together, the drain electrode of P channel mosfet pipe V1 and the drain electrode of N-channel MOS FET pipe V2, the positive pole of diode VD1, the negative pole of diode VD2 and one end of resistance Ra link together, the drain electrode of P channel mosfet pipe V3 and the drain electrode of N-channel MOS FET pipe V4, the positive pole of diode VD3, the negative pole of diode VD4 and one end of resistance Rb link together, the drain electrode of P channel mosfet pipe V5 and the drain electrode of N-channel MOS FET pipe V6, the positive pole of diode VD5, the negative pole of diode VD6 and one end of resistance Rc link together, the grid of P channel mosfet pipe V1 is unsettled, the grid of N-channel MOS FET pipe V2 is unsettled, the grid of P channel mosfet pipe V3 is unsettled, the grid of N-channel MOS FET pipe V4 is unsettled, the grid of P channel mosfet pipe V5 is unsettled, the grid of N-channel MOS FET pipe V6 is unsettled, the other end of resistance Ra connects one end of inductance L a, the other end of inductance L a connects one end of back electromotive force Ea, the other end of resistance Rb connects one end of inductance L b, the other end of inductance L b connects one end of back electromotive force Eb, the other end of resistance Rc connects one end of inductance L c, and the other end of inductance L c connects one end of back electromotive force Ec, the other end of back electromotive force Ea and the other end of back electromotive force Eb, the other end of back electromotive force Ec is connected to the winding Y type connection mid point Un of brshless DC motor together.
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