CN105304470A - LTPS array substrate, manufacturing method thereof and display device - Google Patents
LTPS array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN105304470A CN105304470A CN201510633394.9A CN201510633394A CN105304470A CN 105304470 A CN105304470 A CN 105304470A CN 201510633394 A CN201510633394 A CN 201510633394A CN 105304470 A CN105304470 A CN 105304470A
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- 239000000758 substrate Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 103
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 63
- 229920005591 polysilicon Polymers 0.000 claims description 61
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 5
- 238000005516 engineering process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Liquid Crystal (AREA)
Abstract
The invention discloses an LTPS array substrate, a manufacturing method thereof and a display device. The method comprises steps that, a substrate is provided; a buffer layer, a semiconductor graph layer and a first insulation layer are sequentially formed on the substrate; a grid electrode layer is formed on the first insulation layer, thickness of a zone of the first insulation layer not covered by a grid electrode graph is reduced; a second insulation layer and a source-drain layer are sequentially formed on the grid electrode layer. Through the method, the first insulation layer with different thicknesses can be formed, on one hand, a TFT threshold voltage is improved, and on the other hand, the low dosage phosphor doping effect is improved.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of LTPS array base palte and manufacture method, display unit.
Background technology
Low-temperature polysilicon silicon technology LTPS (LowTemperaturePoly-silicon) develops at present just rapidly, and its sharpest edges are ultra-thin, lightweight, low power consumption, can provide more gorgeous color and image more clearly.
In the manufacturing process of LTPS array base palte, in order to save the access times of light shield, in general all do not use light shield when N+ doping and N-doping.N+ doping do not use light shield to represent the raceway groove of NTFT and PTFT has all done boron implantation, the threshold voltage of NTFT and PTFT can be smaller, affects the driving of CMOS.
Current common practices is the size increasing threshold voltage by increasing GI thickness, but GI thickness can affect the effect of phosphorus low dosage doping.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of LTPS array base palte and manufacture method, display unit, can form the first insulating barrier that thickness is different, improves the threshold voltage of TFT on the one hand, improves the effect of phosphorus low dosage doping on the other hand.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: the manufacture method providing a kind of LTPS array base palte, and the method comprises: provide a substrate; Substrate is formed resilient coating, semiconductor figure layer and the first insulating barrier successively; First insulating barrier forms grid layer, and reduces the first insulating barrier not by the thickness of gate patterns occlusion area; Grid layer forms the second insulating barrier and source-drain layer successively.
Wherein, the first insulating barrier forms grid layer, and reduce the first insulating barrier not by the step of the thickness of gate patterns occlusion area, specifically comprise: make on the first insulating barrier, to define gate patterns with photoresist; Etch process is adopted to form grid layer on a photoresist, adopt etch process not etched by the region that gate patterns blocks the first insulating barrier simultaneously, be not less than the first insulating barrier by gate patterns occlusion area by the thickness of gate patterns occlusion area to make the first insulating barrier.
Wherein, grid layer is formed the step of the second insulating barrier and source-drain layer successively, specifically comprises: on grid layer, form the second insulating barrier; Second insulating barrier and the first insulating barrier are formed the first through hole and the second through hole; Wherein, the first through hole and the second through hole all run through the first insulating barrier and the second insulating barrier; Form source electrode and drain electrode over the second dielectric, source electrode and drain electrode are connected the two poles of the earth of semiconductor figure layer with the second through hole respectively by the first through hole.
Wherein, substrate is formed the step of resilient coating, semiconductor figure layer and the first insulating barrier successively, specifically comprises: on substrate, form resilient coating; Form spaced first polysilicon layer and the second polysilicon layer on the buffer layer; N+ doping is carried out to the first polysilicon layer; First polysilicon layer and the second polysilicon layer form the first insulating barrier.
Wherein, the first insulating barrier forms grid layer, and reduce the first insulating barrier not by the step of the thickness of gate patterns occlusion area, specifically comprise: make on the first insulating barrier, to define first grid figure and second grid figure with photoresist; Wherein, first grid figure and second grid figure corresponding first polysilicon layer and the second polysilicon layer respectively; Etch process is adopted to form first grid layer and second grid layer on a photoresist, adopt etch process not etched by the region of first grid figure and second grid graph shealtering the first insulating barrier simultaneously, be not less than the first insulating barrier by first grid figure and second grid graph shealtering region by the thickness in first grid figure and second grid graph shealtering region to make the first insulating barrier.
Wherein, the first insulating barrier forms grid layer, and reduce the first insulating barrier not by after the step of the thickness of gate patterns occlusion area, also comprise: N-doping is carried out to the first polysilicon layer; P+ doping is carried out to the second polysilicon layer.
Wherein, the first polysilicon layer is carried out to the step of N-doping, be specially: the doping of phosphorus low dosage is carried out to the first polysilicon layer; Second polysilicon layer is carried out to the step of P+ doping, be specially: boron doping is carried out to the second polysilicon layer.
Wherein, grid layer is formed the step of the second insulating barrier and source-drain layer successively, specifically comprises: on grid layer, form the second insulating barrier; Second insulating barrier and the first insulating barrier are formed third through-hole, fourth hole, fifth hole and the 6th through hole; Wherein, third through-hole, fourth hole, fifth hole and the 6th through hole all run through the first insulating barrier and the second insulating barrier; Form the first source electrode, the first drain electrode, the second source electrode and the second drain electrode over the second dielectric, first source electrode and the first drain electrode are connected the two poles of the earth of the first polysilicon layer with fourth hole respectively by third through-hole, the second source electrode and the second drain electrode are connected the two poles of the earth of the second polysilicon layer with the 6th through hole respectively by fifth hole.
For solving the problems of the technologies described above, another technical solution used in the present invention is: provide a kind of LTPS array base palte, and this LTPS array base palte comprises: substrate and the resilient coating, semiconductor figure layer, the first insulating barrier, grid layer, the second insulating barrier and the source-drain layer that are formed at successively on substrate; Wherein, on the first insulating barrier, the thickness in the region of non-cover gate layer is less than the thickness in the region of cover gate layer on the first insulating barrier.
For solving the problems of the technologies described above, another technical solution used in the present invention is: provide a kind of display unit, and this display unit comprises array base palte described above.
The invention has the beneficial effects as follows: the situation being different from prior art, the present invention.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of manufacture method first execution mode of LTPS array base palte of the present invention;
Fig. 2 A is the structural representation of LTPS array base palte in the manufacture method first execution mode step 102 of LTPS array base palte of the present invention;
Fig. 2 B is the structural representation of LTPS array base palte in the manufacture method first execution mode step 103 of LTPS array base palte of the present invention;
Fig. 2 C is the structural representation of LTPS array base palte in the manufacture method first execution mode step 104 of LTPS array base palte of the present invention;
Fig. 3 is the schematic flow sheet of manufacture method second execution mode of LTPS array base palte of the present invention;
Fig. 4 A is the structural representation of LTPS array base palte in the manufacture method second execution mode step 304 of LTPS array base palte of the present invention;
Fig. 4 B is the structural representation of LTPS array base palte in the manufacture method second execution mode step 308 of LTPS array base palte of the present invention;
Fig. 4 C is the structural representation of LTPS array base palte in the manufacture method second execution mode step 309 of LTPS array base palte of the present invention;
Fig. 4 D is the structural representation after the manufacture method second execution mode LTPS array base palte of LTPS array base palte of the present invention completes;
Fig. 5 is the structural representation of LTPS array base palte one execution mode of the present invention;
Fig. 6 is the structural representation of display unit one execution mode of the present invention.
Embodiment
Consult Fig. 1, the schematic flow sheet of manufacture method first execution mode of LTPS array base palte of the present invention, consult Fig. 2 A-Fig. 2 C, the method comprises simultaneously:
Step 101 a: substrate 200 is provided.
Step 102: form resilient coating 201, semiconductor figure layer 202 and the first insulating barrier 203 on substrate 200 successively.
Wherein, more than substrate being formed successively, the method for each layer is generally chemical vapour deposition (CVD) (CVD) or physical vapour deposition (PVD) (PVD).
Resilient coating 201 is generally that one deck SiOx and layer of sin x superposes formation jointly, and the first insulating barrier 203 is then formed by the mixture of SiOx and SiNx.
Semiconductor figure layer 202 is generally deposit one deck amorphous silicon on the buffer layer 201, then forms polysilicon by radium-shine annealing technology, and carries out graphical treatment to this polysilicon, to form patterned polysilicon.
In one embodiment, after formation semiconductor figure layer 202, first ion doping is carried out to this semiconductor figure layer 202, then on semiconductor figure layer 202 depositing first insulator layer 203.
Step 103: form grid layer 204 on the first insulating barrier 203, and reduce the first insulating barrier 203 not by the thickness of gate patterns occlusion area.
As can be seen from Fig. 2 B, be significantly less than the first insulating barrier 203 immediately below grid layer 204 at the thickness of the first insulating barrier 203 both sides (not by part that grid layer 204 blocks).In this way, when double conductor pattern layer 202 carries out ion doping, because the thickness of the first insulating barrier 203 covering doped region is less, the effect of ion doping is promoted greatly; Meanwhile, the thickness of the first insulating barrier 203 immediately below grid layer 204 increases, and the distance between grid layer 204 and semiconductor figure layer 202 is increased, improves the threshold voltage of TFT.
Wherein, this semiconductor figure layer 202 can be NMOS also can be PMOS.
Step 104: form the second insulating barrier 205 and source-drain layer 206 on grid layer 204 successively.
Wherein, the second insulating barrier 205 is generally the mixture of SiOx and SiNx, also can be that one or both in SiOx and SiNx carry out stacked.Source-drain layer 206 is generally metal, and source-drain layer 206 comprises source electrode and drain electrode, is connected with two of semiconductor figure layer 202 symmetrical doped regions with the through hole respectively by the first insulating barrier 203 and the second insulating barrier 205.
Be different from prior art, present embodiment, by the manufacturing process of LTPS array base palte, processes the thickness of the first insulating barrier, to form thicker region and thinner region.On the one hand, the distance between grid and polysilicon layer is increased, thus improve the threshold voltage of TFT; On the other hand, due to corresponding doping polycrystalline silicon layer district, thinner region, so that in follow-up doping process, improve the effect of phosphorus low dosage doping.
Consult Fig. 3, the schematic flow sheet of manufacture method second execution mode of LTPS array base palte of the present invention, consult Fig. 4 A-Fig. 4 C, the method comprises simultaneously:
Step 301 a: substrate 400 is provided.
This substrate 400 generally adopts glass substrate, when doing flexible curved surface display screen, also can adopt plastic, transparent substrate.
Step 302: form resilient coating 401 over substrate 400.
Step 303: form spaced first polysilicon layer 4021 and the second polysilicon layer 4022 on resilient coating 401.
Particularly, first on resilient coating 401, form amorphous silicon a-si, realize the crystallization of amorphous silicon again through radium-shine annealing process, to form polysilicon p-si, then by etch process, graphical treatment is carried out to form the first polysilicon layer 4021 and the second polysilicon layer 4022 to polysilicon.
Step 304: N+ doping is carried out to the first polysilicon layer 4021.
Consult Fig. 4 A, wherein, carrying out in the process of N+ doping to the first polysilicon layer 4021, adopt photoresistance to block to the undoped region of the first polysilicon layer 4021 and the second polysilicon 4022.Particularly, this N+ doping can be the high dose doping of phosphorus.
Step 305: form the first insulating barrier on the first polysilicon layer and the second polysilicon layer.
Step 306: make to define first grid figure and second grid figure with photoresist on the first insulating barrier 403.
Wherein, first grid figure and second grid figure corresponding first polysilicon layer 4021 and the second polysilicon layer 4022 respectively.Particularly, first grid figure and second grid figure are corresponding is respectively undoped region on the first polysilicon layer 4021 and the second polysilicon layer 4022.
Step 307: adopt etch process to form first grid layer 4041 and second grid layer 4042 on a photoresist, adopt etch process not etched by the region of first grid figure and second grid graph shealtering the first insulating barrier 403 simultaneously, be not less than the first insulating barrier 403 by first grid figure and second grid graph shealtering region by the thickness in first grid figure and second grid graph shealtering region to make the first insulating barrier 403.
Step 308: N-doping is carried out to the first polysilicon layer.
Consult Fig. 4 B, carrying out in the process of N-doping to the first polysilicon layer 4021, light shield can adopted to block to the second polysilicon 4022, because N-is doped to the doping of phosphorus low dosage, so also photoresistance can not be adopted to block to the second polysilicon 4022.Step 309: P+ doping is carried out to the second polysilicon layer.
Consult Fig. 4 C, carrying out in the process of P+ doping to the second polysilicon layer 4022, photoresistance can adopted to block to the first polysilicon 4021.Particularly, this P+ doping can be the high dose doping of boron.
Step 310: form the second insulating barrier 405 on grid layer.
Step 311: form third through-hole, fourth hole, fifth hole and the 6th through hole on the second insulating barrier 405 and the first insulating barrier 403.
Wherein, third through-hole, fourth hole, fifth hole and the 6th through hole all run through the first insulating barrier and the second insulating barrier.
Step 312: form the first source electrode 4061, first drain electrode 4062, second source electrode 4063 and the second drain electrode 4064 over the second dielectric, first source electrode 4061 and the first drain electrode 4062 are connected the two poles of the earth of the first polysilicon layer 4021 with fourth hole respectively by third through-hole, the second source electrode 4063 and the second drain electrode 4064 are connected the two poles of the earth of the second polysilicon layer 4022 with the 6th through hole respectively by fifth hole.
Consult Fig. 4 D, although do not identify the position of through hole in figure, because the first source electrode 4061, first drain electrode 4062, second source electrode 4063 and the second drain electrode 4064 run through each through hole above, so the position of through hole should correspond to each source-drain electrode.
Be different from prior art, present embodiment is mainly used in the making of CMOS, by the manufacturing process of LTPS array base palte, processes the thickness of the first insulating barrier, to form thicker region and thinner region.On the one hand, the distance between grid and polysilicon layer is increased, thus improve the threshold voltage of TFT; On the other hand, due to corresponding doping polycrystalline silicon layer district, thinner region, so that in follow-up doping process, improve the effect of phosphorus low dosage doping.
Consult Fig. 5, the structural representation of LTPS array base palte one execution mode of the present invention, this LTPS array base palte comprises: substrate 500 and the resilient coating 501, semiconductor figure layer 502, first insulating barrier 503, grid layer 504, second insulating barrier 505 and the source-drain layer 506 that are formed at successively on substrate 500; Wherein, on the first insulating barrier 503, the thickness in the region of non-cover gate layer 504 is less than the thickness in the region of cover gate layer 504 on the first insulating barrier 503.
Wherein, present embodiment is applied to NMOS or this PMOS, in other modes, also can apply to CMOS.
Consult Fig. 6, the structural representation of display unit one execution mode of the present invention, this display unit comprises display floater 610 and backlight 620, and wherein, display floater 610 comprises color membrane substrates 611, LTPS array base palte 613 and the liquid crystal layer between color membrane substrates 611 and LTPS array base palte 613 612.Particularly, this LTPS array base palte 613 is as the array base palte in each execution mode above-mentioned.
What deserves to be explained is, in LTPS array base palte one execution mode and display unit one execution mode, the execution mode of its execution mode and above-mentioned LTPS array substrate manufacturing method is similar, repeats no more here.
The foregoing is only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. a manufacture method for LTPS array base palte, is characterized in that, comprising:
One substrate is provided;
Form resilient coating, semiconductor figure layer and the first insulating barrier on the substrate successively;
Described first insulating barrier forms grid layer, and reduces described first insulating barrier not by the thickness of described gate patterns occlusion area;
Described grid layer forms the second insulating barrier and source-drain layer successively.
2. method according to claim 1, is characterized in that, described first insulating barrier forms grid layer, and reduces described first insulating barrier not by the step of the thickness of described gate patterns occlusion area, specifically comprises:
Make on described first insulating barrier, to define gate patterns with photoresist;
Etch process is adopted to form grid layer on described photoresist, adopt described etch process not etched by the region that described gate patterns blocks described first insulating barrier simultaneously, be not less than described first insulating barrier by described gate patterns occlusion area by the thickness of described gate patterns occlusion area to make described first insulating barrier.
3. method according to claim 1, is characterized in that, described grid layer is formed the step of the second insulating barrier and source-drain layer successively, specifically comprises:
Described grid layer is formed the second insulating barrier;
Described second insulating barrier and described first insulating barrier form the first through hole and the second through hole; Wherein, described first through hole and described second through hole all run through described first insulating barrier and described second insulating barrier;
Described second insulating barrier forms source electrode and drain electrode, and described source electrode and drain electrode are connected the two poles of the earth of described semiconductor figure layer with the second through hole respectively by described first through hole.
4. method according to claim 1, is characterized in that, forms the step of resilient coating, semiconductor figure layer and the first insulating barrier on the substrate successively, specifically comprises:
Form resilient coating on the substrate;
Described resilient coating is formed spaced first polysilicon layer and the second polysilicon layer;
N+ doping is carried out to described first polysilicon layer;
Described first polysilicon layer and the second polysilicon layer form the first insulating barrier.
5. method according to claim 4, is characterized in that, described first insulating barrier forms grid layer, and reduces described first insulating barrier not by the step of the thickness of described gate patterns occlusion area, specifically comprises:
Make on described first insulating barrier, to define first grid figure and second grid figure with photoresist; Wherein, described first grid figure and described second grid figure corresponding described first polysilicon layer and described second polysilicon layer respectively;
Adopt etch process on described photoresist, form first grid layer and second grid layer, adopt described etch process not etched by the region of described first grid figure and described second grid graph shealtering described first insulating barrier simultaneously, be not less than described first insulating barrier by described first grid figure and described second grid graph shealtering region by the thickness in described first grid figure and described second grid graph shealtering region to make described first insulating barrier.
6. method according to claim 4, is characterized in that, described first insulating barrier forms grid layer, and reduces described first insulating barrier not by after the step of the thickness of described gate patterns occlusion area, also comprises:
N-doping is carried out to described first polysilicon layer;
P+ doping is carried out to described second polysilicon layer.
7. method according to claim 6, is characterized in that,
Described first polysilicon layer is carried out to the step of N-doping, is specially:
The doping of phosphorus low dosage is carried out to described first polysilicon layer;
Described second polysilicon layer is carried out to the step of P+ doping, is specially:
Boron doping is carried out to described second polysilicon layer.
8. method according to claim 4, is characterized in that, described grid layer is formed the step of the second insulating barrier and source-drain layer successively, specifically comprises:
Described grid layer is formed the second insulating barrier;
Described second insulating barrier and described first insulating barrier are formed third through-hole, fourth hole, fifth hole and the 6th through hole; Wherein, described third through-hole, fourth hole, fifth hole and the 6th through hole all run through described first insulating barrier and described second insulating barrier;
Described second insulating barrier is formed the first source electrode, the first drain electrode, the second source electrode and the second drain electrode, described first source electrode and the first drain electrode are connected the two poles of the earth of described first polysilicon layer with fourth hole respectively by described third through-hole, described second source electrode and the second drain electrode are connected the two poles of the earth of described second polysilicon layer with the 6th through hole respectively by described fifth hole.
9. a LTPS array base palte, is characterized in that, comprising:
Substrate and the resilient coating, semiconductor figure layer, the first insulating barrier, grid layer, the second insulating barrier and the source-drain layer that are formed at successively on described substrate;
Wherein, the thickness described first insulating barrier not covering the region of described grid layer is less than the thickness described first insulating barrier covering the region of described grid layer.
10. a display unit, is characterized in that, described display unit comprises the array base palte as described in any one of claim 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510633394.9A CN105304470A (en) | 2015-09-29 | 2015-09-29 | LTPS array substrate, manufacturing method thereof and display device |
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| CN201510633394.9A CN105304470A (en) | 2015-09-29 | 2015-09-29 | LTPS array substrate, manufacturing method thereof and display device |
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| CN105304470A true CN105304470A (en) | 2016-02-03 |
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| CN201510633394.9A Pending CN105304470A (en) | 2015-09-29 | 2015-09-29 | LTPS array substrate, manufacturing method thereof and display device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1905165A (en) * | 2005-07-29 | 2007-01-31 | 株式会社半导体能源研究所 | Manufacturing method of semiconductor device |
| CN101840865A (en) * | 2010-05-12 | 2010-09-22 | 深圳丹邦投资集团有限公司 | Manufacturing method of thin film transistor and transistor manufactured by method |
| US20140295627A1 (en) * | 2013-03-29 | 2014-10-02 | Everdisplay Optronics (Shanghai) Limited | Method for adjusting the threshold voltage of ltps tft |
| US20140374718A1 (en) * | 2013-06-21 | 2014-12-25 | Everdisplay Optronics (Shanghai) Limited | Thin film transistor and active matrix organic light emitting diode assembly and method for manufacturing the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905165A (en) * | 2005-07-29 | 2007-01-31 | 株式会社半导体能源研究所 | Manufacturing method of semiconductor device |
| CN101840865A (en) * | 2010-05-12 | 2010-09-22 | 深圳丹邦投资集团有限公司 | Manufacturing method of thin film transistor and transistor manufactured by method |
| US20140295627A1 (en) * | 2013-03-29 | 2014-10-02 | Everdisplay Optronics (Shanghai) Limited | Method for adjusting the threshold voltage of ltps tft |
| US20140374718A1 (en) * | 2013-06-21 | 2014-12-25 | Everdisplay Optronics (Shanghai) Limited | Thin film transistor and active matrix organic light emitting diode assembly and method for manufacturing the same |
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