CN105261618A - Non-volatile memory unit - Google Patents
Non-volatile memory unit Download PDFInfo
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- CN105261618A CN105261618A CN201410240483.2A CN201410240483A CN105261618A CN 105261618 A CN105261618 A CN 105261618A CN 201410240483 A CN201410240483 A CN 201410240483A CN 105261618 A CN105261618 A CN 105261618A
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- 238000007667 floating Methods 0.000 claims abstract description 104
- 230000008878 coupling Effects 0.000 claims abstract description 22
- 238000010168 coupling process Methods 0.000 claims abstract description 22
- 238000005859 coupling reaction Methods 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims description 143
- 238000003860 storage Methods 0.000 claims description 67
- 239000004065 semiconductor Substances 0.000 claims description 60
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 11
- 229910052760 oxygen Inorganic materials 0.000 description 11
- 239000001301 oxygen Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 230000007850 degeneration Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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- Non-Volatile Memory (AREA)
Abstract
The invention discloses a non-volatile memory unit, which comprises a coupling component, a first selection transistor, a second selection transistor, a first floating gate transistor and a second floating gate transistor, wherein the coupling component is formed in a first conductive region; the first selection transistor is connected with the first floating gate transistor and the second selection transistor in series; the first selection transistor, the first floating gate transistor and the second selection transistor are formed in a second conductive region; the second floating gate transistor is formed in a third conductive region; the first conductive region, the second conductive region and the third conductive region are formed in a fourth conductive region; the first conductive region, the second conductive region and the third conductive region are wells; and the fourth conductive region is a deep well.
Description
Technical field
The present invention relates to one can repeatedly write memory unit, particularly a kind of based on logic control and can be compatible with general CMOS (Complementary Metal Oxide Semiconductor) processing procedure, can repeatedly write memory unit.
Background technology
Along with various different circuit unit is often integrated in the middle of single integrated circuit, the demand that nonvolatile storage location and logic circuit unit are integrated also is got over important.But the stack framework required on processing procedure of many nonvolatile storage locations is not compatible with traditional gate processing procedure, such as: only have single polycrystalline silicon layer and be absorbed in the manufacture of semiconductor of framework without special electric charge.
U.S. Patent number 7,382,658 (hereinafter ' 658), 7,391,647 (hereinafter ' 647), 7,263,001 (hereinafter ' 001), 7,423,903 (hereinafter ' 903), 7,209,392 (hereinafter ' 392) describe different memory cell architectures, and ' 658 describe a kind of P type access transistor sharing Floating gate with N-type metal-oxide-semiconductor (MOS) electric capacity.' 647 teach a kind of P type access transistor with P type gold oxygen half electric capacity and N-type gold oxygen half electric capacity.' 001 teaches a kind of P type access transistor sharing Floating gate with two P types gold oxygen half electric capacity.' 903 teach a kind of in order to via channel hot electron beam to write the P type field-effect transistor of content, and a kind of in order to the N-type field-effect transistor via the tunneling content of erasing of Memory windows.' 392 teach a kind of N-type metal-oxide half field effect transistor sharing Floating gate with P type metal-oxide half field effect transistor, and wherein each transistor all couples mutually with respective access transistor.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of ' 392 nonvolatile storage locations introduced.Nonvolatile storage location in Fig. 1 comprises a P type MOS (metal-oxide-semiconductor) transistor T
1, the 2nd P type MOS (metal-oxide-semiconductor) transistor T
2, the first N-type MOS (metal-oxide-semiconductor) transistor T
3and the second N-type MOS (metal-oxide-semiconductor) transistor T
4.One P type MOS (metal-oxide-semiconductor) transistor T
1with the first N-type MOS (metal-oxide-semiconductor) transistor T
3by control voltage V
sGcontrolled, in order to respectively as the 2nd P type MOS (metal-oxide-semiconductor) transistor T
2with the second N-type MOS (metal-oxide-semiconductor) transistor T
4access transistor.One P type MOS (metal-oxide-semiconductor) transistor T
1input and the first N-type MOS (metal-oxide-semiconductor) transistor T
3input receive and select line voltage V
sL, and the 2nd P type MOS (metal-oxide-semiconductor) transistor T
2input and the second N-type MOS (metal-oxide-semiconductor) transistor T
4input then receive the first bitline voltage V respectively
bL1and the second bitline voltage V
bL2.Second N-type MOS (metal-oxide-semiconductor) transistor T
4with the 2nd P type MOS (metal-oxide-semiconductor) transistor T
2share Floating gate.
Summary of the invention
One embodiment of the invention provide a kind of nonvolatile storage location.Nonvolatile storage location comprises coupling assembly, first and selects transistor, second to select transistor, the first Floating gate transistor and the second Floating gate transistor.Coupling assembly is formed in the first conductive region.First selects transistor to be select transistor series connection with the first Floating gate transistor and second, and first selects transistor, the first Floating gate transistor and the second selection transistor to be formed in the second conductive region.Second Floating gate transistor is formed in the 3rd conductive region, and the first conductive region, the second conductive region and the 3rd conductive region are formed in the 4th conductive region.The grid of the first Floating gate transistor, the grid of the second Floating gate transistor and the electrode of coupling assembly are all the single Floating gate formed by polysilicon.First conductive region, the second conductive region and the 3rd conductive region are well, and the 4th conductive region is deep-well, and the 3rd conductive region is around the first conductive region and the second conductive region.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the nonvolatile storage location of prior art.
Fig. 2 is the schematic diagram of the nonvolatile storage location of one embodiment of the invention.
Fig. 3 is the line map of Fig. 2 nonvolatile storage location.
Fig. 4 illustrates the write of Fig. 2 and Fig. 3 nonvolatile storage location in one embodiment of the invention, the voltage arrangement of write of erasing, read, forbid.
Fig. 5 is the oscillogram of forbidding write operation of Fig. 2 and Fig. 3 nonvolatile storage location.
Fig. 6 is the schematic diagram of the nonvolatile storage location of another embodiment of the present invention.
Fig. 7 is the line map of Fig. 6 nonvolatile storage location.
Fig. 8 illustrates the write of Fig. 6 and Fig. 7 nonvolatile storage location in another embodiment of the present invention, the voltage arrangement of write of erasing, read, forbid.
Fig. 9 is the oscillogram of forbidding write operation of Fig. 6 and Fig. 7 nonvolatile storage location.
Figure 10 is the schematic diagram of the nonvolatile storage location of another embodiment of the present invention.
Figure 11 is the line map of Figure 10 nonvolatile storage location.
Figure 12 A-12D is the profile of Figure 10 nonvolatile storage location respectively linearly A-A ', B-B ', C-C ' and D-D ' cutting.
Figure 13 illustrates the write of Figure 10 and Figure 11 nonvolatile storage location in another embodiment of the present invention, the voltage arrangement of write of erasing, read, forbid.
Figure 14 is the oscillogram of forbidding write operation of Figure 10 and Figure 11 nonvolatile storage location.
Wherein, description of reference numerals is as follows:
T
1one P type MOS (metal-oxide-semiconductor) transistor
T
22nd P type MOS (metal-oxide-semiconductor) transistor
T
3first N-type MOS (metal-oxide-semiconductor) transistor
T
4second N-type MOS (metal-oxide-semiconductor) transistor
NMOSN type MOS (metal-oxide-semiconductor) transistor
PMOSP type MOS (metal-oxide-semiconductor) transistor
V
sGcontrol voltage
V
sLselect line voltage
V
bL1first bitline voltage
V
bL2second bitline voltage
40,90,110 nonvolatile storage locations
400,900,1100, FG Floating gate
401,901,1101 first grid portions
402,902,1102 second grid portions
421,921,1,121 first diffusion regions
422,922,1,122 second diffusion regions
461,961,1161 the 3rd diffusion regions
462,962,1162 the 4th diffusion regions
463,963,1163 the 5th diffusion regions
464,964,1164 the 6th diffusion regions
481,981,1181 the 7th diffusion regions
482,982,1182 the 8th diffusion regions
471,971,1171, WL character line
472,972,1172, SG grid selects line
CL control line
SL source electrode line
BL bit line
EL erases line
NW, 930N wellblock
PW, PW1, PW2, PW3P wellblock
500,1000,1200 coupling assemblies
510 first N-type MOS (metal-oxide-semiconductor) transistor
520P type MOS (metal-oxide-semiconductor) transistor
530 second N-type MOS (metal-oxide-semiconductor) transistor
540 the 3rd N-type MOS (metal-oxide-semiconductor) transistor
T1 first time point
T2 second time point
T3 the 3rd time point
T4 the 4th time point
T5 the 5th time point
T6 the 6th time point
V1 first voltage
V2 second voltage
V3 tertiary voltage
V4 the 4th voltage
V5 the 5th voltage
V6 the 6th voltage
1010,1,210 first Floating gate transistors
1020,1,220 second Floating gate transistors
1030,1,230 first transistor is selected
1040,1,240 second transistor is selected
1130, DNWN type deep well area
The substrate of 120P type
AA ', BB ', CC ', DD ' straight line
STI shallow channel isolation layer
Embodiment
Please refer to Fig. 2 and Fig. 3.Fig. 2 is the schematic diagram of the nonvolatile storage location 40 of the embodiment of the present invention, and nonvolatile storage location 40, when its neighbor memory cell writes, has the stronger ability of forbidding writing.Fig. 3 is the line map of Fig. 2 nonvolatile storage location 40.The nonvolatile storage location 40 of Fig. 2 can be formed in substrate or in substrate, and this substrate can be P type or N-type.Nonvolatile storage location 40 comprises Floating gate (FG) 400, character line (WL) 471, grid selection line (SG) 472, control line (CL), source electrode line (SL), bit line (BL) and line of erasing (EL), and selects making for strengthening aforementioned ability of forbidding writing of line (SG) 472 through grid.To use the substrate of P type, it is formed on first conductive region with the first conductivity, as a N wellblock that nonvolatile storage location 40 separately can comprise the first diffusion region 421 and the second diffusion region, diffusion region 422, first 421 and the second diffusion region 422.3rd diffusion region 461, the 4th diffusion region 462, the 5th diffusion region 463 and the 6th diffusion region 464 can be formed on second conductive region with the second conductivity, as a P wellblock.7th diffusion region 481 and the 8th diffusion region 482 can be formed, as another N wellblock on the 3rd conductive region with the first conductivity.Second conductive region can be arranged between the first conductive region and the 3rd conductive region, and namely P wellblock can be arranged between two N wellblocks.In another embodiment of the present invention, the first conductive region is the second conductivity, and the 3rd conductive region is arranged between the first conductive region and the second conductive region.Floating gate (FG) 400 can comprise first grid portion 401 and second grid portion 402.Part I is formed between the first diffusion region 421 and the second diffusion region 422, and second grid portion 402 is formed between the 4th diffusion region 462 and the 5th diffusion region 463, and extend between the 7th diffusion region 481 and the 8th diffusion region 482.The polysilicon that first grid portion 401 and second grid portion 402 can be same layer is formed, and can be connected with each other.The area in first grid portion 401 is large compared with the area in second grid portion 402.Character line (WL) 471 and grid select line (SG) 472 can form by with the polysilicon of Floating gate (FG) 400 with layer.Character line (WL) 471 can be formed between the 3rd diffusion region 461 and the 4th diffusion region 462, and grid selects line (SG) 472 can be formed between the 5th diffusion region 463 and the 6th diffusion region 464.First diffusion region 421 and the second diffusion region 422 can be N+ diffusion region.3rd diffusion region 461, the 4th diffusion region 462, the 5th diffusion region 463 and the 6th diffusion region 464 can be N+ diffusion region.7th diffusion region 481 and the 8th diffusion region 482 can be P+ diffusion region.Nonvolatile storage location 40 can utilize the CMOS processing procedure of single level polysilicon to manufacture.
Please refer to Fig. 2 and Fig. 3.Coupling assembly 500 can be golden oxygen half electric capacity that is made up of first grid portion 401 and control line (CL) or metal-oxide half field effect transistor.Second grid portion 402 can form the first N-type MOS (metal-oxide-semiconductor) transistor 510 jointly with the 4th diffusion region 462 and the 5th diffusion region 463 being all N+ diffusion region, and jointly forms P type MOS (metal-oxide-semiconductor) transistor 520 with the 7th diffusion region 481 and the 8th diffusion region 482.Character line (WL) 471 can form the second N-type MOS (metal-oxide-semiconductor) transistor 530 jointly with the 3rd diffusion region 461 and the 4th diffusion region 462 being all N+ diffusion region, and grid selects line (SG) 472 jointly can form the 3rd N-type MOS (metal-oxide-semiconductor) transistor 540 with the 5th diffusion region 463 and the 6th diffusion region 464 being all N+ diffusion region.Source electrode line (SL) can be electrically connected with the 3rd diffusion region 461, and the 3rd diffusion region 461 can be the source electrode of the second N-type MOS (metal-oxide-semiconductor) transistor 530.Bit line (BL) can be electrically connected with the 6th diffusion region 464, and the 6th diffusion region 464 can be the drain of the 3rd N-type MOS (metal-oxide-semiconductor) transistor 540.Line (EL) of erasing can be electrically connected with the 7th diffusion region 481 of P type MOS (metal-oxide-semiconductor) transistor 520 and the 8th diffusion region 482.4th diffusion region 462 can simultaneously as the source electrode of the first N-type MOS (metal-oxide-semiconductor) transistor 510 and the drain of the second N-type MOS (metal-oxide-semiconductor) transistor 530.5th diffusion region 463 can simultaneously as the drain of the first N-type MOS (metal-oxide-semiconductor) transistor 510 and the source electrode of the 3rd N-type MOS (metal-oxide-semiconductor) transistor 540.First N-type MOS (metal-oxide-semiconductor) transistor 510 and P type MOS (metal-oxide-semiconductor) transistor 520 can respectively as the first Floating gate transistor and the second Floating gate transistors, and the second N-type MOS (metal-oxide-semiconductor) transistor 530 and the 3rd N-type MOS (metal-oxide-semiconductor) transistor 540 can select transistor and second to select transistor as first respectively.In another embodiment of the present invention, the second Floating gate transistor can be made up of golden oxygen half electric capacity.
Fig. 4 describes the voltage arrangement in writing, erase, read, when forbidding write operation of Fig. 2 and Fig. 3 nonvolatile storage location 40 in one embodiment of the invention.When write operation, control line voltage between the scope of 5 volts to 20 volts can be bestowed on control line (CL) and line of erasing (EL).Select line (SG) can bestow the first control voltage in grid, the first control voltage can between the scope of 1 volt to 5 volts.Source electrode line (SL), bit line (BL) and P wellblock (PW) can be ground connection.Character line (WL) can scope between 0 volt to 5 volts.Under the voltage of above-mentioned write operation arranges, control line voltage can come via golden oxygen half electric capacity 500 and according to the area ratio of golden oxygen half electric capacity and the first N-type MOS (metal-oxide-semiconductor) transistor 510 and Floating gate 400 couples mutually.For example, if control line voltage is 6 volts and the area ratio of golden oxygen half electric capacity and the first N-type MOS (metal-oxide-semiconductor) transistor 510 is 9:1, then the current potential of Floating gate 400 is 5.4 volts (9/10ths of 6 volts).When write operation, can there is electrons tunnel and inject in the first N-type MOS (metal-oxide-semiconductor) transistor 510.And when erase operation for use, when voltage of erasing imposes on line of erasing (EL), and control line (CL), source electrode line (SL), bit line (BL) and P wellblock (PW) are when being for ground connection, can there is electrons tunnel injection in P type MOS (metal-oxide-semiconductor) transistor 520.Character line (WL) and grid selection line (SG) can between the scopes of 0 volt to 5 volts, and voltage of erasing can between the scope of 5 volts to 20 volts.Thus, the electronics injecting Floating gate 400 when write operation can when erase operation for use from the tunneling injection of Floating gate 400.
When read operation, the first control voltage can be bestowed on control line (CL) and line of erasing (EL), select the second control voltage bestowed by line (SG) in character line (WL) and grid, and bestow reading voltage on bit line (BL).Second control voltage and reading voltage can between the scopes of 1 volt to 5 volts.First control voltage can between the scope of 5 volts of 0 volt.Source electrode line (SL) and P wellblock (PW) can be ground connection.Couple through the capacitive character with golden oxygen half electric capacity, the first control voltage of part, as first control voltage of 9/10ths, will be coupled to Floating gate 400.If not volatile storage 40 is erased, then the current potential of Floating gate 400 can be enough to conducting first N-type MOS (metal-oxide-semiconductor) transistor 510.Put on that bit line (BL) is upper and source electrode line (SL) is ground connection owing to reading voltage, read electric current and can flow through the first N-type MOS (metal-oxide-semiconductor) transistor 510.The reading electric current be now detected can be expressed as high potential logic state.If non-volatility memorizer 40 is written into, the part that the electronics being then injected into Floating gate 400 can be enough to the first control voltage to be coupled to Floating gate 400 offsets, or reduce at least in large quantities, thus, first N-type MOS (metal-oxide-semiconductor) transistor 510 can maintain cut-off state, or the electric current that only the conduction ratio reading electric current that can be detected when non-volatility memorizer 40 erases is much smaller.Now be detected less reading electric current and can be expressed as electronegative potential logic state.In another embodiment of the present invention, higher reading electric current also can be mapped to electronegative potential logic state, and lower reading electric current then can be mapped to high logic level.
Please refer to Fig. 5, Fig. 5 is the oscillogram of forbidding write operation of Fig. 2 and Fig. 3 nonvolatile storage location.The mode chart of Fig. 5 describes during forbidding write operation, impose on the control line voltage of control line (CL), impose on the word line voltages on character line (WL), imposing on grid selects the grid on line (SG) to select line voltage, impose on the line voltage of erasing on line of erasing (EL), impose on the bitline voltage on bit line (BL), impose on the source line voltage on source electrode line (SL), impose on the P trap zone voltage of P wellblock (PW), and in the 3rd time point t3 and the 4th time point t4 the channel voltage of the first N-type MOS (metal-oxide-semiconductor) transistor 510 of lifting.As shown in Figure 5, from the second time point t2 to the period of the 3rd time point t3 in, channel voltage is raised to the 6th voltage V6.From the 3rd time point t3 to the period of the 4th time point t4 in, control line voltage is the first voltage V1, and grid selects line voltage to be the second voltage V2, and line voltage of erasing is tertiary voltage V3, bitline voltage is the 4th voltage V4, and channel voltage is the 5th voltage V5.During forbidding write operation, the magnitude relationship of the first voltage V1 to the 6th voltage V6 can be V1 >=V3>V5>V4 >=V2>V6.Magnitude relationship in write operation period first voltage V1 to the 6th voltage V6 can be V1 >=V3 >=V2>V4=V5=V6 >=0V.For example, as shown in Figure 4, during forbidding write operation, control line voltage can between the scope of 5 volts to 20 volts, word line voltages can between the scope of 5 volts of 0 volt, grid selection line voltage can between the scope of 5 volts of 1 volt, erasing line voltage can between the scope of 5 volts to 20 volts, bitline voltage can between the scope of 1 volt to 5 volts, source line voltage can between the scope of 0 volt to 5 volts, and P trap zone voltage can be 0 volt.
Above-mentioned nonvolatile storage location 40 can be completely compatible with general CMOS processing procedure, and only need relatively little assembly layout area can realize good write and speed of erasing, durability and data keeping quality, and without the cycle-index of degeneration memory.
Please refer to Fig. 6 and Fig. 7.Fig. 6 is the schematic diagram of the nonvolatile storage location 90 of another embodiment of the present invention, and Fig. 7 is the line map of Fig. 6 nonvolatile storage location 90.Nonvolatile storage location 90 comprises Floating gate 900, character line (WL) 971, grid selection line (SG) 972, control line (CL), source electrode line (SL), bit line (BL) and line of erasing (EL), and grid can be utilized to select line (SG) 972 to make it when neighbor memory cell writes, strengthen the function forbidding writing.For P type (the first conductivity) substrate, that is nonvolatile storage location 90 is that N wellblock 930 is then form in the substrate of P type in N wellblock 930 (having the 3rd conductive region of the second conductivity) composition.Nonvolatile storage location 90 is separately contained in the first diffusion region 921 and the second diffusion region 922 formed in first conductive region (P wellblock PW1) with the first conductivity.3rd diffusion region 961, the 4th diffusion region 962, the 5th diffusion region 963 and the 6th diffusion region 964 can be formed in second conductive region (P wellblock PW2) with the first conductivity.7th diffusion region 981 and the 8th diffusion region 982 can be formed in the 4th conductive region (P wellblock PW3) with the first conductivity.Second conductive region (P wellblock PW2) can be arranged between the first conductive region (P wellblock PW1) and the 4th conductive region (P wellblock PW3).Floating gate (FG) 900 comprises first grid portion 901 and second grid portion 902.First grid portion 901 is formed between the first diffusion region 921 and the second diffusion region 922, and second grid portion 902 is formed between the 4th diffusion region 962 and the 5th diffusion region 963, and extends between the 7th diffusion region 981 and the 8th diffusion region 982.First grid portion 901 and second grid portion 902 are made up of the polysilicon of same layer, and can be connected with each other.The area in first grid portion 901 is large compared with the area in second grid portion 902.Character line (WL) 971 can be formed between the 3rd diffusion region 961 and the 4th diffusion region 962, and grid selects line (SG) 972 to be formed between the 5th diffusion region 963 and the 6th diffusion region 964.First diffusion region 921 and the second diffusion region 922 have the second conductivity.3rd diffusion region 961, the 4th diffusion region 962, the 5th diffusion region 963 and the 6th diffusion region 964 also all have the second conductivity.7th diffusion region 981 and the 8th diffusion region 982 also all have the second conductivity.Nonvolatile storage location 90 can utilize the CMOS processing procedure of single level polysilicon to manufacture.In addition, in another embodiment of the invention, the first conductivity is N-type, and the second conductivity is then P type.
Please refer to Fig. 6 and Fig. 7.Coupling assembly 1000 can be golden oxygen half electric capacity that is made up of first grid portion 901 and control line (CL) or metal-oxide half field effect transistor.Second grid portion 902 can form the first Floating gate transistor 1010 (N-type MOS (metal-oxide-semiconductor) transistor) jointly with the 4th diffusion region 962 and the 5th diffusion region 963, and jointly forms the second Floating gate transistor 1020 (N-type MOS (metal-oxide-semiconductor) transistor) with the 7th diffusion region 981 and the 8th diffusion region 982.Character line (WL) 971 can forming first selects transistor 1030 (N-type MOS (metal-oxide-semiconductor) transistor) jointly with the 3rd diffusion region 961 and the 4th diffusion region 962.Grid selects that line (SG) 972 can forming second selects transistor 1040 (N-type MOS (metal-oxide-semiconductor) transistor) jointly with the 5th diffusion region 963 and the 6th diffusion region 964.Source electrode line (SL) can be electrically connected with the 3rd diffusion region 961, and the 3rd diffusion region 961 can be the source electrode of the first selection transistor 1030.Bit line BL can be electrically connected with the 6th diffusion region 964, and the 6th diffusion region 964 can be the drain of the second selection transistor 1040.Line (EL) of erasing can be electrically connected with the 7th diffusion region 981 of the second Floating gate transistor 1020 and the 8th diffusion region 982.4th diffusion region 962 can simultaneously as the source electrode of the first Floating gate transistor 1010 and the drain of the first selection transistor 1030.5th diffusion region 963 can simultaneously as the drain of the first Floating gate transistor 1010 and the source electrode of the second selection transistor 1040.In another embodiment of the present invention, the second Floating gate transistor 1020 can be made up of golden oxygen half electric capacity.
Fig. 8 illustrates the voltage arrangement in writing, erase, read, when forbidding write operation of Fig. 6 and Fig. 7 nonvolatile storage location 90 in one embodiment of the invention.When write operation, in the upper control line voltage applied between the scope of 5 volts to 20 volts of control line (CL), apply the first well voltage identical with control line voltage in the first conductive region (P wellblock PW1) is upper, source electrode line (SL), bit line (BL) and the second conductive region (P wellblock PW2) can be ground connection.Character line (WL) voltage can scope between 0 volt to 5 volts.In the upper line voltage of erasing applied between the scope of 5 volts to 20 volts of line of erasing (EL), apply the four well voltage identical with line voltage of erasing in the 4th conductive region (P wellblock PW3) is upper, select the upper grid applied between 1 volt to 5 volts of line (SG) to select line voltage in grid.In addition, the Mitsui voltage between the scope of 5 volts to 20 volts is applied in N wellblock 930 (the 3rd conductive region).Under the voltage of above-mentioned write operation arranges, control line voltage can come via coupling assembly 1000 and according to the area ratio of coupling assembly 1000 and the first Floating gate transistor 1010 and Floating gate 900 couples mutually.For example, if control line voltage is 10 volts and coupling assembly 1000 is 9:1 with the area ratio of Floating gate transistor 1010, then the current potential of Floating gate 900 is 9 volts (9/10ths of 10 volts).When write operation, the first Floating gate transistor 1010 can produce electrons tunnel and inject, and electronics can inject Floating gate 900 via the first Floating gate transistor 1010 thus.
When erase operation for use, in the upper word line voltages applied between 0 volt to 5 volts of character line (WL), and control line (CL), the first conductive region (P wellblock PW1), source electrode line (SL), bit line (BL) and the second conductive region (P wellblock PW2) are ground connection.The upper grid applied between 0 volt to 5 volts of line (SG) is selected to select line voltage in grid.In the upper line voltage of erasing applied between 5 volts to 20 volts of line of erasing (EL), and apply the four well voltage equal with line voltage of erasing in the 4th conductive region (P wellblock PW3).In addition, Mitsui voltage between 5 volts to 20 volts is applied in N wellblock 930 (the 3rd conductive region) to avoid generation first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) and the forward bias voltage drop between the 4th conductive region (P wellblock PW3) and N wellblock 930.When erase operation for use, in line of erasing (EL) and the upper voltage of erasing applied between 5 volts to 20 volts of the 4th conductive region (P wellblock PW3), now the second Floating gate transistor 1020 can produce electrons tunnel injection.Thus, the electronics left on Floating gate 900 can from the tunneling injection of Floating gate 900.
When read operation, in the upper control line voltage applied between 0 volt to 5 volts of control line (CL), in the upper word line voltages applied between 1 volt to 5 volts of character line (WL), the upper grid applied between 1 volt to 5 volts of line (SG) is selected to select line voltage, in the upper bitline voltage applied between 1 volt to 5 volts of bit line (BL) in grid.In addition, the first well voltage identical with control line voltage is applied in the first conductive region (P wellblock PW1).Source electrode line (SL) and the second conductive region (P wellblock PW2) can be ground connection.In the upper line voltage of erasing applied between 0 volt to 5 volts of line of erasing (EL), the 4th well voltage wherein putting on the 4th conductive region (P wellblock PW3) is identical with line voltage of erasing.In addition, Mitsui voltage between 0 volt to 5 volts is applied in N wellblock 930 (the 3rd conductive region) to avoid generation first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) and the forward bias voltage drop between the 4th conductive region (P wellblock PW3) and N wellblock 930.Couple through the capacitive character with coupling assembly 1000, part, as 9/10ths, control line voltage, will be coupled to Floating gate 900.If not volatile storage 90 is erased, then the current potential of Floating gate 900 can be enough to conducting first Floating gate transistor 1010.Because bitline voltage puts on that bit line (BL) is upper and source electrode line (SL) and the second conductive region (P wellblock PW2) are all ground connection, read electric current and can flow through the first Floating gate transistor 1010.Now be detected larger reading electric current and can be expressed as high potential logic state.If non-volatility memorizer 90 is written into, the electronics being then injected into Floating gate 900 can be enough to partial offset control line voltage (VCL) being coupled to Floating gate 900, or reduce at least in large quantities, thus, first Floating gate transistor 1010 can maintain cut-off state, or the electric current that only the conduction ratio reading electric current that can be detected when non-volatility memorizer 90 erases is much smaller.And be now detected less reading electric current and can be expressed as electronegative potential logic state.Above-mentioned by larger reading current judgement be high potential logic state and by less reading current judgement be electronegative potential logic state be only one embodiment of the invention and and be not used to limit the present invention.In other embodiments, larger reading electric current also can be mapped to electronegative potential logic state, and less reading electric current then can be mapped to high logic level.
Please refer to Fig. 9, Fig. 9 is the oscillogram of forbidding write operation of Fig. 6 and Fig. 7 nonvolatile storage location 90.The mode chart of Fig. 9 describes during forbidding write operation, impose on the control line voltage of control line (CL), impose on the word line voltages on character line (WL), imposing on grid selects the grid on line (SG) to select line voltage, impose on the line voltage of erasing on line of erasing (EL), impose on the bitline voltage on bit line (BL), impose on the source line voltage on source electrode line (SL), impose on the second well voltage of the second conductive region (P wellblock PW2), impose on the Mitsui voltage of N wellblock 930, and from the 3rd time point t3 to the channel voltage of the first Floating gate transistor 1010 of lifting in the period of the 4th time point t4.The the first well voltage wherein imposing on the first conductive region (P wellblock PW1) is equal with control line voltage, and the 4th well voltage imposing on the 4th conductive region (P wellblock PW3) is equal with line voltage of erasing.As shown in Figure 9, in from the second time point t2 to the period of the 3rd time point t3, channel voltage has been lifted to the 6th voltage V6.In from the 3rd time point t3 to the period of the 4th time point t4, control line voltage is the first voltage V1, and grid selects line voltage to be the second voltage V2, and line voltage of erasing is tertiary voltage V3, bitline voltage is the 4th voltage V4, and channel voltage is the 5th voltage V5.During forbidding write operation, the magnitude relationship of the first voltage V1 to the 6th voltage V6 can be V1 >=V3>V5>V4 >=V2>V6.During write operation, the magnitude relationship of the first voltage V1 to the 6th voltage V6 can be V1 >=V3 >=V2>V4=V5=V6 >=0V.For example, as shown in Figure 8, during forbidding write operation, control line voltage can between the scope of 5 volts to 20 volts, word line voltages can between the scope of 0 volt to 5 volts, grid selection line voltage can between the scope of 1 volt to 5 volts, erasing line voltage can between the scope of 5 volts to 20 volts, bitline voltage can between the scope of 1 volt to 5 volts, source line voltage can between the scope of 0 volt to 5 volts, 4th well voltage can between the scope of 5 volts to 20 volts, and the second well voltage imposing on the second conductive region (P wellblock PW2) can be 0 volt.
Please refer to Fig. 6, although nonvolatile storage location 90 can be applicable in the middle of embedded system, but because the second conductive region (P wellblock PW2) is arranged between the first conductive region (P wellblock PW1) and the 4th conductive region (P wellblock PW3), therefore nonvolatile storage location 90 also needs more chip area to reach set process design specification.
Please refer to Figure 10 and Figure 11.Figure 10 is the schematic diagram of the nonvolatile storage location 110 of another embodiment of the present invention, and Figure 11 is the line map of Figure 10 nonvolatile storage location 110.The nonvolatile storage location 110 of Figure 10 comprises Floating gate (FG) 1100, character line (WL) 1171, grid selection line (SG) 1172, control line (CL), source electrode line (SL), bit line (BL) and line of erasing (EL), and select line (SG) 1172 to make it when neighbor memory cell writes through grid, the function forbidding writing can be strengthened.For P type (the first conductivity) substrate 120, that is, nonvolatile storage location 110 is middle compositions in N-type deep-well district 1130 (having the 4th conductive region of the second conductivity), and N-type deep-well district 1130 forms in P type substrate 120.Nonvolatile storage location 110 separately can be contained in upper the first diffusion region 1121 and the second diffusion region 1122 formed of first conductive region (P wellblock PW1) with the first conductivity.3rd diffusion region 1161, the 4th diffusion region 1162, the 5th diffusion region 1163 and the 6th diffusion region 1164 can above in second conductive region (P wellblock PW2) with the first conductivity be formed.7th diffusion region 1181 and the 8th diffusion region 1182 can above in the 3rd conductive region (N wellblock NW) with the second conductivity be formed.3rd conductive region (N wellblock NW) is centered around around the first conductive region (P wellblock PW1) and the second conductive region (P wellblock PW2).Floating gate (FG) 1100 can comprise first grid portion 1101 and second grid portion 1102.First grid portion 1101 is formed between the first diffusion region 1121 and the second diffusion region 1122, and second grid portion 1102 is formed between the 4th diffusion region 1162 and the 5th diffusion 1163rd district, and also between the 7th diffusion region 1181 and the 8th diffusion region 1182.First grid portion 1101 and second grid portion 1102 are made up of the polysilicon of same layer, and can be connected with each other.The area in first grid portion 1101 is large compared with the area in second grid portion 1102.Character line (WL) 1171 and grid select line (SG) 1172 can form by with the polysilicon of Floating gate (FG) 1100 with layer.Character line (WL) 1171 can be formed between the 3rd diffusion region 1161 and the 4th diffusion region 1162, and grid selects line (SG) 1172 can be formed between the 5th diffusion region 1163 and the 6th diffusion region 1164.First diffusion region 1121 and the second diffusion region 1122 have the second conductivity.3rd diffusion region 1161, the 4th diffusion region 1162, the 5th diffusion region 1163 and the 6th diffusion region 1164 also have the second conductivity.And the 7th diffusion region 1181 and the 8th diffusion region 1182 have the first conductivity.Nonvolatile storage location 110 can utilize the CMOS processing procedure of single level polysilicon to manufacture.And the first conductivity can be P type, the second conductivity can be N-type.
Please refer to Figure 10 and Figure 11.Coupling assembly 1200 can be golden oxygen half electric capacity that is made up of first grid portion 1101 and control line (CL) or metal-oxide half field effect transistor.Second grid portion 1102 can form the first Floating gate transistor 1210 (N-type MOS (metal-oxide-semiconductor) transistor) jointly with the 4th diffusion region 1162 and the 5th diffusion region 1163, and jointly can form the second Floating gate transistor 1220 (P type MOS (metal-oxide-semiconductor) transistor) with the 7th diffusion region 1181 and the 8th diffusion region 1182, and the second Floating gate transistor 1220 can be golden oxygen half electric capacity or metal-oxide half field effect transistor.In addition, as shown in figure 11, character line (WL) 1171 can forming first selects transistor 1230 (N-type MOS (metal-oxide-semiconductor) transistor) jointly with the 3rd diffusion region 1161 and the 4th diffusion region 1162.Grid selects that line (SG) 1172 can forming second selects transistor (N-type MOS (metal-oxide-semiconductor) transistor) 1240 jointly with the 5th diffusion region 1163 and the 6th diffusion region 1164.And the first Floating gate transistor 1210 selects transistor 1230 and second to select between transistor 1240 between first.Source electrode line (SL) can be electrically connected with the 3rd diffusion region 1161, and the 3rd diffusion region 1161 can be used as the source electrode of the first selection transistor 1230.Bit line (BL) can be electrically connected with the 6th diffusion region 1164, and the 6th diffusion region 1164 can be the drain of the second selection transistor 1240.Line (EL) of erasing can be electrically connected with the 7th diffusion region 1181 of the second Floating gate transistor 1220 and the 8th diffusion region 1182.4th diffusion region 1162 can simultaneously as the source electrode of the first Floating gate transistor 1210 and the drain of the first selection transistor 1230.5th diffusion region 1163 can simultaneously as the drain of the first Floating gate transistor 1210 and the source electrode of the second selection transistor 1240.In another embodiment of the present invention, the second Floating gate transistor 1220 device can be made up of golden oxygen half electric capacity.
Please refer to Figure 12 A-12D, Figure 12 A-12D is the profile of Figure 10 nonvolatile storage location 110 respectively linearly A-A ', B-B ', C-C ' and D-D ' cutting.As shown in fig. s 12a through 12d, 3rd conductive region (N wellblock NW) is around the first conductive region (P wellblock PW1) and the second conductive region (P wellblock PW2), and the first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) and the 3rd conductive region (N wellblock NW) are all form in the 4th conductive region 1130.And the first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) and the 3rd conductive region (N wellblock NW) are well structure, and the 4th conductive region 1130 is deep-well structure.In addition, the shallow channel isolation layer STI shown in Figure 12 A-12D is shallow trench isolation (shallowtrenchisolation).
Figure 13 illustrate Figure 10 and Figure 11 nonvolatile storage location 110 write, erase, read, voltage arrangement when forbidding write operation.When write operation, control line voltage between the scope of 5 volts to 20 volts is applied in control line (CL), apply the first well voltage identical with control line voltage in the first conductive region (P wellblock PW1), source electrode line (SL), bit line (BL) and the second conductive region (PW2) can be ground connection.Word line voltages can scope between 0 volt to 5 volts.The line voltage of erasing between the scope of 5 volts to 20 volts is applied in line of erasing (EL), apply the Mitsui voltage identical with line voltage of erasing in the 3rd conductive region (NW), the grid selecting line (SG) to apply between 1 volt to 5 volts in grid selects line voltage.In addition, the 4th well voltage between 5 volts to 20 volts is applied, to avoid generation first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) or the forward bias voltage drop between the 3rd conductive region and N-type deep-well district 1130 in N-type deep-well district 1130 (the 4th conductive region).Under the arrangement of above-mentioned write voltage, control line voltage can to couple according to the area ratio of coupling assembly 1200 and the first Floating gate transistor 1210 and Floating gate 1100 mutually via coupling assembly 1200.For example, if control line voltage is 10 volts and the area ratio of coupling assembly 1200 and the first Floating gate transistor 1210 is 9:1, then the current potential of Floating gate 1100 is 9 volts (9/10ths of 10 volts).When write operation, the first Floating gate transistor 1210 can produce electrons tunnel and inject, and electronics can inject Floating gate 1100 via the first Floating gate transistor 1210 thus.
When erase operation for use, in the upper word line voltages applied between 0 volt to 5 volts of character line (WL).Control line, the first conductive region (P wellblock PW1), source electrode line (SL), bit line (BL) and the second conductive region (P wellblock PW2) are ground connection.The upper grid applied between 0 volt to 5 volts of line (SG) is selected to select line voltage in grid.In the upper line voltage of erasing applied between 5 volts to 20 volts of line of erasing (EL), and apply the Mitsui voltage equal with line voltage of erasing in the 3rd conductive region (N wellblock NW).In addition, the 4th well voltage between 5 volts to 20 volts is applied in N-type deep-well district 1130 (the 4th conductive region) to avoid generation first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) or the forward bias voltage drop between the 3rd conductive region and N-type deep-well district 1130.When erase operation for use, when erasing voltage in line of erasing (EL) and the upper applying of the 3rd conductive region (N wellblock NW), can there is electrons tunnel injection in the second Floating gate transistor 1220.Thus, the electronics left on Floating gate 1100 can penetrate from Floating gate 1100.
When read operation, in the upper control line voltage applied between 0 volt to 5 volts of control line (CL), in the upper word line voltages applied between 1 volt to 5 volts of character line (WL), the upper grid applied between 1 volt to 5 volts of line (SG) is selected to select line voltage in grid, in the upper bitline voltage applied between 1 volt to 5 volts of bit line (BL), and apply the first well voltage identical with control line voltage in the first conductive region (P wellblock PW1).Source electrode line (SL) and the second conductive region (P wellblock PW2) can be ground connection.In the upper line voltage of erasing applied between 0 volt to 5 volts of line of erasing (EL), the Mitsui voltage wherein putting on the 3rd conductive region (N wellblock NW) is identical with line voltage of erasing.In addition, the 4th well voltage between 0 volt to 5 volts is applied in N-type deep-well district 1130 (the 4th conductive region) to avoid generation first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) or the forward bias voltage drop between the 3rd conductive region and N-type deep-well district 1130.Couple through the capacitive character with coupling assembly 1200, the control line voltage of part, as the control line voltage of 9/10ths, will be coupled to Floating gate 1100.If not volatile storage 110 is erased, then the current potential of Floating gate 1100 can be enough to conducting first Floating gate transistor 1210.Because bitline voltage puts on that bit line (BL) is upper and source electrode line (SL) and the second conductive region (P wellblock PW2) are all ground connection, read electric current and can flow through the first Floating gate transistor 1210.The reading electric current be detected can be expressed as high potential logic state.If non-volatility memorizer 110 is written into, the electronics being then injected into Floating gate 1100 can be enough to control line voltage couples to the partial offset of Floating gate 1100, or reduce at least in large quantities, thus, first Floating gate transistor 1210 can maintain cut-off state, or can electric current that only the conduction ratio reading electric current that can be detected when non-volatility memorizer 110 erases is much smaller.And be now detected less reading electric current and can be expressed as electronegative potential logic state.Above-mentioned will larger reading current judgement be high potential logic state and will less reading current judgement be electronegative potential logic state be only one embodiment of the invention and and be not used to limit the present invention.In other embodiments, larger reading electric current also can be mapped to electronegative potential logic state, and less reading electric current then can be mapped to high logic level.
Please refer to Figure 14, Figure 14 is the oscillogram of forbidding write operation of Figure 10 and Figure 11 nonvolatile storage location 110.The mode chart of Figure 14 describes during forbidding write operation, impose on the control line voltage of control line (CL), impose on the word line voltages on character line (WL), imposing on grid selects the grid on line (SG) to select line voltage, impose on the line voltage of erasing on line of erasing (EL), impose on the bitline voltage on bit line (BL), impose on the source line voltage on source electrode line (SL), impose on the second well voltage of the second conductive region (P wellblock PW2), impose on the 4th well voltage in N-type deep-well district 1130, and in the 3rd time point t3 to the 4th time point t4 the channel voltage of the first Floating gate transistor 1210 of lifting.The the first well voltage wherein imposing on the first conductive region (P wellblock PW1) is equal with control line voltage, and the Mitsui voltage imposing on the 3rd conductive region (N wellblock NW) is equal with line voltage of erasing.As shown in figure 14, from the second time point t2 to the 3rd time point t3, channel voltage is raised to the 6th voltage V6.From in the 3rd time point t3 to the 4th time point t4, control line voltage is the first voltage V1, and grid selects line voltage to be the second voltage V2, and line voltage of erasing is tertiary voltage V3, and bitline voltage is the 4th voltage V4, and channel voltage is the 5th voltage V5.During forbidding write operation, the magnitude relationship of the first voltage V1 to the 6th voltage V6 can be V1 >=V3>V5>V4 >=V2>V6.Can be V1 >=V3 >=V2>V4=V5=V6 >=0V in the magnitude relationship of write operation period first voltage V1 to the 6th voltage V6.For example, as shown in figure 14, during forbidding write operation, control line voltage can between the scope of 5 volts to 20 volts, word line voltages can between the scope of 5 volts of 0 volt, grid selection line voltage can between the scope of 1 volt to 5 volts, erasing line voltage can between the scope of 5 volts to 20 volts, bitline voltage can between the scope of 1 volt to 5 volts, source line voltage can between the scope of 0 volt to 5 volts, second well voltage can be 0 volt, and the 4th well voltage can between the scope of 5 volts to 20 volts.In addition, as shown in Figure 14 figure, what impose on the Mitsui voltage of the 3rd conductive region (N wellblock NW) rises leading the first well voltage (P wellblock PW1) imposing on the first conductive region of edge, and the edge that falls imposing on the Mitsui voltage of the 3rd conductive region (N wellblock NW) falls behind the first well voltage imposing on the first conductive region (P wellblock PW1), therefore can avoid the first conductive region (P wellblock PW1) and the forward bias voltage drop between the second conductive region (P wellblock PW2) and the 3rd conductive region (N wellblock NW).
In sum, the nonvolatile storage location of the invention described above can be completely compatible with general CMOS processing procedure, and only need relatively little assembly layout area can realize good write and speed of erasing, durability and data keeping quality, and without the cycle-index of degeneration memory.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. a nonvolatile storage location, is characterized in that, comprises:
Coupling assembly, is formed on the first conductive region;
First selects transistor, selects transistor series connection with the first Floating gate transistor and second, and wherein this first selection transistor, this first Floating gate transistor and this second selection transistor are formed on the second conductive region; And
Second Floating gate transistor, be formed on the 3rd conductive region, wherein this first conductive region, this second conductive region and the 3rd conductive region are formed in the 4th conductive region, and the grid of this first Floating gate transistor, the grid of this second Floating gate transistor and the electrode of this coupling assembly are the Floating gate formed by single-polysilicon;
Wherein this first conductive region, this second conductive region and the 3rd conductive region are well, and the 4th conductive region is deep-well; And
Wherein the 3rd conductive region is around this first conductive region and this second conductive region.
2. nonvolatile storage location as claimed in claim 1, is characterized in that, this first conductive region and this second conductive region belong to first electrically, and the 3rd conductive region and the 4th conductive region belong to second electrical.
3. nonvolatile storage location as claimed in claim 1, it is characterized in that, this Floating gate comprises:
First grid portion, in order to form this electrode of this coupling assembly; And
Second grid portion, in order to this grid of this grid and this second Floating gate transistor of forming this first Floating gate transistor;
Wherein the area in this first grid portion is large compared with the area in this second grid portion.
4. nonvolatile storage location as claimed in claim 1, it is characterized in that, this coupling assembly is metal-oxide-semiconductor's electric capacity or metal-oxide half field effect transistor.
5. nonvolatile storage location as claimed in claim 1, it is characterized in that, this second Floating gate transistor is metal-oxide half field effect transistor or metal-oxide-semiconductor's electric capacity.
6. nonvolatile storage location as claimed in claim 1, is characterized in that, this first Floating gate transistor is provided between this first selection transistor and this second selection transistor.
7. nonvolatile storage location as claimed in claim 6, is characterized in that, separately comprise:
Control line, is electrically connected on this coupling assembly;
Character line, is electrically connected on the grid of this first selection transistor;
Grid selects line, is electrically connected on the grid of this second selection transistor;
To erase line, be electrically connected on diffusion region and the 3rd conductive region of this second Floating gate transistor;
Bit line, is electrically connected on the drain of this second selection transistor; And
Source electrode line, is electrically connected on the source electrode of this first selection transistor.
8. nonvolatile storage location as claimed in claim 7, it is characterized in that, under read mode, control the control line voltage imposing on this control line, control the word line voltages imposing on this character line, controlling to impose on this grid selects the grid of line to select line voltage, control the line voltage of erasing imposing on this line of erasing, control the bitline voltage imposing on this bit line, control the source line voltage imposing on this source electrode line, control the first well voltage imposing on this first conductive region, control the second well voltage imposing on this second conductive region, control the Mitsui voltage imposing on the 3rd conductive region, and control the 4th well voltage imposing on the 4th conductive region, with senses flow this first selection transistor through being connected in series mutually, the electric current of this first Floating gate transistor and this second selection transistor, this the first well voltage wherein imposing on this first conductive region is equal with this control line voltage imposing on this control line and to impose on this Mitsui voltage of the 3rd conductive region equal with this line voltage of erasing imposing on this line of erasing.
9. nonvolatile storage location as claimed in claim 7, it is characterized in that, under write operation mode, control the control line voltage imposing on this control line, control the word line voltages imposing on this character line, controlling to impose on this grid selects the grid of line to select line voltage, control the line voltage of erasing imposing on this line of erasing, control the bitline voltage imposing on this bit line, control the source line voltage imposing on this source electrode line, control the first well voltage imposing on this first conductive region, control the second well voltage imposing on this second conductive region, control the Mitsui voltage imposing on the 3rd conductive region, and the 4th well voltage controlling to impose on the 4th conductive region flows into this first Floating gate transistor to bring out electrons tunnel, this the first well voltage wherein imposing on this first conductive region imposes on that this control line voltage of this control line is equal with this and to impose on this Mitsui voltage of the 3rd conductive region equal with this line voltage of erasing imposing on this line of erasing.
10. nonvolatile storage location as claimed in claim 7, it is characterized in that, forbidding under write operation mode, control the control line voltage imposing on this control line, control the word line voltages imposing on this character line, controlling to impose on this grid selects the grid of line to select line voltage, control the line voltage of erasing imposing on this line of erasing, control the bitline voltage imposing on this bit line, control the source line voltage imposing on this source electrode line, control the first well voltage imposing on this first conductive region, control the second well voltage imposing on this second conductive region, control the Mitsui voltage imposing on the 3rd conductive region, and the 4th well voltage controlling to impose on the 4th conductive region ends this first selection transistor and this second selection transistor to force, this the first well voltage wherein imposing on this first conductive region is equal with this control line voltage imposing on this control line and to impose on this Mitsui voltage of the 3rd conductive region equal with this line voltage of erasing imposing on this line of erasing.
11. nonvolatile storage locations as claimed in claim 7, it is characterized in that, under erase operation for use pattern, control the control line voltage imposing on this control line, control the word line voltages imposing on this character line, controlling to impose on this grid selects the grid of line to select line voltage, control the line voltage of erasing imposing on this line of erasing, control the bitline voltage imposing on this bit line, control the source line voltage imposing on this source electrode line, control the first well voltage imposing on this first conductive region, control the second well voltage imposing on this second conductive region, control the Mitsui voltage imposing on the 3rd conductive region, and the 4th well voltage controlling to impose on the 4th conductive region penetrates in this second Floating gate transistor to bring out electrons tunnel, this Mitsui voltage wherein imposing on the 3rd conductive region is equal with this line voltage of erasing imposing on this line of erasing.
12. nonvolatile storage locations as claimed in claim 7, it is characterized in that, what impose on the Mitsui voltage of the 3rd conductive region rises leading the first well voltage imposing on this first conductive region of edge, and the edge that falls imposing on this Mitsui voltage of the 3rd conductive region falls behind this first well voltage imposing on this first conductive region.
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| CN107093456A (en) * | 2016-02-17 | 2017-08-25 | 爱思开海力士有限公司 | Single-layer polysilicon non-volatile memory cell |
| CN107093456B (en) * | 2016-02-17 | 2020-09-22 | 爱思开海力士有限公司 | Single-layer polysilicon nonvolatile memory cell |
| CN108806748A (en) * | 2017-05-01 | 2018-11-13 | 卡比科技有限公司 | Nonvolatile memory device and method of operating the same |
| CN109841629A (en) * | 2017-11-24 | 2019-06-04 | 力旺电子股份有限公司 | Every multiunit Nonvolatile memery unit |
| CN109841629B (en) * | 2017-11-24 | 2020-11-27 | 力旺电子股份有限公司 | Multi-cell per bit non-volatile memory cell |
| US11063772B2 (en) | 2017-11-24 | 2021-07-13 | Ememory Technology Inc. | Multi-cell per bit nonvolatile memory unit |
| CN110610735A (en) * | 2018-06-15 | 2019-12-24 | 卡比科技有限公司 | Non-volatile memory device |
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| CN105261618B (en) | 2018-07-27 |
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