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CN1052340C - 塑料模制的具有小平直度偏差引线的集成电路组件 - Google Patents

塑料模制的具有小平直度偏差引线的集成电路组件 Download PDF

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CN1052340C
CN1052340C CN96112259A CN96112259A CN1052340C CN 1052340 C CN1052340 C CN 1052340C CN 96112259 A CN96112259 A CN 96112259A CN 96112259 A CN96112259 A CN 96112259A CN 1052340 C CN1052340 C CN 1052340C
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insulating barrier
assembly
lead
semiconductor chip
metal level
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CN1148733A (zh
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铃木克信
羽贺彰
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NEC Corp
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NEC Corp
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Abstract

在塑料模制IC组件中，在绝缘层(3)的第1表面上形成金属图形(2)的引线(1)，在绝缘层的第2表面上，形成与半导体芯片(6)相连的导电图形(4)。穿过绝缘层的通孔，把导电图形连到引线上。

Description

塑料模制的具有小平直度偏差引线的集成电路组件
本发明涉及一种塑料模制集成电路(IC)组件。
在第1现有技术塑料模制IC组件中，把半导体芯片装配在岛上并用焊接引线连接到引线。用模制树脂密封半导体芯片、岛、焊接引线和引线。从模制树脂伸出的外引线部分被分段弯曲。以后详细解释它。
但是，在第1现有技术塑料模制IC组件中，当半导体芯片引线数增加时，则减少引线间距，即，外引线间距，它使引线平直度产生偏差。于是，它难于可靠地处理外引线，热耗散效果不好。此外，从模制树脂伸出的外引线受到机械碰撞，容易变形。此外，由于他们的弹性特性和模制树脂的热膨胀和收缩，引线容易变形。
在第2现有技术塑料模制IC组件中(见日本实用新型公开NO.2-95256)，把绝缘带粘贴到外引线上，于是，保证了外引线的平直度。以后将详细解释。
但是，在第2现有技术塑料模制IC组件中，绝缘带增加制造成本。并且引线容易变形。
在第3现有技术塑料模制IC组件中，在中间绝缘衬底上形成导电图形。这样，导电图形有许多导电条，其外侧间距比内侧间距大。通过焊接引线把半导体芯片连接到导电图形的内侧上，通过焊接引线把引线连到导电图形的外侧。于是，可能增加半导体芯片导线数目。以后将详细解释它。
但是，在第3现有技术塑料模制IC组件，两种焊接操作减少制造的合格率，增加制造成本。在组件中延迟传输信号，于是减少工作速度。并且，引线容易变形。
在第4现有技术塑料模制IC组件中，设置散热片，其由有优良散热特性的金属构成，以后将详细解释它。
但是，在第4现有技术塑料模制IC组件中，散热片和引线框架增加制造成本。并且，引线容易变形。
本发明的目的是提供一种塑料模制IC组件，其具有小平整度偏差特性。
按照本发明，在塑料摸制IC组件中，在绝缘层第1表面上形成金属图形和引线，在绝缘层第2表面上形成和半导体芯片连接的导电图形。通过绝缘层的孔，连接导电图形和引线。这样，保持平整度，引线几乎不变形。
下面参考附图进行叙述，并和现有技术进行比较，将会更清楚的理解本发明，其中：
图1A是表示第1现有技术塑料模制IC组件的透视图：
图1B是表示如图1A所示组件的剖视图；
图2A是表示第2现有技术塑料模制IC组件的透视图；
图2B是如图2A所示组件的剖视图；
图3A是表示第3现有技术模制IC组件的透视图；
图3B是如图3A所示组件的剖视图；
图4A是第4现有技术塑料模制IC组件的透视图；
图4B是如图4A所示组件的剖视图；
图5A是表示按照本发明塑料模制IC组件第1实施例的俯视图；
图5B是如图5A所示组件的后视图；
图5C是如图5A所示组件的剖视图。
图6A是表示按照本发明塑料模制IC组件第2实施例的俯视图；
图6B是如图6A所示组件的后视图；
图6C是如图6A所示组件的剖视图；
图7A是按照本发明塑料模制IC组件第3实施例的俯视图；
图7B是如图7A所示组件的后视图；
图7C是如图7A所示组件的剖视图；
图8A是按照本发明塑料模制IC组件第4实施例的俯视图；
图8B是如图8A所示组件的后视图；
图8C是如图8A所示组件的剖视图；
图9A是按照本发明塑料模制IC组件第5实施例的俯视图；
图9B是如图9A所示组件的后视图；
图9C是如图9A所示组件的剖视图；
图10A是按照本发明塑料模制IC组件第6实施例的俯视图；
图10B是如图10A所示组件的后视图；
图10C是如图10A所示组件的剖视图；
图11A，11B和11C是分别表示如图10A，10B，10C所示一种修改的塑料模制IC组件的俯视图，后视图和剖视图；
图12A，12B和12C分别表示如图10A，10B，10C所示另一种改形塑料模制IC组件的俯视图，后视图，剖视图；
图13A是按照本发明塑料模制IC组件第7实施例的俯视图；
图13B是如图13A所示组件的后视图；
图13C是如图13A所示组件的剖视图；
图14是按照本发明塑料模制IC组件第8实施例的剖视图；
图15是按照本发明塑料模制IC组件第9实施例的剖视图；
图16A到图16G是说明如图13A，13B，13C所示组件制造方法的剖视图。
在叙述优选实施例之前，将参考图1A，1B，2A，2B，3A，3B，4A，4B解释现有技术塑料模制IC组件。
图1A和图1B分别是透视图和剖视图，表示第1现有技术塑料模制IC组件，通过银(Ag)膏粘含剂层102把半导体芯片101粘合到岛103上。通过焊接引线104把半导体芯片101连接到引线105上。利用模制树脂外壳106密封半导体芯片101、Au膏粘合剂层102、岛103、焊接引线104和引线105。引线105的外引线105a从模制树脂外壳106伸出，被金属模具(未示出)分段弯曲。
但是，在图1A和图1B的塑料模制IC组件中，当增加半导体芯片101的引线数时，引线105的间距，即外引线105a的间距减少，使外引线105a平直度产生偏差。这样，难于有保障地处理外引线105a，特别是方形扁平封装组件(QFP)和载带组件(TCP)，此处外引线间距小于0.5mm。而且，QFPS变得更小，要求较大的热耗散。此外，从模制树脂外壳106伸出的外引线105a受到机械碰撞，容易变形。还有，由于其弹性特性和模制树脂外壳的热膨胀和收缩，外引线105a容易变形。
图2A和图2B分别是透视图和剖视图，表示第2现有技术塑料模制IC组件(见日本实用新型公开NO.2-95256)，把绝缘带107粘合到如图1A和图1B所示的外引线105a，这样，保证了外引线105a的平直度。
但是，在如图2A和2B所示的塑料模制IC组件中，绝缘带107增加制造成本。而且，导线105仍然容易变形。
在表示第3现有技术塑料模制IC组件的透视图3A和剖视图3B中，中间绝缘衬底108形成在图1A和图1B所示的岛103上，导电图形109形成在中间绝缘衬底108上。导电图形109有许多外侧间距大于内侧的间距的导电条。通过焊接把引线14A连接到半导体芯片101到导电图形109的内侧，通过地焊接引线14B连接到引线105导电图形的外侧。于是，可能增加半导体芯片101的引线数。
但是，在如图3A和3B所示的塑料模制IC组件中，两种引线焊接操作减少了制造合格率，于是增加了制造成本。并且，在组件中延迟传输信号，这就减少了工作速度。此外，引线105容易变形。
透视图4A和剖视图4B表示第4现有技术塑料模制IC组件，散热片110由优良散热金属构成，代替图1A和1B所示的岛103。即，通过Ag膏粘合层102把散热片110粘合到半导体芯片101上，同时，通过绝缘树脂层111把散热片110和引线105的内引线部分粘合在一起，从而减少热阻。
但是，在4A和4B塑料模制IC组件中，散热片110和引线105的引线框架增加制造成本。而且，引线105容易变形。
俯视图5A、后视图5B、剖视图5C表示本发明第1实施例，引线1和基底图形2是由大约0.15到0.2mm厚的铜片制成，在其上设置大约20到50μm的聚酰亚胺。在聚酰亚胺上设置由约18到35μm厚的铜箔或类似物组成的导电图形4。导电图形4有很多条，其外侧间距大于内侧间距。导电图形4通过孔TH和引线1相连。
在聚酰亚胺中心部分打孔形成器件孔。穿过器件孔在基底图形2上设置由铜片制成的岛5，利用Ag(银)膏粘合层(未表示)或诸如此类的粘合层把半导体芯片6粘接到岛5上。
利用焊接引线7把半导体芯片6连到导电图形4上。
用模制树脂外壳8密封聚酰亚胺层3，导电图形4、岛5、半导体芯片6、焊接引线7。
在5A和5B的塑料模制IC组件中，因为引线1整体地设置在聚酰亚胺层3上，引线1的平直度几乎没有产生偏差。并且，引线1几乎没有变形。由于焊接引线数少，可能减少成本，抑制传输信号的延迟。此外，基底图形2增强了半导体芯片6的热耗散。
利用焊接把图5A、5B和5C所示的塑料模制IC组件装配到印刷电路板上(未表示)。这样，当引线1的间距太窄的时候，在引线1之间可能产生焊料桥(或短路)。
图6A、6B、6C表示本发明第2实施例，将图5A、5B、5C所示的引线1的外部引线交错地设置，显著增加引线1的间距。因此，可能抑制上述的短路现象发生。
图7A、7B、7C表示本发明第3实施例，不存在图5A，5B，5C的聚酰亚胺层3的器件孔，用图形2A和2B代替图5A、5B、5C的基底图形2。这样，把图形2A和2B作为电源电压端和地电压端，或者把图形2A和2B作为地电压端。
图8A、8B、8C表示本发明第4实施例，图7A、7B、7C的图形2A和2B作为电源电压端和地电压端，把芯片电容9设置在图形2A和2B之间。注意，把设置在图形2A和2B之间50Ω或75Ω的芯片电阻代替芯片电容9。
图9A、9B、9C表示本发明第5实施例，图5A，5B，5C聚酰亚胺层3的器件孔不存在，利用小凸块10把半导体芯片6装置在导电图形4上。这样，半导体芯片6成为倒置连接类型的芯片。注意，小凸块10可能形成在导电图形4的边缘或者半导体芯片6的电极上。
图10A、10B、10C表示本发明第6实施例，图5A、5B、5C的引线1从聚酰亚胺层3中伸出。交错设置引线1的外部引线1a，则显著的增加引线1的间距。因此，抑制短路现象发生，引线1可能变形成如图11A，11B，11C那样的鸥冀形状。引线1也可能变形成如图12A，12B，12C所示的丁字形状。
图13A、13B、13C表示本发明第7实施例，环形图形11设置在导电图形4的外围，并从此隔开。可能把电源电压或地电压加在环形图形11上。当形成模制树脂外壳时，环形图形11阻挡树脂。
图14表示本发明第8实施例，用聚酰亚胺层3A和3B代替图13C中的聚酰亚胺层3。导电图形4A和4B形成在聚酰亚胺层3A和3B上，并通过焊接引线7A和7B与半导体芯片6相连。注意，环形图形11形成在聚酰亚胺层3B上。
图15表示本发明第9实施例，设置半导体芯片6A和6B代替图15中的半导体芯片6。注意，可以把本发明用于包括3个以上半导体芯片的组件。
制造本发明第1到第9实施例半导体器件的步骤，相互间类似。下面参考附图16A到16G，解释如图13A，13B，13C所示的制造组件的方法。
首先，参考图16A，设置大约0.15到0.20mm的铜基片1601。然后，在铜基片1601上淀积大约20到50μm厚的聚酰亚胺层1602，然后在聚酰亚胺1602上淀积大约9到18μm厚的铜箔1603。
接着，参考图16B，利用光刻工艺形成光致抗蚀剂图形1604，利用光致抗蚀剂图形1604作为掩模腐蚀铜箔1603。然后，除掉光致抗蚀剂图形1604。
接着，参考图16C，利用铜箔1603作为掩模，腐蚀聚酰亚胺层1602。这样，获得图13A，13B，13C的聚酰亚胺层3。形成如图13A、13B、13C所示的聚酰亚胺层3的通孔TH。
接着，参考图16D，利用电镀在整个表面上淀积大约9到17μm的铜层1605。
接着，参考图16E，用光刻工艺形成光致抗蚀剂图形1606，用光致抗蚀剂图形1606作掩模，腐蚀铜层1605。
参考图16E，利用光刻工艺形成光致抗触剂图形1607，然后，用光致抗蚀剂图形1607作掩模，腐蚀铜基片1601。
参考图16G，除掉光致抗蚀剂图形1606和1607。结果，获得引线1，基底图形2，导电图形4，环形图形11。
在图16G的器件孔中装配岛5和半导体芯片6，在半导体芯片6和导电图形4之间焊接引线7。最后，用金属模具夹住器件注入树脂，于是制成如图13A，13B，13C所示的半导体器件。
如上所述，按照本发明，因为在绝缘层上形成引线，并使引线穿过绝缘层的通孔和连接半导体芯片的导电图形相连，结果没有引起引线的平直度引起偏差，引线几乎没有变形。

Claims (10)

1.一种半导体组件，其特征在于，它包括：
具有第1和第2表面的绝缘层(3)；
形成在所述绝缘层第1表面上的基底图形(2)；
形成只在所述绝缘层第1表面上的引线(1)；
形成在所述绝缘层第2表面上的导电图形(4)，穿过所述绝缘层的通孔(TH)和所述引线相连；
和所述导电图形相连的半导体芯片(6)；
密封所述半导体芯片的模制树脂外壳(8)。
2.按照权利要求1的组件，其特征在于，交错设置所述引线的外段。
3.按照权利要求1的组件，其特征在于，还包括穿过所述绝缘层的器件孔形成在所述基底图形上的岛(5)，形成在所述岛上的所述半导体芯片。
4.按照权利要求3的组件，其特征在于，利用焊接引线(7)把所述半导体芯片连到所述导电图形上。
5.按照权利要求1的组件，其特征在于，利用小凸块(10)把所述半导体芯片连到所述导电层上。
6.按照权利要求1的组件，其特征在于，还包括环状图形(11)，其形成在所述绝缘层第2表面的外部。
7.按照权利要求4的组件，其特征在于，还包括：
另一绝缘层(3B)，其形成在所述绝缘层上；
另一导电图形(4B)，其形成在所述的其它绝缘层上；
所述半导体芯片，其通过另一焊接引线(7B)和所述另一导电层相连。
8.按照权利要求1的组件，其特征在于，还包括与所述导电图形相连的其它半导体芯片(6A，6B)。
9.一种用于制造如权利要求1所述的半导体组件的方法，其特征在于，它包括下列步骤：
在绝缘层(1602)的第1表面上形成第1金属层(1601)；
在所述绝缘层的第2表面上形成第2金属层(1603)
把所述第2金属层刻成图形；
利用所述的形成图形的第2金属层作掩模，腐蚀所述的绝缘层，以便在所述绝缘层中形成器件孔和通孔；
在所述绝缘层的第2表面上淀积第3金属层(1605)，通过所述器件孔和所述通孔中的所述第3导电层使所述第1金属层和所述第2金属层接触；
使所述第3金属层形成图形，以除掉所述器件孔中的所述第3金属层；
把所述第1金属层形成图形，以便形成基底图形(2)和引线(1)，所述基底图形面对所述器件孔，所述引线通过所述通孔和所述第2和第3金属层相连；
通过所述器件孔，把半导体芯片(6)设置在所述的基底图形上；
连接所述半导体芯片和所述第3金属层；
用树脂密封所述半导体芯片。
10.按照权利要求9的方法，其特征在于，所述第3金属层形成步骤在所述绝缘层第2表面外部上形成一环形图形(11)。
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US5844307A (en) 1998-12-01
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JP2917868B2 (ja) 1999-07-12

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