CN105204581A - Satellite-borne beam controlling computer - Google Patents

Abstract

The invention discloses a satellite-borne beam controlling computer. The satellite-borne beam controlling computer comprises a processor MCU, an SRAM, a FLASH memory, an interface circuit and a driving circuit, wherein the SRAM, the FLASH memory, the interface circuit and the driving circuit are electrically connected with the processor MCU. A BM3803MGRH chip is adopted in the processor MCU. Two UT9Q512K32E-SWC chips and one B8R512K8RH chip are adopted in the SRAM. Two ACT-F512K32N-060P3Q chips are adopted in the FLASH memory. A driver SN74ALVC164245DGG chip is adopted in the driving circuit. The satellite-borne beam controlling computer is suitable for being applied to the spaceflight field, can be in embedded design, can adapt to the single event effect, the total dose effect, surface charge and discharge and the like of astrospace, has the advantages of being small in size, low in weight, low in power consumption and the like, and meets the high-reliability, non-maintainability and radiation resistance and other requirements of satellite-borne electronic equipment.

Description

A kind of satellite-borne wave beam computer for controlling

Technical field

The present invention relates to a kind of computing machine of satellite borne electronic system measurement and control area, particularly relate to a kind of satellite-borne wave beam computer for controlling.

Background technology

Growing along with every country economic construction and national defense construction, the range of application of satellite is more and more extensive, as communication and signal forwarding, for observing meteorology, topography and geomorphology, global location and navigation etc.Under the promotion of widely applying, the demand of satellite is growing, and satellite overall performance requires to improve constantly, and day by day strengthens the demand of spaceborne autonomous processing power.

Spaceborne ripple control computer is the key equipment that satellite Autonomous controls, and the wave beam that the quality of its product design, the height of quality have been directly connected to satellite controls and information processing capability.Environment residing for satellite platform and ground and low hollow panel completely different, the circuit reliability design difficulty caused due to space environment (particularly outstanding with accumulated dose, single-particle, interior charged and surperficial discharge and recharge) increases suddenly, makes simple function originally need a large amount of peripheral safeguard measures that equipment just can be made normally to work; Simultaneously because aerospace product does not mostly possess the property tieed up, require that equipment runs reliably and with long-term, ensure there is counter-measure when breaking down; Space electronic equipment also requires to reduce weight as far as possible, reduces volume, reduces hear rate simultaneously; Simultaneously due to the rugged surroundings in space, cause can alternative starting material of space environment work and components and parts scope very limited, even selectable components and parts, performance is also all very low, needs designer's serious analysis to use.Therefore, design a meet spaceborne environment under the Embedded beam computer for controlling that uses extremely urgent.

Summary of the invention

The object of the invention is to the particular/special requirement according to Space-borne, design the satellite-borne wave beam computer for controlling of a applicable space industry application, it can be embedded design, can adapt to the single particle effect in cosmic space, total dose effect, surperficial discharge and recharge etc.There is the features such as volume is little, lightweight, low in energy consumption, meet the requirements such as electronic equipment on satellite high reliability, non-maintenanceability, Flouride-resistani acid phesphatase.

Solution of the present invention is: a kind of satellite-borne wave beam computer for controlling, it SRAM memory, FLASH memory, interface circuit, driving circuit of comprising processor MCU and being all electrically connected with processor MCU; Wherein, processor MCU is BM3803MGRH chip, SRAM memory is 2 UT9Q512K32E-SWC chips and 1 B8R512K8RH chip, and FLASH memory is 2 ACT-F512K32N-060P3Q chips, and driving circuit adopts driver SN74ALVC164245DGG chip.

As the further improvement of such scheme, BM3803MGRH chip, by its address wire [ADDR0 ~ ADDR27], data line [DATA0 ~ DATA31], chip select line SRAM_CS_0, SRAM_CS_1, ROM_CE0, ROM_CE1, is connected with UT9Q512K32E-SWC chip, ACT-F512K32N-060P3Q chip, the address wire of B8R512K8RH chip, data line, chip select line after driver SN74ALVC164245DGG chip drives.

As the further improvement of such scheme, interface circuit is standard RS232 interface, adopt MAX3232ESE chip, BM3803MGRH chip carries out level conversion by the UART4 mouth of its pin V2, W5, the UART1 mouth of pin AH30, AM34 through MAX3232ESE chip, be converted to standard RS232 interface level, wherein UART4 mouth is debug port, in a debug state, UART4 mouth receives the debug command from host computer, UART1 mouth is common serial ports, and host computer carries out data transmission alternately; To be connected with satellite task electronic system communication by the UART3 mouth of pin AB2, AC1 of BM3803MGRH chip.

As the further improvement of such scheme, AG1, AD6 pin of the clock delay input of BM3803MGRH chip connects 1K ohm pull down ground connection; G33, F28, A33, E29, K30 pin of the frequency multiplication multiple of BM3803MGRH chip, control V4, W3 pin entering debugging mode.

As the further improvement of such scheme, the G35 pin of BM3803MGRH connects 1K ohm pull down resistance to ground, during input/output space read and write access, after the latent period of configuration, if BRDYN is after low level, terminate to wait for that the N3 pin of BM3803MGRH chip connects 1K ohm pull down resistance to ground, the abnormal instruction of bus, internal bus can receive errored response; The U1 pin series connection 1K Ohmage of BM3803MGRH chip connects LED to ground, and when BM3803MGRH chip enters debugging mode, U1 pin exports high level, drives V2LED lamp to light; The P6 pin series connection 1K Ohmage of BM3803MGRH chip connects LED to 3.3V power supply, and when processor run-time error, P6 pin is low level, and V3LED lamp is lighted; The AB6 pin series connection 1K Ohmage of same BM3803MGRH chip connects LED to 3.3V power supply, and when processor house dog is overflowed, AB6 pin is low level, and V4LED lamp is lighted.

As the further improvement of such scheme, pin DSUEN, DSUBRE, PLL_M0, PLL_M1, PLL_M2, PLL_M3, PLL_BP of BM3803MGRH chip are received on toggle switch, carry out pull-up, drop-down selection, when DSUEN, DSUBRE pull-up, BM3803MGRH enters debugging mode, processor receives the order from serial ports 4, and when DSUEN, DSUBRE are drop-down, BM3803MGRH enters operational mode.

As the further improvement of such scheme, the frequency multiplication multiple of pin PLL_M0, PLL_M1, PLL_M2, PLL_M3 placement processor MCU of BM3803MGRH chip, when PLL_M [3:0] is arranged to " 0001 ", M is 1; When being arranged to " 0010 ", M is 2; The rest may be inferred, when being arranged to " 1111 "; M is 15, PLL is when BYPASS pattern and PLL_BP are " 1 ", processor MCU frequency of operation and Clock Multiplier Factor M have nothing to do, PLL is when mode of operation and PLL_BP are " 0 ", processor MCU frequency of operation is that the output frequency of clock source is multiplied by Clock Multiplier Factor M and obtains, and now the phaselocked loop input range of processor MCU is 2MHz-30MHz.

As the further improvement of such scheme, the SRAM memory be connected with BM3803MGRH chip be used for scratch system run data, use two panels UT9Q512K32E-SWC chip, by chip selection signal H34 pin RAMSN [0] of BM3803MGRH chip, L31 pin RAMSN [1] is through signal drived control CE, and T30 pin RWEN [0], M34 pin RAMOEN [0] drives through signal and carries out read-write operation to SRAM, and store 8 SRAM memory B8R512K8RH of EDAC check code, by BM3803MGRH chip selection signal K34 pin RAMSN [2] control chip gating, and N33 pin RWEN [1], R35 pin RAMOEN [1] drives through signal and carries out read-write operation to SRAM.

As the further improvement of such scheme, the FLASH memory be connected with BM3803MGRH chip is used for storing operating system, application program and beam-control code data, use two panels ACT-F512K32N-060P3Q chip, by chip selection signal U35 pin ROMSN [0] of BM3803MGRH chip, V30 pin ROMSN [1] through signal drived control control chip gating, and K32 pin WRITEn signal, J31 pin READ signal drive through signal and carry out read-write operation to storer SRAM.

As the further improvement of such scheme, the debug serial port of BM3803MGRH chip, by MAX3232ESE chip, Transistor-Transistor Logic level is converted to RS232 level, when DSUEN, DSUBRE pull-up of BM3803MGRH chip, processor MCU enters debugging mode, to be connected with host computer by serial interface cable and to debug, processor MCU receives the debug command of host computer.

The present invention will meet reliability application under single particle effect under the complex environment of cosmic space, total dose effect, surperficial discharge and recharge, vacuum condition, whole beam guidance computer circuit board needs to adopt following design tactics: select the aerospace level device with radioresistance index, and use device derate; Carry out the Allowance Design of circuit, component parameter is changed within the specific limits, the product failure caused because this change causes circuit performance to drift about can not be caused; EDAC technology is adopted to carry out EDC error detection and correction to single-particle inversion; Heat loss through conduction is carried out to heater members.Satellite-borne wave beam computer for controlling, can be widely used in the fields such as telstar, instrumented satellite and reconnaissance satellite.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of the satellite-borne wave beam computer for controlling that the embodiment of the present invention provides.

Fig. 2 is the circuit theory diagrams of processor MCU in Fig. 1.

Fig. 2-1 is the enlarged drawing of region in Fig. 2 (1).

Fig. 2-2 is enlarged drawings of region in Fig. 2 (2).

Fig. 2-3 is enlarged drawings of region in Fig. 2 (3).

Fig. 2-4 is enlarged drawings of region in Fig. 2 (4).

Fig. 2-5 is enlarged drawings of region in Fig. 2 (5).

Fig. 2-6 is enlarged drawings of region in Fig. 2 (6).

Fig. 2-7 is enlarged drawings of region in Fig. 2 (7).

Fig. 2-8 is enlarged drawings of region in Fig. 2 (8).

Fig. 2-9 is enlarged drawings of region in Fig. 2 (9).

Fig. 2-10 is enlarged drawings of region in Fig. 2 (10).

Fig. 2-11 is enlarged drawings of region in Fig. 2 (11).

Fig. 2-12 is enlarged drawings of region in Fig. 2 (12).

Fig. 2-13 is enlarged drawings of region in Fig. 2 (13).

Fig. 2-14 is enlarged drawings of region in Fig. 2 (14).

Fig. 2-15 is enlarged drawings of region in Fig. 2 (15).

Fig. 3 is the circuit theory diagrams of the B8R512K8RH chip of SRAM memory in Fig. 1.

Fig. 4 is the circuit theory diagrams of the UT9Q512K32E-SWC chip of wherein a slice of SRAM memory in Fig. 1.

Fig. 5 is the circuit theory diagrams of the UT9Q512K32E-SWC chip of other a slice of SRAM memory in Fig. 1.

Fig. 6 is the circuit theory diagrams of the ACT-F512K32N-060P3Q chip of wherein a slice of FLASH memory in Fig. 1.

Fig. 7 is the circuit theory diagrams of the ACT-F512K32N-060P3Q chip of other a slice of FLASH memory in Fig. 1.

Fig. 8 is the circuit theory diagrams of interface circuit in Fig. 1.

Fig. 9 is the communication succession figure that Fig. 1 culminant star carries beam guidance computer and Beamsteering Unit;

Figure 10 is the communications protocol figure that Fig. 1 culminant star carries beam guidance computer and satellite task electronic system.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

The present invention is mainly for the realization of beam guidance computer unit, beam guidance computer is the core link of beam steering system, and Beamsteering Unit is primarily of the part such as BM3803MGRH processor, signal drive circuit, differential conversion circuit, SRAM memory, FLASH memory, deploy switch, crystal oscillator, the serial port level conversion composition of the SPARCV8 framework of anti-space radiation.Beam guidance computer receive satellite task electronic system operating mode instruction, pair time information, reception and under storing ground injection way continuous 1 segmental arc (500 groups) sensing data, in conjunction with rectification building-out value, phase shift, time delay code are calculated, receive (β, α) value, according to (β, α) beam pointing-angle, calculate the phase shift code of each phase shifter on antenna array, the decay code of attenuator, the time delay code of time delay amplifier, be referred to as beam-control code.And beam-control code is sent to together with work schedule the Beamsteering Unit of antenna out of my cabin.

In the present embodiment, the satellite-borne wave beam computer for controlling SRAM memory, FLASH memory, interface circuit, driving circuit, the power supply that comprise processor MCU and be all electrically connected with processor MCU.

The specific operation process of satellite-borne wave beam computer for controlling is: by ground control station by beam position data (β, α) send to satellite task electronic system platform, or independently produce beam position data (β by satellite task electronic system platform, α), β, α is respectively horizontal angle and the angle of pitch of controlling antenna wave beam to point, beam guidance computer is according to (β, α) value, calculate the phase shift code of each phase shifter on antenna array, the decay code of attenuator, the time delay code of time delay amplifier, and be added with the check code that antenna array obtains in power up initialization process, eliminate the inconsistency of each passage.Finally obtain the time delay code of the phase shift code of each phase shifter, the decay code of attenuator and delay line, be referred to as beam-control code; Beam guidance computer, according to the job requirement of complete machine satellite antenna system, produces the work schedule meeting front end microwave TR assembly accordingly.Beam-control code is sent to Beamsteering Unit by beam guidance computer together with work schedule.

The present invention is mainly for the realization of beam guidance computer device, and beam guidance computer is the core link of beam steering system, and this Embedded beam computer for controlling has conventional serial ports, can realize external communication, as: receive operating mode instruction; Receive satellite send pair time information; Receive (β, α) value that satellite sends; Receive and the sensing data of continuous 1 segmental arc (500 groups) under storing ground injection way; Data after reception enter MCU aftertreatment, complete corresponding computing, and different computing demand software programmings realizes, and in conjunction with rectification building-out value, calculate, inter-channel phase difference counted in phase shift code and compensate phase shift, time delay code.

MCU is the core devices of beam guidance computer unit, and its stability directly affects the control of antenna beam.The MCU that satellite, airship use faces the working environment more complicated and harsh than ground environment.Device need resist rocket launching time vibration and impact, bear the high temperature in operational process, low temperature, vacuum environment, and normally can work under space radiation environment.All the time, the MCU that China aerospace electron uses can only dependence on import device, and the independent development development of this situation to the aerospace industry of China is very unfavorable.External spationautics developed country carries out strict control of export to high-performance army grade, aerospace level electron device, and the external electronic devices and components source causing China's aerospace engineering to be purchased is unreliable, the order cycle time long and the source of goods cannot ensure.The long-range sustainable development of this present situation to the military project of China and aerospace engineering causes serious threat.But this year, China's microelectric technique achieved significant progress, emerges a collection of outstanding research institute and company along with production domesticization components and parts progress of research.

The MCU that the present invention uses, the BM3803MGRH processor of radioresistance 32 the SPARCV8 frameworks adopting research institute of China Aerospace Science and Technology Corporation the 9th the 772nd to research and develop.BM3803MGRH has good anti-radiation performance, and its resistant to total dose ability is greater than 1 × 103Gy (Si), and anti-single particle overturn (SEU) is better than 3E-5 mistake/device/sky, and anti-single particle breech lock is better than 75MeV/cm2/mg; Chip internal also with the floating-point calculation component of 64, and supports EDAC (ErrorDetectAndCorrect error detection and correction the adopts Hamming code) function of internal memory operation, can entangle a dislocation and inspection two dislocations to 32 position datawires; With regard to performance, BM3803MGRH far above 8086/87, the processor that can apply in spaceborne radiation environment such as 80C32, i386ex, TSC695.It can have to have in the environment of higher reliability requirement compared with highly anti-radiation requirement and weapon, ground, naval vessel etc. in aerospace etc. applies.

In systems in which, SRAM is used for the operating data of storage program, because SRAM is single-particle Sensitive Apparatus, easy generation logic upset, so the SRAM of Flouride-resistani acid phesphatase will be selected, the UT9Q512K32E-SWC model SRAM of Aeroflex company is selected in this design, its capacity is 2M byte, data bit width is 32bit, resistant to total dose ability is greater than 50krads (Si), anti-single particle breech lock is better than 80MeV/cm2/mg, linear energy transfer threshold values is greater than 10MeV/cm2/mg, the requirement of space flight SRAM can be met, plate is selected 2 UT9Q512K32E-SWC, capacity is 4MB, control to use by BM3803MGRH chip selection signal.Because this beam guidance computer application of installation is in spaceborne environment, in order to the reliability read and write data, this device uses BM3803FMGRH processor to EDAC (error correcting and detecting) function of external memory access, correct a mistake in 32 words, detect two mistakes in 32 words.Therefore the SRAM memory (use wherein 7 bit data positions) of a slice 8 need be increased, store the check code of EDAC, model also select space flight nine institute 772 B8R512K8RH storer.

FLASH is used for storage three kinds of contents: operating system, application program and beam-control code data, taking up room of application program itself is generally little, general hundreds of about K.Operating system adopts VxWorks, system does not need other assemblies such as network, only use the functional modules such as difference serial ports and timer, because the space that operating system takies should be no more than 1MB, the sensing data wave control code data of ripple control computer continuous 1 segmental arc (500 groups) under ground injection way will be stored.Segmental arc data are: 1920 (passage) * 16bit*500 group=1920000 byte, about 2M byte, and therefore, FLASH is used for storage three kinds of contents needs 4MB capacity altogether.In space flight equipment catalogue, the FLASH model of max cap. is ACT-F512K32N-060P3Q, and capacity is 2M byte, and data live width is 32bit.Use two panels, is controlled by BM3803MGRH chip selection signal.

For improving stability and the antijamming capability of ripple control link data and sequential transmission; beam guidance computer and ripple control unit, RS422 interface level between beam guidance computer and satellite task electronic system, is all adopted to carry out communication; with check code function during data transmission, have during sequential transmission and extremely judge defencive function.

See Fig. 1, whole beam guidance computer is the BM3803MGRH embedded system based on SPARCV8 framework, comprises processor B M3803MGRH, 2 UT9Q512K32E-SWCSRAM, 2 ACT-F512K32N-060P3QFLASH, crystal oscillator, deploy switch, serial interface switching circuit, signal drive circuits etc.Beam guidance computer receive satellite task electronic system operating mode instruction, pair time information, system time is adjusted, receive and under storing ground injection way continuous 1 segmental arc (500 groups) sensing data, in conjunction with rectification building-out value, phase shift, time delay code are calculated, receive (β, α) value, according to (β, α) beam pointing-angle, calculate the beam-control code of each T/R assembly on antenna array, according to the job requirement of complete machine satellite antenna system, produce the work schedule meeting front end microwave TR assembly accordingly.And beam-control code is sent to Beamsteering Unit together with work schedule.

See Fig. 2, be the circuit theory diagrams of BM3803MGRH, due to Fig. 2 more complicated, be therefore divided into 15 regions and carry out amplification display, wherein, Fig. 2-1 is the enlarged drawing of region in Fig. 2 (1); Fig. 2-2 is enlarged drawings of region in Fig. 2 (2); Fig. 2-3 is enlarged drawings of region in Fig. 2 (3); Fig. 2-4 is enlarged drawings of region in Fig. 2 (4); Fig. 2-5 is enlarged drawings of region in Fig. 2 (5); Fig. 2-6 is enlarged drawings of region in Fig. 2 (6); Fig. 2-7 is enlarged drawings of region in Fig. 2 (7); Fig. 2-8 is enlarged drawings of region in Fig. 2 (8); Fig. 2-9 is enlarged drawings of region in Fig. 2 (9); Fig. 2-10 is enlarged drawings of region in Fig. 2 (10); Fig. 2-11 is enlarged drawings of region in Fig. 2 (11); Fig. 2-12 is enlarged drawings of region in Fig. 2 (12); Fig. 2-13 is enlarged drawings of region in Fig. 2 (13); Fig. 2-14 is enlarged drawings of region in Fig. 2 (14); Fig. 2-15 is enlarged drawings of region in Fig. 2 (15).

BM3803MGRH, by address wire [ADDR0 ~ ADDR27], data line [DATA0 ~ DATA31], chip select line SRAM_CS_0, SRAM_CS_1, ROM_CE0, ROM_CE1, is connected with the address wire of UT9Q512K32E-SWC, ACT-F512K32N-060P3Q, B8R512K8RH, data line, chip select line after driver SN74ALVC164245DGG drives; Crystal oscillator G1 provides 20MH reference clock to the clock pin D28 of BM3803MGRH; BM3803MGRH carries out level conversion by UART4 mouth (pin V2, W5), UART1 mouth (pin AH30, AM34) through MAX3232ESE chip, be converted to standard RS232 interface level, wherein UART4 mouth is debug port, in a debug state, UART4 mouth receives the debug command from host computer.UART1 mouth is common serial ports, and host computer carries out data transmission alternately; To be connected with satellite task electronic system communication by UART3 mouth (pin AB2, AC1); Because system does not need SCAN pattern, therefore G35, G31, E1 pin of SCAN function is connect 1K ohm pull down ground connection; Owing to not using 8 FLASH of band EDAC to guide, do not need to determine FLASH spatial dimension before activation, therefore AG3, AF4, AH2, AE5 pin of definition FLASHBANK size is connect 1K ohm pull down ground connection; Because three Clock Tree clock phases of BM3803MGRH are identical, without skewed clock, therefore AG1, AD6 pin of clock delay input connects 1K ohm pull down ground connection; G33, F28, A33, E29, K30 pin of the frequency multiplication multiple of control processor, control V4, W3 pin entering debugging mode; Due to the data width that external FLASH is 16, therefore PIO0 connects 1K ohm pull down resistance to ground, and PIO1 connects on 4.7K resistance and sockets 3.3V power supply; The G35 pin (BRDYN signal) of BM3803MGRH connects 1K ohm pull down resistance to ground, during input/output space read and write access, after the latent period of configuration, if BRDYN is after low level, terminates to wait for; N3 (BEXCN signal) pin connects 1K ohm pull down resistance to ground, the abnormal instruction of bus, and internal bus can receive errored response; U1 pin (DSUACT signal) 1K Ohmage of connecting connects LED to ground, and when BM3803MGRH enters debugging mode, U1 pin exports high level, drives V2LED lamp to light; P6 pin (ERRORN signal) 1K Ohmage of connecting connects LED to 3.3V power supply, and when processor run-time error, P6 pin is low level, and V3LED lamp is lighted; Same AB6 pin (WDOGN signal) 1K Ohmage of connecting connects LED to 3.3V power supply, and when processor house dog is overflowed, AB6 pin is low level, and V4LED lamp is lighted; P4 pin (RESETN signal) connects the pin two of reset chip MAX811T, during hand-reset, presses S2 button, makes BM3803MGRH processor reset; Because native system does not need pci bus to transmit data, therefore AM4 pin PCI_CLK clock signal, AK20 pin PCI_66 test signal are connect 10K ohm pull down to ground.DSUEN, DSUBRE, PLL_M0, PLL_M1, PLL_M2, PLL_M3, PLL_BP, PIO2 are received on toggle switch, carry out pull-up, drop-down selection, when DSUEN, DSUBRE pull-up, BM3803MGRH enters debugging mode, processor receives the order from serial ports 4, and when DSUEN, DSUBRE are drop-down, BM3803MGRH enters operational mode; The frequency multiplication multiple of PLL_M0, PLL_M1, PLL_M2, PLL_M3 placement processor, when PLL_M [3:0] is arranged to " 0001 ", M is 1; When being arranged to " 0010 ", M is 2; The rest may be inferred, when being arranged to " 1111 "; M is 15, PLL is when BYPASS pattern (PLL_BP is " 1 "), processor working frequency and Clock Multiplier Factor M have nothing to do, PLL is when mode of operation (PLL_BP is " 0 "), processor working frequency is that the output frequency of clock source is multiplied by Clock Multiplier Factor M and obtains, and now phaselocked loop input range is 2MHz-30MHz; By the pull-up of PIO2 mouth, drop-down come configuration ROM EDAC whether enable.Guide, so ROMBSD [0], ROMBSD [1], ROMBSD [2], ROMBSD [3] are respectively by 10K resistive pull-downs owing to not using 8 FLASH of band EDAC; Because three Clock Tree clock phases of BM3803MGRH are identical, without skewed clock, therefore SKEW [0], SKEW [1] are by pull down resistor ground connection; Due to the data width that external FLASH is 16, therefore PIO0 connects pull down resistor to ground, and PIO1 is connected by 4.7K resistance and sockets 3.3V power supply.

See Fig. 3, Fig. 4 and Fig. 5, the SRAM memory UT9Q512K32E-SWC be connected with BM3803MGRH, its data bit width is 32bit, 2M byte capacity, SRAM be used for scratch system run data, use two panels UT9Q512K32E-SWC, by BM3803MGRH chip selection signal H34 pin RAMSN [0], L31 pin RAMSN [1] through signal drived control CE, and T30 pin RWEN [0], M34 pin RAMOEN [0] carry out read-write operation through signal driving to SRAM.And store 8 SRAM memory B8R512K8RH of EDAC check code, by BM3803MGRH chip selection signal K34 pin RAMSN [2] control chip gating, and N33 pin RWEN [1], R35 pin RAMOEN [1] carry out read-write operation through signal driving to SRAM.

See Fig. 6 and Fig. 7, the FLASH memory ACT-F512K32N-060P3Q be connected with BM3803MGRH, its data bit width is 32bit, data live width is 32bit, 2M byte capacity, FLASH is used for storing operating system, application program and beam-control code data, approximately need the FLASH of 4M byte, therefore use two panels ACT-F512K32N-060P3Q, by BM3803MGRH chip selection signal U35 pin ROMSN [0], V30 pin ROMSN [1] is through signal drived control control chip gating, and K32 pin WRITEn signal, J31 pin READ signal drives through signal and carries out read-write operation to SRAM.

See Fig. 8, be the debug serial port of BM3803MGRH, by MAX3232ESE, Transistor-Transistor Logic level converted to RS232 level, when DSUEN, DSUBRE pull-up, processor enters debugging mode, and to be connected with computer by serial interface cable and to debug, processor receives the debug command of host computer.

See Fig. 9, the communication succession figure of wave beam ripple control computer and the unit of ripple control out of my cabin, TR_R and TR_T is receiving cable gating pulse and the transmission channel gating pulse of T/R assembly, wave beam ripple control computer sends data DATA1 at CLK rising edge, data are transmitted between SYN low period, after T/R assembly completes beam-control code reception, when REDAY low level, new beam position comes into force.DATA2 is the digital telemetry data that Beamsteering Unit sends, and between FLAG low period, CLK negative edge receives data.

See Figure 10, it is the software communication interface protocol of ripple control computer and satellite task electronic system, " length ", " function number " in structure, " check and " are indispensable byte, and length n equals the byte number of all information not comprising two " prefixs " in framework.Therefore, 3≤n≤255,0≤function number≤255, check and=-(length+function number+content 1+ ... + content i), " content 1 " ... the particular content of " content n " byte can be defined as various command information, pattern information, (β, α) value etc. according to the requirement of each system.

Present invention achieves beam guidance computer is crossed satellite platform application by ground surface platform.Complete according to (β, α) beam pointing-angle, calculate the generation of the phase shift code of each phase shifter on antenna array, the decay code of attenuator, the time delay code of time delay amplifier, the present invention will meet reliability application under single particle effect under the complex environment of cosmic space, total dose effect, surperficial discharge and recharge, vacuum condition, whole beam guidance computer circuit board needs to adopt following design tactics: select the aerospace level device with radioresistance index, and use device derate; Carry out the Allowance Design of circuit, component parameter is changed within the specific limits, the product failure caused because this change causes circuit performance to drift about can not be caused; EDAC technology is adopted to carry out EDC error detection and correction to single-particle inversion; Heat loss through conduction is carried out to heater members.Satellite-borne wave beam computer for controlling, can be widely used in the fields such as telstar, instrumented satellite and reconnaissance satellite.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a satellite-borne wave beam computer for controlling, is characterized in that, it SRAM memory, FLASH memory, interface circuit, driving circuit of comprising processor MCU and being all electrically connected with processor MCU; Wherein, processor MCU is BM3803MGRH chip, SRAM memory is 2 UT9Q512K32E-SWC chips and 1 B8R512K8RH chip, and FLASH memory is 2 ACT-F512K32N-060P3Q chips, and driving circuit adopts driver SN74ALVC164245DGG chip.

2. satellite-borne wave beam computer for controlling as claimed in claim 1, it is characterized in that: BM3803MGRH chip, by its address wire [ADDR0 ~ ADDR27], data line [DATA0 ~ DATA31], chip select line SRAM_CS_0, SRAM_CS_1, ROM_CE0, ROM_CE1, is connected with UT9Q512K32E-SWC chip, ACT-F512K32N-060P3Q chip, the address wire of B8R512K8RH chip, data line, chip select line after driver SN74ALVC164245DGG chip drives.

3. satellite-borne wave beam computer for controlling as claimed in claim 2, it is characterized in that: interface circuit is standard RS232 interface, adopt MAX3232ESE chip, BM3803MGRH chip carries out level conversion by the UART4 mouth of its pin V2, W5, the UART1 mouth of pin AH30, AM34 through MAX3232ESE chip, be converted to standard RS232 interface level, wherein UART4 mouth is debug port, in a debug state, UART4 mouth receives the debug command from host computer, UART1 mouth is common serial ports, and host computer carries out data transmission alternately; To be connected with satellite task electronic system communication by the UART3 mouth of pin AB2, AC1 of BM3803MGRH chip.

4. satellite-borne wave beam computer for controlling as claimed in claim 3, is characterized in that: AG1, AD6 pin of the clock delay input of BM3803MGRH chip connects 1K ohm pull down ground connection; G33, F28, A33, E29, K30 pin of the frequency multiplication multiple of BM3803MGRH chip, control V4, W3 pin entering debugging mode.

5. satellite-borne wave beam computer for controlling as claimed in claim 4, it is characterized in that: the G35 pin of BM3803MGRH connects 1K ohm pull down resistance to ground, during input/output space read and write access, after the latent period of configuration, if BRDYN is after low level, terminate to wait for that the N3 pin of BM3803MGRH chip connects 1K ohm pull down resistance to ground, the abnormal instruction of bus, internal bus can receive errored response; The U1 pin series connection 1K Ohmage of BM3803MGRH chip connects LED to ground, and when BM3803MGRH chip enters debugging mode, U1 pin exports high level, drives V2LED lamp to light; The P6 pin series connection 1K Ohmage of BM3803MGRH chip connects LED to 3.3V power supply, and when processor run-time error, P6 pin is low level, and V3LED lamp is lighted; The AB6 pin series connection 1K Ohmage of same BM3803MGRH chip connects LED to 3.3V power supply, and when processor house dog is overflowed, AB6 pin is low level, and V4LED lamp is lighted.

6. satellite-borne wave beam computer for controlling as claimed in claim 5, it is characterized in that: pin DSUEN, DSUBRE, PLL_M0, PLL_M1, PLL_M2, PLL_M3, PLL_BP of BM3803MGRH chip are received on toggle switch, carry out pull-up, drop-down selection, when DSUEN, DSUBRE pull-up, BM3803MGRH enters debugging mode, processor receives the order from serial ports 4, and when DSUEN, DSUBRE are drop-down, BM3803MGRH enters operational mode.

7. satellite-borne wave beam computer for controlling as claimed in claim 6, it is characterized in that: the frequency multiplication multiple of pin PLL_M0, PLL_M1, PLL_M2, PLL_M3 placement processor MCU of BM3803MGRH chip, when PLL_M [3:0] is arranged to " 0001 ", M is 1; When being arranged to " 0010 ", M is 2; The rest may be inferred, when being arranged to " 1111 "; M is 15, PLL is when BYPASS pattern and PLL_BP are " 1 ", processor MCU frequency of operation and Clock Multiplier Factor M have nothing to do, PLL is when mode of operation and PLL_BP are " 0 ", processor MCU frequency of operation is that the output frequency of clock source is multiplied by Clock Multiplier Factor M and obtains, and now the phaselocked loop input range of processor MCU is 2MHz-30MHz.

8. satellite-borne wave beam computer for controlling as claimed in claim 7, it is characterized in that: the SRAM memory be connected with BM3803MGRH chip be used for scratch system run data, use two panels UT9Q512K32E-SWC chip, by chip selection signal H34 pin RAMSN [0] of BM3803MGRH chip, L31 pin RAMSN [1] is through signal drived control CE, and T30 pin RWEN [0], M34 pin RAMOEN [0] drives through signal and carries out read-write operation to SRAM, and store 8 SRAM memory B8R512K8RH of EDAC check code, by BM3803MGRH chip selection signal K34 pin RAMSN [2] control chip gating, and N33 pin RWEN [1], R35 pin RAMOEN [1] drives through signal and carries out read-write operation to SRAM.

9. satellite-borne wave beam computer for controlling as claimed in claim 8, it is characterized in that: the FLASH memory be connected with BM3803MGRH chip is used for storing operating system, application program and beam-control code data, use two panels ACT-F512K32N-060P3Q chip, by chip selection signal U35 pin ROMSN [0] of BM3803MGRH chip, V30 pin ROMSN [1] through signal drived control control chip gating, and K32 pin WRITEn signal, J31 pin READ signal drive through signal and carry out read-write operation to storer SRAM.

10. satellite-borne wave beam computer for controlling as claimed in claim 9, it is characterized in that: the debug serial port of BM3803MGRH chip, by MAX3232ESE chip, Transistor-Transistor Logic level is converted to RS232 level, when DSUEN, DSUBRE pull-up of BM3803MGRH chip, processor MCU enters debugging mode, to be connected with host computer by serial interface cable and to debug, processor MCU receives the debug command of host computer.