CN105097917A - LDMOS device and making method thereof - Google Patents
LDMOS device and making method thereof Download PDFInfo
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- CN105097917A CN105097917A CN201410186604.XA CN201410186604A CN105097917A CN 105097917 A CN105097917 A CN 105097917A CN 201410186604 A CN201410186604 A CN 201410186604A CN 105097917 A CN105097917 A CN 105097917A
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Abstract
The invention provides an LDMOS device and a making method thereof. The LDMOS device comprises a substrate, and gate structures, wherein the substrate is provided with drift regions and a well region; the gate structure is arranged on the surface of the substrate and comprises a gate oxide layer and a polysilicon layer, the gate oxide layer comprises a first gate oxide part and second gate oxide parts, the first gate oxide part is located on the surface of the substrate where the well region is, the distance between the upper surface of the first gate oxide part and the upper surface of the substrate is H1, the second gate oxide parts are located on the surfaces of the substrate where the drift regions are, the distance between the upper surface of each second gate oxide part and the upper surface of the substrate is H2, and H1 is smaller than H2. The second gate oxide parts located on the surface of the substrate where the drift regions are have large thickness, device breakdown caused by over large voltage can be effectively prevented; and in the condition in which the thickness of the first gate oxide part is unchanged, the thickness of the second gate oxide part can be added, and the breakdown voltage of the device can be improved in the condition in which the device size is unchanged.
Description
Technical field
The application relates to technical field of manufacturing semiconductors, in particular to a kind of LDMOS device and preparation method thereof.
Background technology
LDMOS (lateral double diffusion metal oxide semiconductor field effect) transistor arrangement is widely used in the eurypalynous transistor perhaps of such as high-pressure MOS field-effect transistor.
In prior art, ldmos transistor mainly contains two kinds of structures, and one is symmetrical LDMOS device, and another kind is asymmetric LDMOS device, and the position that its difference is mainly reflected in well region and drift region is arranged, and below with reference to accompanying drawing, above-mentioned two kinds of structures is described.
As shown in Figure 1, symmetrical LDMOS device comprises substrate 100 ', is arranged in the well region 102 ' of substrate 100 ' and symmetrically arranged two drift regions 101 ' centered by well region 102 ', grid structure 103 ' is also be that symmetry axis is arranged on well region 102 ' and two drift regions 101 ' symmetrically with the axis of well region 102 ', and similarly two side walls 104 ' and source electrode 105 ' and drain electrode 106 ' is also be that symmetry axis is arranged symmetrically with the axis of well region 102 '.
As shown in Figure 2, asymmetric LDMOS device comprises substrate 100 ', the well region 102 ' be arranged in substrate 100 ', the channel region be arranged in well region 102 ', the source electrode 105 ' connected by channel region and drain electrode 106 ' and cover channel region and affect the grid structure 103 ' of electron distributions in channel region and be positioned at the side wall 104 ' of grid structure 103 ' both sides, source electrode 105 ' is arranged in well region 102 ', and drain electrode 106 ' is arranged in drift region 101 '.
In the LDMOS pipe of above-mentioned two kinds of structures, grid structure 103 ' includes the gate oxide and polysilicon layer that arrange from bottom to top, and gate oxide wherein plays an important role preventing from puncturing in generation.Puncture voltage (BreakdownVoltage) weighs the important parameter of LDMOS device performance, typically refers to when ensureing not breakdown, the maximum voltage that can apply between grid and drain electrode 106 '.At present, the general puncture voltage adopting the thickness of the gate oxide increasing grid structure 103 ' to improve LDMOS in symmetrical structure, or the width increasing drift region 101 ' improves the puncture voltage of LDMOS, but the increase of gate oxide thickness and the increase of well region 102 ' width are all unfavorable for the reduction of device size.The drift region 101 ' arranged in asymmetric LDMOS device is mainly used in the distribution changing electric field in LDMOS, improve the puncture voltage of LDMOS, but if device architecture reduces further, it is not obvious to the raising effect of puncture voltage.
As can be seen here, prior art is difficult to the puncture voltage improving small size LDMOS pipe further, and therefore the restriction of puncture voltage becomes the obstacle being difficult to overcome reducing LDMOS tube device further.
Summary of the invention
The application aims to provide a kind of LDMOS device and preparation method thereof, to solve the problem that prior art small-medium size LDMOS device breakdown potential is forced down.
To achieve these goals, according to an aspect of the application, provide a kind of LDMOS device, this LDMOS device comprises: substrate, is provided with drift region and well region in substrate; Grid structure, arrange on a surface of the substrate, comprise gate oxide and polysilicon layer, gate oxide comprises: first grid oxidation section, is positioned on the surface of the substrate at well region place, and the distance of the upper surface of the upper surface distance substrate of first grid oxidation section is H
1; And second gate oxidation section, be positioned on the surface of the substrate at place, drift region, the distance of the upper surface of the upper surface distance substrate of second gate oxidation section is H
2, above-mentioned H
1be less than above-mentioned H
2.
Further, above-mentioned H
1above-mentioned H
260 ~ 95%.
Further, above-mentioned H
1be 50 ~ 390
, H
2be 50 ~ 400
.
Further, above-mentioned LDMOS device is symmetrical LDMOS device, and drift region comprises: the first drift region, is arranged on the side of well region; Second drift region, is arranged on the opposite side of well region symmetrically with the first drift region.
Further, above-mentioned LDMOS device also comprises: side wall, is arranged on the both sides extended along orientation of grid structure; Source electrode, to be arranged in the first drift region not by position that grid structure covers; Drain electrode, to be arranged in the second drift region not by position that grid structure covers.
Further, above-mentioned LDMOS device is asymmetric LDMOS device.
Further, above-mentioned LDMOS device also comprises: side wall, is arranged on the both sides extended along orientation of grid structure; Source electrode, to be arranged in well region not by position that grid structure covers; Drain electrode, to be arranged in drift region not by position that grid structure covers.
Further, above-mentioned substrate is P type substrate, and well region is P type trap zone, and drift region is the drift region of the shallow doping of N-type.
According to the another aspect of the application, provide a kind of manufacture method of LDMOS device, this manufacture method comprises: step S1, forms drift region and well region in the substrate, and carries out N~+ implantation to well region; Step S2, at Grown oxide; Step S3, on oxides deposit spathic silicon; And step S4, etching is carried out successively to polysilicon and oxide and forms grid structure, the gate oxide of grid structure is formed after oxide etching, the gate oxide be wherein positioned on the surface of the substrate at well region place is first grid oxidation section, the gate oxide be positioned on the surface of the substrate at place, drift region is second gate oxidation section, forms the polysilicon layer of grid structure after etching polysilicon.
Further, the dosage of above-mentioned N~+ implantation is 1E12 ~ 1E16/cm
3, energy is 1 ~ 100Kev, and the nitrogenous source of N~+ implantation is ammonia or nitrogen.
Further, above-mentioned steps S2 adopts Fast Heating oxidation technology or high temperature furnace pipe growth technique to implement.
Further, above-mentioned Fast Heating oxidation technology comprises: the substrate of completing steps S1 is warming up to 700 ~ 1000 DEG C; Substrate after heating up passes into oxygen, and substrate surface oxidation is formed oxide.
Further, above-mentioned steps S1 comprises: arrange the first photoresist mask on the surface of a substrate, and the first photoresist mask has the first opening in the position for forming drift region; First foreign ion injection is carried out to the substrate with the first photoresist mask, forms drift region; Remove the first photoresist mask; Arrange the second photoresist mask at the substrate surface with drift region, the second photoresist mask has the second opening in the position for forming well region; Second foreign ion injection is carried out to the substrate with the second photoresist mask, forms well region; N~+ implantation is carried out to well region; Remove the second photoresist mask, wherein, the first foreign ion and the second foreign ion are transoid ion.
Further, above-mentioned steps S1 comprises: arrange the second photoresist mask on the surface of a substrate, and the second photoresist mask has the second opening in the position for forming well region; Second foreign ion injection is carried out to the substrate with the second photoresist mask, forms well region; N~+ implantation is carried out to well region; Remove the second photoresist mask; Arrange the first photoresist mask at the substrate surface with well region, the first photoresist mask has the first opening in the position for forming drift region; First foreign ion injection is carried out to the substrate with the first photoresist mask, forms drift region; Remove the first photoresist mask, wherein, the first foreign ion and the second foreign ion are transoid ion.
Further, above-mentioned substrate is P type substrate, and the first foreign ion is N-type ion, and the second foreign ion is P type ion.
Further, above-mentioned manufacture method also comprises after formation of the gate structure: step S5, arranges side wall in the both sides along orientation extension of grid structure; Step S6, carries out the first foreign ion injection with grid structure and side wall for mask, forms source electrode and drain electrode.
The technical scheme of application the application, the thickness being arranged at drift region institute second gate oxidation section on the surface of a substrate comparatively greatly, therefore, it is possible to the voltage excessive device breakdown caused when effectively preventing LDMOS device from working; And be arranged at well region the thickness of first grid oxidation section on the surface of a substrate little compared with the thickness of second gate oxidation section, that is when ensureing that original device property is constant, namely when first grid oxidation section thickness is constant, second gate oxidation section thickness can be increased, thus the puncture voltage of device can be improved when device size is constant, therefore, the minor variations of above-mentioned gate oxide structure can not impact the size of LDMOS device, and is applicable to small size symmetry or asymmetric LDMOS device.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the cross-sectional view of symmetrical LDMOS device in prior art;
Fig. 2 shows the cross-sectional view of asymmetric LDMOS device in prior art;
Fig. 3 shows the cross-sectional view of the symmetrical LDMOS device that a kind of preferred implementation of the application provides;
Fig. 4 shows the cross-sectional view of the asymmetric LDMOS device that the another kind of preferred implementation of the application provides;
Fig. 5 shows the schematic flow sheet of the manufacture method of the LDMOS device that another preferred implementation of the application provides;
The device profile structural representation that Fig. 6 to Figure 11 obtains after illustrating and implementing each step shown in Fig. 5, wherein,
Fig. 6 shows the cross-sectional view after forming drift region in the substrate;
Fig. 7 shows the cross-sectional view to form well region in substrate shown in Fig. 6 after;
Fig. 8 shows and carries out the cross-sectional view after N~+ implantation to well region shown in Fig. 7;
Fig. 9 shows the cross-sectional view after the Grown oxide shown in Fig. 8;
Figure 10 shows the cross-sectional view on the oxide shown in Fig. 9 after deposit spathic silicon;
Figure 11 shows and carries out etching the cross-sectional view after forming grid structure successively to the polysilicon shown in Figure 10 and oxide;
Figure 12 shows the cross-sectional view after the both sides along orientation extension of the grid structure shown in Figure 11 arrange side wall; And
Figure 13 shows and injects the cross-sectional view after forming source electrode and drain electrode with the grid structure shown in Figure 12 and side wall for mask carries out the first foreign ion.
Embodiment
It is noted that following detailed description is all exemplary, be intended to provide further instruction to the application.Unless otherwise, all technology used herein and scientific terminology have the identical meanings usually understood with the application person of an ordinary skill in the technical field.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Introduce as background technology, prior art is difficult to the puncture voltage improving small size LDMOS pipe further, in order to solve as above problem, present applicant proposes LDMOS device and preparation method thereof.
The application's one preferred embodiment in, provide a kind of LDMOS device, as shown in Figure 3 and Figure 4, this LDMOS device comprises substrate 100 and grid structure 103, drift region 101 and well region 102 is provided with in substrate 100, grid structure 103 is arranged on the surface of substrate 100, comprise gate oxide 131 and polysilicon layer 132, gate oxide 131 comprises first grid oxidation section 311 and second gate oxidation section 312, first grid oxidation section 311 is positioned on the surface of the substrate 100 at well region 102 place, and the distance of the upper surface of the upper surface of first grid oxidation section 311 distance substrate 100 is H
1, second gate oxidation section 312 is positioned on the surface of the substrate 100 at place, drift region 101, and the distance of the upper surface of the upper surface of second gate oxidation section 312 distance substrate 100 is H
2wherein, H
1be less than H
2.
Have the LDMOS device of said structure, the thickness being arranged at the second gate oxidation section 312 on substrate 100 surface, place, drift region 101 is comparatively large, therefore, it is possible to the voltage excessive device breakdown caused when effectively preventing LDMOS device from working; And be arranged at well region 102 the thickness (H of first grid oxidation section 311 on the surface of a substrate
1) compared with the thickness (H of second gate oxidation section 312
2) little, the size of LDMOS device can not be caused to increase, that is when ensureing that original device property is constant, namely when first grid oxidation section 311 thickness is constant, second gate oxidation section 312 thickness can be increased, thus the puncture voltage of device can be improved when device size is constant, therefore, the minor variations of above-mentioned gate oxide 131 structure can not impact the size of LDMOS device, and is applicable to small size symmetry or asymmetric LDMOS device.
The thickness that the application has gate oxide in the thickness of the second gate oxidation section 312 of the gate oxide 131 of the LDMOS device of said structure and current LDMOS device is suitable, preferred H
1described H
260 ~ 95%.Further preferred above-mentioned H
1be 50 ~ 390
, H
2be 50 ~ 400
.
Described by background technology, in prior art, LDMOS device mainly contains symmetrical LDMOS device and asymmetric LDMOS device, and the above-mentioned grid structure 103 of the application is applicable to above-mentioned two kinds of LDMOS device.
When LDMOS device is symmetrical LDMOS device, drift region 101 comprises the side that the first drift region 111 and the second drift region 111, drift region 112, first are arranged on well region 102; Second drift region 112 and the first drift region 111 are arranged on the opposite side of well region 102 symmetrically.Thickness corresponding to the second gate oxidation section 312 of the first drift region 111 and the second drift region 112 is all greater than the thickness of first grid oxidation section 311.In addition, preferred above-mentioned LDMOS device also comprises side wall 104, source electrode 105 and drain electrode 106, and side wall 104 is arranged on the both sides extended along orientation of grid structure 103; Source electrode 105 to be arranged in the first drift region 111 not by position that grid structure 103 covers; Drain electrode 106 to be arranged in the second drift region 112 not by position that grid structure 103 covers.
When LDMOS device is asymmetric LDMOS device, the thickness corresponding to the second gate oxidation section 312 of drift region 101 is greater than the thickness of first grid oxidation section 311.In addition, preferred LDMOS device also comprises side wall 104, source electrode 105 and drain electrode 106, and side wall 104 is arranged on the both sides extended along channel width dimension of grid structure 103; Source electrode 105 to be arranged in well region 102 not by position that grid structure 103 covers; Drain electrode 106 to be arranged in drift region 101 not by position that grid structure 103 covers.
The material being used as semiconductor device substrates that the substrate 100 of the application can adopt this area to commonly use, preferred above-mentioned substrate 100 is P type substrate, and well region 102 is P type trap zone, and drift region 101 is the drift region of the shallow doping of N-type.
In the application's another preferred embodiment, provide a kind of manufacture method of LDMOS device, wherein figure 5 show the schematic flow sheet of this manufacture method, this manufacture method comprises: step S1, in substrate 100, form drift region 101 and well region 102, and N~+ implantation is carried out to well region 102; Step S2, on the substrate 100 grow oxide 131 '; Step S3, at the upper deposit spathic silicon 132 ' of oxide 131 '; And step S4, etching is carried out successively to polysilicon 132 ' and oxide 131 ' and forms grid structure 103, after oxide 131 ' etches, form the gate oxide 131 of grid structure 103, after polysilicon 132 ' etches, form the polysilicon layer 132 of grid structure 103.
Above-mentioned manufacture method, N~+ implantation is carried out at well region 102, make well region 102 surface or portion doped with Nitrogen ion, form N~+ implantation district 121, and then when oxidation growth forms oxide 131 ', because the Nitrogen ion had in N~+ implantation district 121 consumes part oxygen atom, nitrogen oxide can be formed when thermal oxidation, the compactness of nitrogen oxide is better than the compactness of silicon dioxide, makes oxygen atom be not easy to spread in silicon substrate, thus slow down the speed of growth of silica; And the substrate that the substrate 100 outside well region 102 comprises drift region 101 does not have the speed of the injection of Nitrogen ion therefore its oxidation growth to remain unchanged, so under same oxidation growth condition, the thickness of the oxide formed above well region 102 is less than the thickness of the oxide formed above drift region 101, by regulating the condition of oxidation growth, control the thickness of the oxide 131 ' formed.Said process increases the step of N~+ implantation in existing technique, the enforcement of other processing steps can not be affected, and not needing extra mask plate during N~+ implantation, mask set when utilizing well region 102 to inject after completing well region 102 and injecting is as the mask of N~+ implantation.
The thickness difference of oxide 131 ' on well region 102 and drift region 101 can regulate according to the concentration of N~+ implantation, the object of above-mentioned N~+ implantation mainly affects the growth of subsequent oxidation thing 131 ', therefore it injects the degree of depth can not need too dark, the application improves puncture voltage and does not increase the size of LDMOS device on the basis of the satisfied isolation of oxide 131 ', and the dosage of preferred above-mentioned N~+ implantation is 1E12 ~ 1E16/cm
3, energy is 1 ~ 100Kev, nitrogenous source used be nitrogen, ammonia etc. ionizable go out the material of Nitrogen ion.Those skilled in the art are noted that above-mentioned ion implantation process not only comprises and N~+ implantation be can further include the process of annealing to substrate 100 to the process of well region 102, the temperature of preferred above-mentioned annealing is 900 ~ 1200 DEG C, and the time is 5 ~ 20s.
Now, by for the structure of symmetrical LDMOS device, with reference to accompanying drawing, the illustrative embodiments according to the application is described in more detail.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
First, in substrate 100, form the drift region 101 shown in Fig. 7 and well region 102, and N~+ implantation is carried out to the well region 102 in Fig. 7, form N~+ implantation district 121 (see Fig. 8), form the device with cross-section structure shown in Fig. 8.
Said process can be sequentially different according to the formation of drift region 101 and well region 102.Such as, first form drift region 101, rear formation well region 102, this process comprises: the first photoresist mask 201, the first photoresist mask 201 arranged on the surface as shown in Figure 6 at substrate 100 has the first opening in the position for forming drift region 101; First foreign ion injection is carried out to the substrate 100 with the first photoresist mask 201, forms drift region 101 as shown in Figure 6; Remove the first photoresist mask 201; The second photoresist mask 202, the second photoresist mask 202 arranged as shown in Figure 7 on substrate 100 surface with drift region 101 has the second opening in the position for forming well region 102; Second foreign ion injection is carried out to the substrate 100 with the second photoresist mask 202, forms well region 102 as shown in Figure 7; N~+ implantation is carried out to the well region 102 shown in Fig. 7; Remove the second photoresist mask 202, wherein, the first foreign ion and the second foreign ion are transoid ion.Said process, after formation well region 102, utilizes the region outside the second photoresist mask 202 pairs of well regions 102 to protect, and carries out N~+ implantation form N~+ implantation district 121 to well region 102.
Certainly, the application forms drift region 101 after also first can forming well region 102, and this process comprises: arrange the second photoresist mask 202, second photoresist mask 202 on the surface at substrate 100 and have the second opening in the position for forming well region 102; Second foreign ion injection is carried out to the substrate 100 with the second photoresist mask 202, forms well region 102; N~+ implantation is carried out to well region 102; Remove the second photoresist mask 202; First photoresist mask 201, first photoresist mask 201 is set on substrate 100 surface with well region 102 and in the position for forming drift region 101, there is the first opening; First foreign ion injection is carried out to the substrate 100 with the first photoresist mask 201, forms drift region 101; Remove the first photoresist mask 201, wherein, the first foreign ion and the second foreign ion are transoid ion.Region outside the second photoresist mask 202 pairs of well regions 102 of same utilization formation well region 102 is protected, and carries out N~+ implantation form N~+ implantation district 121 to well region 102.
In order to realize the due function of LDMOS device, in said process, the first foreign ion and the second foreign ion are transoid ion.Namely, when the first foreign ion is for providing the P type ion in hole, the second foreign ion is for providing the N-type ion of free electron; Otherwise when the first foreign ion is for providing the N-type ion of free electron, the second foreign ion is for providing the P type ion in hole.The preferred above-mentioned substrate 100 of the application is P type substrate, and the first foreign ion is N-type ion, and the second foreign ion is P type ion.
After completing above-mentioned N~+ implantation, the Grown oxide 131 ' shown in Fig. 8, obtains having the device of cross-section structure shown in Fig. 9.As seen from Figure 9, the thickness being positioned at the oxide 131 ' above drift region 101 is greater than the thickness of the oxide 131 ' being positioned at well region 102 (N~+ implantation district 121) top, and Crack cause is as described above, does not repeat them here.
The growth of above-mentioned oxide 131 ' preferably adopts Fast Heating oxidation technology or high temperature furnace pipe growth technique to implement.No matter be adopt Fast Heating oxidation technology or adopt high temperature furnace pipe growth technique, those skilled in the art all can implement with reference to current process conditions, the application is preferably when adopting Fast Heating oxidation technology, and this technique comprises: the substrate 100 of completing steps S1 is warming up to 700 ~ 1000 DEG C; Substrate 100 after heating up passes into oxygen, and substrate 100 surface oxidation is formed oxide.Between 700 ~ 1000 DEG C, implement oxidation, make the compactness of the oxide 131 ' obtained better.
After completing the growth of above-mentioned oxide 131 ', the upper deposit spathic silicon 132 ' of the oxide 131 ' shown in Fig. 9, obtains having the device of cross-section structure shown in Figure 10.The chemical vapour deposition (CVD) that above-mentioned deposition process can adopt this area conventional, physical vapour deposition (PVD) or the mode such as plasma-deposited are implemented, and do not repeat them here.
After completing the deposition of above-mentioned polysilicon 132 ', polysilicon 132 ' shown in Figure 10 and oxide 131 ' are etched successively, form the grid structure 103 shown in Figure 11, wherein oxide 131 ' forms the gate oxide 131 of grid structure 103 after etching, and forms the polysilicon layer 132 of grid structure 103 after polysilicon 132 ' etches.This etching process adopts selective wet chemical etching or chemical drying method etching all can implement, and the application preferably adopts has the enforcement of anisotropic dry etching.
After the above-mentioned grid structure 103 of formation, the manufacture method of the application preferably also comprises: step S5, and the both sides along orientation extension of the grid structure 103 shown in Figure 11 arrange the side wall 104 shown in Figure 12; Step S6, carries out the first foreign ion injection with the grid structure 103 shown in Figure 12 and side wall 104 for mask, forms the source electrode 105 shown in Figure 13 and drain electrode 106.
Said process all can adopt existing common process to implement, and can not cause damage to the grid structure 103 formed, the grid structure 103 formed also can not have a negative impact to the enforcement of said process.
It is more than the explanation carried out for the manufacturing process of symmetrical LDMOS device, under the guidance of foregoing and in conjunction with prior art, the completely capable manufacture craft implementing asymmetric LDMOS device of those skilled in the art, the application does not repeat them here the manufacture method of asymmetric LDMOS device.
As can be seen from the above description, the application's the above embodiments achieve following technique effect:
1), the LDMOS device of the application, be arranged at drift region the thickness of second gate oxidation section on the surface of a substrate comparatively large, therefore, it is possible to the voltage excessive device breakdown caused when effectively preventing LDMOS device from working; And be arranged at well region the thickness of first grid oxidation section on the surface of a substrate little compared with the thickness of second gate oxidation section, the size of LDMOS device can not be caused to increase, that is when ensureing that original device property is constant, namely when first grid oxidation section thickness is constant, second gate oxidation section thickness can be increased, thus the puncture voltage of device can be improved when device size is constant, therefore, the minor variations of above-mentioned gate oxide structure can not impact the size of LDMOS device, and is applicable to small size symmetry or asymmetric LDMOS device;
2), said process increases the step of N~+ implantation in existing technique, the enforcement of other processing steps can not be affected, and not needing extra mask plate during N~+ implantation, mask set when utilizing well region to inject after completing well region and injecting is as the mask of N~+ implantation.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (16)
1. a LDMOS device, described LDMOS device comprises:
Substrate, is provided with drift region and well region in described substrate;
Grid structure, is arranged on the surface of described substrate, comprises gate oxide and polysilicon layer, and described gate oxide comprises:
First grid oxidation section, is positioned on the surface of the described substrate at described well region place, and the upper surface of described first grid oxidation section is H apart from the distance of the upper surface of described substrate
1; And
Second gate oxidation section, is positioned on the surface of the described substrate at place, described drift region, and the upper surface of described second gate oxidation section is H apart from the distance of the upper surface of described substrate
2,
It is characterized in that, described H
1be less than described H
2.
2. LDMOS device according to claim 1, is characterized in that, described H
1described H
260 ~ 95%.
3. LDMOS device according to claim 1, is characterized in that, described H
1be 50 ~ 390
, described H
2be 50 ~ 400
.
4. LDMOS device according to claim 1, is characterized in that, described LDMOS device is symmetrical LDMOS device, and described drift region comprises:
First drift region, is arranged on the side of described well region;
Second drift region, is arranged on the opposite side of described well region symmetrically with described first drift region.
5. want the LDMOS device described in 4 according to right, it is characterized in that, described LDMOS device also comprises:
Side wall, is arranged on the both sides extended along orientation of described grid structure;
Source electrode, to be arranged in described first drift region not by position that described grid structure covers;
Drain electrode, to be arranged in described second drift region not by position that described grid structure covers.
6. LDMOS device according to claim 1, is characterized in that, described LDMOS device is asymmetric LDMOS device.
7. LDMOS device according to claim 6, is characterized in that, described LDMOS device also comprises:
Side wall, is arranged on the both sides extended along orientation of described grid structure;
Source electrode, to be arranged in described well region not by position that described grid structure covers;
Drain electrode, to be arranged in described drift region not by position that described grid structure covers.
8. LDMOS device according to any one of claim 1 to 7, is characterized in that, described substrate is P type substrate, and described well region is P type trap zone, and described drift region is the drift region of the shallow doping of N-type.
9. a manufacture method for LDMOS device, is characterized in that, described manufacture method comprises:
Step S1, forms drift region and well region in the substrate, and carries out N~+ implantation to described well region;
Step S2, over the substrate grow oxide;
Step S3, deposit spathic silicon on described oxide; And
Step S4, etching is carried out successively to described polysilicon and described oxide and forms grid structure, the gate oxide of described grid structure is formed after described oxide etching, the gate oxide be wherein positioned on the surface of the described substrate at described well region place is first grid oxidation section, the gate oxide be positioned on the surface of the described substrate at place, described drift region is second gate oxidation section, forms the polysilicon layer of described grid structure after described etching polysilicon.
10. manufacture method according to claim 9, is characterized in that, the dosage of described N~+ implantation is 1E12 ~ 1E16/cm
3, energy is 1 ~ 100Kev, and the nitrogenous source of described N~+ implantation is ammonia or nitrogen.
11. manufacture methods according to claim 9, is characterized in that, described step S2 adopts Fast Heating oxidation technology or high temperature furnace pipe growth technique to implement.
12. manufacture methods according to claim 11, is characterized in that, described Fast Heating oxidation technology comprises:
The described substrate completing described step S1 is warming up to 700 ~ 1000 DEG C;
Pass into oxygen to the substrate after described intensification, described substrate surface oxidation is formed described oxide.
13. manufacture methods according to claim 9, is characterized in that, described step S1 comprises:
Described substrate surface arranges the first photoresist mask, and described first photoresist mask has the first opening in the position for forming drift region;
First foreign ion injection is carried out to the described substrate with described first photoresist mask, forms described drift region;
Remove described first photoresist mask;
Arrange the second photoresist mask at the described substrate surface with described drift region, described second photoresist mask has the second opening in the position for forming described well region;
Second foreign ion injection is carried out to the described substrate with described second photoresist mask, forms described well region;
N~+ implantation is carried out to described well region;
Remove described second photoresist mask, wherein, described first foreign ion and described second foreign ion are transoid ion.
14. manufacture methods according to claim 9, is characterized in that, described step S1 comprises:
Described substrate surface arranges the second photoresist mask, and described second photoresist mask has the second opening in the position for forming well region;
Second foreign ion injection is carried out to the described substrate with described second photoresist mask, forms described well region;
N~+ implantation is carried out to described well region;
Remove described second photoresist mask;
Arrange the first photoresist mask at the described substrate surface with described well region, described first photoresist mask has the first opening in the position for forming described drift region;
First foreign ion injection is carried out to the described substrate with described first photoresist mask, forms described drift region;
Remove described first photoresist mask, wherein, described first foreign ion and described second foreign ion are transoid ion.
15. manufacture methods according to claim 13 or 14, it is characterized in that, described substrate is P type substrate, and described first foreign ion is N-type ion, and described second foreign ion is P type ion.
16. manufacture methods according to claim 9, is characterized in that, described manufacture method also comprises after the described grid structure of formation:
Step S5, arranges side wall in the both sides along orientation extension of described grid structure;
Step S6, carries out the first foreign ion injection with described grid structure and described side wall for mask, forms source electrode and drain electrode.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729242A (en) * | 2018-07-17 | 2020-01-24 | 上海宝芯源功率半导体有限公司 | Semiconductor switch device and manufacturing method thereof |
| CN112216745A (en) * | 2020-12-10 | 2021-01-12 | 北京芯可鉴科技有限公司 | High-voltage asymmetric LDMOS device and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147008A (en) * | 1999-11-19 | 2000-11-14 | Chartered Semiconductor Manufacturing Ltd. | Creation of multiple gate oxide with high thickness ratio in flash memory process |
| CN101447432A (en) * | 2007-11-27 | 2009-06-03 | 上海华虹Nec电子有限公司 | Manufacturing method of double diffusion field effect transistor |
| CN101752251A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Fully-automatic aligning high-pressure N-shaped DMOS device and manufacturing method thereof |
| CN102479712A (en) * | 2010-11-29 | 2012-05-30 | 无锡华润上华半导体有限公司 | Method for manufacturing double-gate oxide semiconductor device |
-
2014
- 2014-05-05 CN CN201410186604.XA patent/CN105097917A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147008A (en) * | 1999-11-19 | 2000-11-14 | Chartered Semiconductor Manufacturing Ltd. | Creation of multiple gate oxide with high thickness ratio in flash memory process |
| CN101447432A (en) * | 2007-11-27 | 2009-06-03 | 上海华虹Nec电子有限公司 | Manufacturing method of double diffusion field effect transistor |
| CN101752251A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Fully-automatic aligning high-pressure N-shaped DMOS device and manufacturing method thereof |
| CN102479712A (en) * | 2010-11-29 | 2012-05-30 | 无锡华润上华半导体有限公司 | Method for manufacturing double-gate oxide semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729242A (en) * | 2018-07-17 | 2020-01-24 | 上海宝芯源功率半导体有限公司 | Semiconductor switch device and manufacturing method thereof |
| CN112216745A (en) * | 2020-12-10 | 2021-01-12 | 北京芯可鉴科技有限公司 | High-voltage asymmetric LDMOS device and preparation method thereof |
| CN112216745B (en) * | 2020-12-10 | 2021-03-09 | 北京芯可鉴科技有限公司 | High-voltage asymmetric LDMOS device and preparation method thereof |
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