CN105097844A - Thin film transistor array substrate, manufacture method thereof and liquid crystal display device - Google Patents
Thin film transistor array substrate, manufacture method thereof and liquid crystal display device Download PDFInfo
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- CN105097844A CN105097844A CN201510514177.8A CN201510514177A CN105097844A CN 105097844 A CN105097844 A CN 105097844A CN 201510514177 A CN201510514177 A CN 201510514177A CN 105097844 A CN105097844 A CN 105097844A
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Abstract
The invention relates to a thin film transistor array substrate and a manufacture method thereof. The thin film transistor array substrate comprises a substrate, a first metal layer, a first insulating protective layer, a semiconductor layer, a second metal layer, a second insulating protective layer, a first conductive layer, a third insulating protective layer and a second conductive layer; the second metal layer includes a source, a drain and a data line; the first conductive layer comprises a conductive connecting part which transversely spans the data line; a first through hole corresponding to the conductive connecting part is formed in the third insulating protective layer; a second through hole corresponding to the drain, is formed in the third insulating protective layer and the second insulating protective layer; the second conductive layer includes a first part and a second part which are arranged separately, wherein the first part is correspondingly located above the data line and extends forwards along the data line, and the second part fills the first through hole and contacts with the conductive connecting pat so as to realize electric connection; the first conductive layer and the first part commonly form a first electrode; the second part fills the second through hole and contacts with the drain so as to realize electric connection; and the second part forms a second electrode.
Description
Technical field
The present invention relates to technical field of liquid crystal display, and particularly relate to a kind of thin-film transistor array base-plate and preparation method thereof, and there is the liquid crystal indicator of this thin-film transistor array base-plate.
Background technology
Liquid crystal display (LCD, LiquidCrystalDisplay) is a kind of flat-panel screens be widely used at present, compares with other display modes, has the advantages such as low-power consumption, external form be thin, lightweight, radiationless.Generally speaking, the LCD liquid crystal layer that comprises thin-film transistor array base-plate, color membrane substrates and be filled between thin-film transistor array base-plate and color membrane substrates.Viewing area on thin-film transistor array base-plate comprises multiple subpixel area, each subpixel area is generally two gate lines (also known as scan line) and two data wires and intersects formed rectangle or other shape area, be provided with thin-film transistor and pixel electrode in it, thin-film transistor serves as switch element; Common electrode on color membrane substrates and the common electrode between the pixel electrode on thin-film transistor array base-plate or on thin-film transistor array base-plate and the electric field strength between pixel electrode modulate the yawing moment of liquid crystal molecule.
The distribution of LCD comprises data wire, gate line, repair line etc.Due to the resistance that distribution itself exists, and the electric capacity formed between common electrode on the electric capacity between this layer of distribution and other conductive layer of thin-film transistor array base-plate, this layer of distribution and color membrane substrates, make distribution there is signal delay.Along with the increase of LCD board size and the raising of resolution, the signal delay of the distribution of LCD also can increase thereupon.And excessive signal delay can affect the brightness, contrast etc. of liquid crystal display, thus reduce display quality.As the signal delay on data wire then can affect the signal voltage be added on liquid crystal layer, thus affect display characteristic.
Fig. 1 is the planar structure schematic diagram of the thin-film transistor array base-plate of existing a kind of liquid crystal indicator, Fig. 2 is the cross-sectional view along II-II line of the thin-film transistor array base-plate shown in Fig. 1, refer to Fig. 1 and Fig. 2, thin-film transistor array base-plate 1 comprises multi-strip scanning line and a plurality of data lines, and multi-strip scanning line and a plurality of data lines are mutually intersected and limited multiple pixel region, scan line and data wire crossover location place are provided with thin-film transistor.Existing thin-film transistor array base-plate 1 comprises underlay substrate 10, grid 11, first insulating protective layer 12 be formed on underlay substrate 10, semiconductor layer 13, source electrode 14a, drain electrode 14b, data wire 14c, the second insulating protective layer 15, first electrode 16, the 3rd insulating protective layer 17 and the second electrode 18.First insulating protective layer 12 is formed on underlay substrate 10.Data wire 14c is formed on the first insulating protective layer 12.Second insulating protective layer 15 is formed on the first insulating protective layer 12, and cover data line 14c.First electrode 16 is formed on the second insulating protective layer 15.3rd insulating protective layer 17 covers the first electrode 16.Second electrode 18 is formed on the 3rd insulating protective layer 17.One deck second insulating protective layer 15 is only provided with between data wire 14c and the first electrode 16; make the distance between data wire 14c and the first electrode 16 less; cause the electric capacity between data wire 14c and the first electrode 16 comparatively large, thus increase the total capacitance on the electrode of thin-film transistor array base-plate.Timeconstantτ based on signal delay is proportional to the product of total capacitance and all-in resistance, when the all-in resistance of thin-film transistor array base-plate remains unchanged substantially, and total capacitance larger time, cause the signal delay of this thin-film transistor array base-plate to increase, thus impact have the display characteristic of the display unit of this thin-film transistor array base-plate.
Summary of the invention
The invention provides a kind of thin-film transistor array base-plate, it contributes to improving the penetrance of liquid crystal indicator and reduces the signal delay of liquid crystal indicator.
The invention provides a kind of manufacture method of thin-film transistor array base-plate, the thin-film transistor array base-plate made by it contributes to improving the penetrance of liquid crystal indicator and reduces the signal delay of liquid crystal indicator.
The invention provides a kind of liquid crystal indicator, it has higher penetrance and less signal delay.
It is adopt following technical scheme to realize that the present invention solves its technical problem.
A kind of thin-film transistor array base-plate, comprises underlay substrate, the first metal layer, the first insulating protective layer, semiconductor layer, the second metal level, the second insulating protective layer, the first conductive layer, the 3rd insulating protective layer and the second conductive layer.The first metal layer is formed on this underlay substrate.This first metal layer comprises grid and scan line.First insulating protective layer to be formed on this underlay substrate and to cover this first metal layer.Semiconductor layer to be formed on this first insulating protective layer and to be positioned at above this grid.Second metal level is formed on this first insulating protective layer; this second metal level comprises source electrode, drain electrode and data wire; this source electrode is separate with this drain electrode and contact with this semiconductor layer respectively; a part for this semiconductor layer is exposed between this source electrode and this drain electrode; this data wire is connected with this source electrode, intersects to form multiple pixel cell by many these scan lines and many these data wires.Second insulating protective layer to be formed on this first insulating protective layer and to cover this source electrode, this drain electrode, this data wire and from this semiconductor layer of the part exposed between this source electrode and this drain electrode.First conductive layer is formed on this second insulating protective layer, and this first conductive layer comprises the conductive connection part across this data wire.3rd insulating protective layer is formed on this first conductive layer; 3rd insulating protective layer is in the position of conductive connection part having the first through hole with this conductive connection part of exposed portion, and the 3rd insulating protective layer and this second insulating barrier are in the position that should drain being had to the second through hole with this drain electrode of exposed portion.Second conductive layer is formed on the 3rd insulating protective layer, this second conductive layer comprises Part I and the Part II of separate setting, this Part I correspondence is positioned at above this data wire and this data wire of postponing is arranged, this Part I is also inserted in this first through hole to contact with this conductive connection part and is realized being electrically connected, the first electrode is jointly formed by this Part I of this first conductive layer and this second conductive layer, this first electrode is public electrode, this Part II is arranged in corresponding pixel cell and also inserts this second through hole and realizes being electrically connected with this drain contact, this Part II forms the second electrode, this second electrode is pixel electrode.
In present pre-ferred embodiments; this first conductive layer is in the position of data wire forming the first breach to expose this second insulating protective layer of below, and the 3rd insulating protective layer be formed on this first conductive layer is also inserted in this first breach and contacted with this second insulating protective layer.
In present pre-ferred embodiments; this first conductive layer forms the second breach to expose this second insulating protective layer of below in the position at corresponding thin-film transistor place, the 3rd insulating protective layer be formed on this first conductive layer is also inserted in this second breach and contacted with this second insulating protective layer.
In present pre-ferred embodiments, the Part I of this second conductive layer is the list structure corresponding with this data wire and covers this data wire.
A kind of liquid crystal indicator, comprises above-mentioned thin-film transistor array base-plate.
A manufacture method for thin-film transistor array base-plate, comprising: make on underlay substrate and form the first metal layer, this first metal layer comprises grid and scan line, this underlay substrate makes formation first insulating protective layer, and this first insulating protective layer covers this first metal layer, this first insulating protective layer makes and forms semiconductor layer, this semiconductor layer is positioned at above this grid, this first insulating protective layer makes formation second metal level, this second metal level comprises source electrode, drain electrode and data wire, this source electrode is separate with this drain electrode and contact with this semiconductor layer respectively, a part for this semiconductor layer is exposed between this source electrode and this drain electrode, this data wire is connected with this source electrode, intersects to form multiple pixel cell by many these scan lines and many these data wires, this first insulating protective layer makes formation second insulating protective layer, and this second insulating protective layer covers this source electrode, this drain electrode, this data wire and from this semiconductor layer of the part exposed between this source electrode and this drain electrode, this second insulating protective layer makes formation first conductive layer, and this first conductive layer comprises the conductive connection part across this data wire, this first conductive layer makes formation the 3rd insulating protective layer, 3rd insulating protective layer is in the position of conductive connection part forming the first through hole with this conductive connection part of exposed portion, and the 3rd insulating protective layer and this second insulating barrier are in the position that should drain being formed to the second through hole with this drain electrode of exposed portion, and formation second conductive layer is made on the 3rd insulating protective layer, this second conductive layer comprises Part I and the Part II of separate setting, this Part I correspondence is positioned at above this data wire and this data wire of postponing is arranged, this Part I is also inserted in this first through hole to contact with this conductive connection part and is realized being electrically connected, the first electrode is jointly formed by the Part I of this first conductive layer and this second conductive layer, this first electrode is public electrode, this Part II is arranged in corresponding pixel cell and also inserts this second through hole and realizes being electrically connected with this drain contact, this Part II forms the second electrode, this second electrode is pixel electrode.
In present pre-ferred embodiments; when this second insulating protective layer makes this first conductive layer of formation; be included in this first conductive layer in the position of data wire formation first breach should be made to expose this second insulating protective layer of below, the 3rd insulating protective layer be formed on this first conductive layer also inserted in this first breach and contacts with this second insulating protective layer.
In present pre-ferred embodiments; when this second insulating protective layer makes this first conductive layer of formation; be included in this first conductive layer and make formation second breach to expose this second insulating protective layer of below in the position at corresponding thin-film transistor place, the 3rd insulating protective layer be formed on this first conductive layer is also inserted in this second breach and contacts with this second insulating protective layer.
In present pre-ferred embodiments, the Part I of this second conductive layer is the list structure corresponding with this data wire and covers this data wire.
In present pre-ferred embodiments, this Part I and this Part II be make this second conductive layer with optical cover process in make formed.
The invention has the beneficial effects as follows, second conductive layer of thin-film transistor array base-plate of the present invention comprises Part I and Part II, Part I is inserted in the first through hole to contact with the conductive connection part of the first conductive layer and is realized being electrically connected, the first electrode is jointly formed by the Part I of the first conductive layer and the second conductive layer, namely the first electrode is formed jointly by the Part I of the first conductive layer and the second conductive layer that are positioned at different layers, Part II is arranged in corresponding pixel cell and also inserts the second through hole and realizes being electrically connected with drain contact, Part II forms the second electrode.Except the electric field formed by the Part II of the first conductive layer and the second conductive layer that are positioned at different layers, the Part II of the Part I and the second conductive layer that are positioned at the second conductive layer of same layer also forms electric field, enhance the electric field strength between the first electrode and the second electrode, light is made to pass the penetration capacity grow of viewing area, effectively improve the penetrance of thin-film transistor array base-plate, and then the liquid crystal indicator making to have this thin-film transistor array base-plate has higher penetrance.
Further; in the position of respective data lines; second insulating protective layer is contacted by the first breach with the 3rd insulating protective layer; and the second insulating protective layer and the 3rd insulating protective layer are between data wire and the Part I of the second conductive layer; thus the distance between the Part I increasing data wire and the second conductive layer, the electric capacity between the second conductive layer and data wire is reduced.That is, the total capacitance on the electrode of thin-film transistor array base-plate reduces.Timeconstantτ based on signal delay is proportional to the product of total capacitance on electrode and all-in resistance, when the all-in resistance of thin-film transistor array base-plate remains unchanged substantially, when total capacitance reduces, the signal delay of thin-film transistor array base-plate reduces accordingly, thus the signal delay effectively reduced on data wire, improve display quality.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent with other objects, feature and advantage to allow above-mentioned liquid crystal indicator of the present invention and preparation method thereof, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail.
Accompanying drawing explanation
Fig. 1 is the planar structure schematic diagram of the thin-film transistor array base-plate of existing a kind of liquid crystal indicator.
Fig. 2 is the cross-sectional view along II-II line of the thin-film transistor array base-plate shown in Fig. 1.
Fig. 3 is the planar structure schematic diagram of the thin-film transistor array base-plate of present pre-ferred embodiments.
Fig. 4 is the Making programme figure of the thin-film transistor array base-plate shown in Fig. 3.
Fig. 5 is the cross-sectional view of the thin-film transistor array base-plate shown in Fig. 3 along V-V line.
Fig. 6 is the cross-sectional view of the thin-film transistor array base-plate shown in Fig. 3 along VI-VI line.
Fig. 7 is the cross-sectional view of the thin-film transistor array base-plate shown in Fig. 3 along VII-VII line.
Fig. 8 a to Fig. 8 f is the planar structure schematic diagram of the Making programme of the thin-film transistor array base-plate shown in Fig. 3.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to thin-film transistor array base-plate proposed according to the present invention and preparation method thereof, and there is the embodiment of liquid crystal indicator of this thin-film transistor array base-plate, structure, feature and effect thereof, be described in detail as follows:
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the present invention for the technological means reaching predetermined object and take and effect be able to more deeply and concrete understanding, however institute's accompanying drawings be only to provide with reference to and the use of explanation, be not used for being limited the present invention.
Fig. 3 is the planar structure schematic diagram of the thin-film transistor array base-plate of present pre-ferred embodiments, Fig. 4 is the Making programme figure of the thin-film transistor array base-plate shown in Fig. 3, Fig. 5 is the cross-sectional view of the thin-film transistor array base-plate shown in Fig. 3 along V-V line, Fig. 6 is the cross-sectional view of the thin-film transistor array base-plate shown in Fig. 3 along VI-VI line, and Fig. 7 is the cross-sectional view of the thin-film transistor array base-plate shown in Fig. 3 along VII-VII line.Fig. 8 a to Fig. 8 f is the planar structure schematic diagram of the Making programme of the thin-film transistor array base-plate shown in Fig. 3.It should be noted that, thin-film transistor array base-plate comprises multi-strip scanning line and a plurality of data lines, and multi-strip scanning line and a plurality of data lines are mutually intersected and are limited multiple pixel region, scan line and data wire crossover location place are provided with thin-film transistor, this is well known to those skilled in the art technology, does not repeat them here.In order to illustrative simplicity, Fig. 3 to Fig. 7, Fig. 8 a to Fig. 8 f only illustrate the partial structurtes schematic diagram of a pixel region of corresponding thin-film transistor array base-plate.And in order to the more convenient position relationship embodied in pixel region intuitively between each element of being formed by light-proof material; Fig. 8 a to Fig. 8 f does not show underlay substrate 10, first insulating protective layer 12, second insulating protective layer 15 and the 3rd insulating protective layer 17 that are formed by transparent material, about the position relationship of underlay substrate 10, first insulating protective layer 12, second insulating protective layer 15 and the 3rd insulating protective layer 17 can with reference to figure 3 to Fig. 7.Below the manufacture method of the thin-film transistor array base-plate to the present embodiment is described in further detail.
Step S11: please refer to Fig. 4, Fig. 5 and Fig. 8 a, utilizes first optical cover process to form the first metal layer 11 on underlay substrate 10.This underlay substrate 10 is such as transparent glass substrate substrate, and this first metal layer 11 comprises grid 111 and scan line (not shown).
Step S12: form the first insulating protective layer 12 on this underlay substrate 10, this first insulating protective layer 12 covers this first metal layer 11.This first insulating protective layer 12 is such as gate insulator.Then, please refer to Fig. 4, Fig. 5 and Fig. 8 b, utilize second optical cover process to form semiconductor layer 13 on this first insulating protective layer 12, this semiconductor layer 13 is positioned at above the grid 111 of this first metal layer 11.In the present embodiment, this semiconductor layer 13 comprises amorphous silicon (a-Si) semiconductor layer 131 and two n being positioned at this amorphous silicon (a-Si) semiconductor layer 131
+thin amorphous silicon layer 133.This n
+thin amorphous silicon layer 133 is positioned at the two ends of this amorphous silicon (a-Si) semiconductor layer 131, thus exposes this amorphous silicon (a-Si) semiconductor layer 131 of mid portion.In other embodiments, also this n can be saved
+thin amorphous silicon layer 133, or one deck etch stop layer (etchingstopper) is made again on this semiconductor layer 13, this is well known, is not repeated herein.
Step S13: please refer to Fig. 4, Fig. 5 and Fig. 8 c, after this semiconductor layer 13 is formed, utilizes the 3rd road optical cover process to form the second metal level 14 on this first insulating protective layer 12.This second metal level 14 comprises source electrode 142, drain electrode 144 and data wire 146.This source electrode 142 and this drain electrode 144 separate and respectively with the n of this semiconductor layer 13
+thin amorphous silicon layer 133 directly contacts and covers this n
+thin amorphous silicon layer 133.That is, this amorphous silicon (a-Si) semiconductor layer 131 of mid portion comes out between this source electrode 142 and this drain electrode 154.In other words, a part for this semiconductor layer 13 comes out between this source electrode 142 and this drain electrode 154.In the present embodiment, this source electrode 142 is connected with this data wire 146, but not as limit.Multiple pixel cell P is intersected to form by many these scan lines and many these data wires 146.
Step S14: after this second metal level 14 is formed, this first insulating protective layer 12 forms the second insulating protective layer 15.This second insulating protective layer 15 covers this source electrode 142, this drain electrode 144, this data wire 146 and from this semiconductor layer 13 of the part come out between this source electrode 142 and this drain electrode 144.This second insulating protective layer 15 is such as by silicon nitride (SiN
x) passivation layer (PV, Passivation) that formed or the protective layer (OC, Overcoat) formed by organic resin.Then, please refer to Fig. 4, Fig. 5 and Fig. 8 d, utilize the 4th road optical cover process to form the first conductive layer 16 on this second insulating protective layer 15.This first conductive layer 16 comprises the conductive connection part 162 across this data wire 146.First conductive layer 16 is such as be made up of transparent conductive materials such as tin indium oxides (ITO, IndiumTinOxide), but not as limit.When this second insulating protective layer 15 makes this first conductive layer 16 of formation, this first conductive layer 16 is also formed the first breach 164 and the second breach 166.This first breach 164 correspondence is positioned at the top of this data wire 146 and this first breach 164 is separated into upper and lower two parts by conductive connection part 162, to expose this second insulating protective layer 15 of below.This second breach 166 correspondence is positioned at the position at thin-film transistor place, to expose this second insulating protective layer 15 of below.
Step S15: after this first conductive layer 16 is formed, this first conductive layer 16 makes formation the 3rd insulating protective layer 17.The 3rd insulating protective layer 17 be formed on this first conductive layer 16 also inserts this first breach 164 with this second breach 166, and the 3rd insulating protective layer 17 is contacted with this second insulating protective layer 15.3rd insulating protective layer 17 is such as the passivation layer (PV, Passivation) formed by silicon nitride (SiNx).
Then, please refer to Fig. 4, Fig. 5 and Fig. 8 e, utilize the 5th road optical cover process at the 3rd insulating protective layer 17 in the position of conductive connection part 162 forming the first through hole 172 with this conductive connection part 162 of exposed portion, namely the first through hole 172 is through the 3rd insulating protective layer 17, this conductive connection part 162 of below is partly come out, the 3rd insulating protective layer 17 and this second insulating barrier 15 in should drain 144 position form the second through hole 174 with this drain electrode 144 of exposed portion, namely the second through hole 174 is simultaneously through the 3rd insulating protective layer 17 and this second insulating barrier 15, this drain electrode 144 of below is partly come out.This first through hole 172 and this second through hole 174 all complete in the 5th road optical cover process.Also can utilize simultaneously and form third through-hole (figure does not illustrate) for making periphery line with optical cover process (i.e. the 5th road optical cover process) in periphery, the viewing area of thin-film transistor array base-plate 100, this is well known to those skilled in the art, and does not repeat them here.
Step S16: please refer to Fig. 4, Fig. 5 and Fig. 8 f, utilizes the 6th road optical cover process to form the second conductive layer 18 on the 3rd insulating protective layer 17.This second conductive layer 18 is such as be made up of transparent conductive materials such as tin indium oxides (ITO, IndiumTinOxide), but not as limit.This second conductive layer 18 comprises Part I 182 and the Part II 184 of separate setting, this Part I 182 correspondence is positioned at above this data wire 146 and this data wire 146 of postponing is arranged, this Part I 182 is specially the list structure corresponding with this data wire 146 and covers this data wire 146, this Part I 182 is also inserted in this first through hole 172 to contact with this conductive connection part 162 and is realized being electrically connected, jointly form the first electrode by the Part I 182 of this first conductive layer 16 and this second conductive layer 18, the first electrode is such as public electrode.This Part II 184 is arranged in corresponding pixel cell P and also inserts this second through hole 174 and contacts with this drain electrode 144 and realize being electrically connected, this Part II 184 forms the second electrode, second electrode such as pixel electrode, this Part II 184 such as comprises main part (figure does not mark) and the multiple stripes (scheming not mark) that is connected with this main part further, this main part correspondence is positioned to conduct electricity above this drain electrode 144 and with this drain electrode 144 and is connected, and the plurality of stripes stretches in pixel cell P.Understandable, this Part I 182 of this second conductive layer 18 and this Part II 184 all make and are formed in the 6th road optical cover process.
Please refer to Fig. 3, Fig. 5 to Fig. 7, this Part I 182 of the present invention is inserted in this first through hole 172 to contact with this conductive connection part 162 and is realized being electrically connected, jointly form the first electrode by the Part I 182 of this first conductive layer 16 and this second conductive layer 18, namely the first electrode is formed (ginseng Fig. 6) jointly by the Part I 182 of this first conductive layer 16 and this second conductive layer 18 that are positioned at different layers.This Part II 184 is arranged in corresponding pixel cell P and also inserts this second through hole 174 and contacts with this drain electrode 144 and realize being electrically connected, and this Part II 184 forms the second electrode (ginseng Fig. 5).Except the electric field formed by the Part II 184 of this first conductive layer 16 and this second conductive layer 18 of being positioned at different layers, the Part I 182 being positioned at this second conductive layer 18 of same layer also forms electric field with the Part II 184 of this second conductive layer 18, enhance the electric field strength between the first electrode and the second electrode, light is made to pass the penetration capacity grow of viewing area, effectively improve the penetrance of thin-film transistor array base-plate, and then the liquid crystal indicator making to have this thin-film transistor array base-plate has higher penetrance.
Further; in to should the position of data wire 146; this second insulating protective layer 15 is contacted by this first breach 164 with the 3rd insulating protective layer 17; and this second insulating protective layer 15 and the 3rd insulating protective layer 17 are between this data wire 146 and Part I 182 of this second conductive layer 18 (ginseng Fig. 7); thus the distance between the Part I 182 increasing data wire 146 and this second conductive layer 18, the electric capacity between this second conductive layer 18 and this data wire 146 is reduced.That is, the total capacitance on the electrode of thin-film transistor array base-plate 100 reduces.Timeconstantτ based on signal delay is proportional to the product of total capacitance on electrode and all-in resistance, when the all-in resistance of thin-film transistor array base-plate 100 remains unchanged substantially, when total capacitance reduces, the signal delay of thin-film transistor array base-plate 100 reduces accordingly, thus the signal delay effectively reduced on data wire, improve display quality.
As shown in Fig. 3, Fig. 5 to Fig. 7, the thin-film transistor array base-plate 100 utilizing above six road optical cover process to make comprises underlay substrate 10, the first metal layer 11, first insulating protective layer 12 be formed on underlay substrate 10, semiconductor layer 13, second metal level 14, second insulating protective layer 15, first conductive layer 16, the 3rd insulating protective layer 17 and the second conductive layer 18.
This underlay substrate 10 is such as transparent glass substrate substrate.This first metal layer 11 comprises grid 111 and scan line (not shown).This first insulating protective layer 12 to be formed on this underlay substrate 10 and to cover the grid 111 of this first metal layer 11.First insulating protective layer 12 is such as gate insulator.This semiconductor layer 13 to be formed on this first insulating protective layer 12 and to be positioned at above the grid 111 of this first metal layer 11.In the present embodiment, this semiconductor layer 13 comprises amorphous silicon (a-Si) semiconductor layer 131 and two n
+thin amorphous silicon layer 133.This n
+thin amorphous silicon layer 133 is positioned at the two ends of this amorphous silicon (a-Si) semiconductor layer 131, thus exposes this amorphous silicon (a-Si) semiconductor layer 131 of mid portion.This second metal level 14 is formed on this first insulating protective layer 12.This second metal level 14 comprises source electrode 142, drain electrode 144 and data wire 146.Source electrode 142 and drain electrode 144 separate and respectively with the n of semiconductor layer 13
+thin amorphous silicon layer 133 directly contacts and covers n
+thin amorphous silicon layer 133.That is, amorphous silicon (a-Si) semiconductor layer 131 of mid portion comes out between source electrode 142 and drain electrode 154.In other words, a part for semiconductor layer 13 comes out between source electrode 142 and drain electrode 154.In the present embodiment, source electrode 142 is connected with data wire 146, but not as limit.Multiple pixel cell P is intersected to form by many these scan lines and many these data wires 146.This second insulating protective layer 15 is formed on this first insulating protective layer 12.This second insulating protective layer 15 covers this source electrode 142, this drain electrode 144, this data wire 146 and from this semiconductor layer 13 of the part come out between this source electrode 142 and this drain electrode 144.This second insulating protective layer 15 is such as by silicon nitride (SiN
x) passivation layer (PV, Passivation) that formed or the protective layer (OC, Overcoat) formed by organic resin.This first conductive layer 16 is formed on this second insulating protective layer 15.This first conductive layer 16 comprises the conductive connection part 162 across this data wire 146.First conductive layer 16 is such as be made up of transparent conductive materials such as tin indium oxides (ITO, IndiumTinOxide), but not as limit.This first conductive layer 16 is also formed the first breach 164 and the second breach 166.This first breach 164 correspondence is positioned at the top of this data wire 146 and this first breach 164 is separated into upper and lower two parts by conductive connection part 162, to expose this second insulating protective layer 15 of below.This second breach 166 correspondence is positioned at the position at thin-film transistor place, to expose this second insulating protective layer 15 of below.3rd insulating protective layer 17 is formed on this first conductive layer 16.3rd insulating protective layer 17 also inserts this first breach 164 with this second breach 166, and the 3rd insulating protective layer 17 is contacted with this second insulating protective layer 15.3rd insulating protective layer 17 is such as the passivation layer (PV, Passivation) formed by silicon nitride (SiNx).3rd insulating protective layer 17 is in the position of conductive connection part 162 being formed with the first through hole 172 with this conductive connection part 162 of exposed portion; namely the first through hole 172 is through the 3rd insulating protective layer 17, is partly come out by this conductive connection part 162 of below.3rd insulating protective layer 17 and this second insulating barrier 15 in should drain 144 position be formed with the second through hole 174 with this drain electrode 144 of exposed portion; namely the second through hole 174 is simultaneously through the 3rd insulating protective layer 17 and this second insulating barrier 15, this drain electrode 144 of below is partly come out.This second conductive layer 18 is formed on the 3rd insulating protective layer 17.This second conductive layer 18 is such as be made up of transparent conductive materials such as tin indium oxides (ITO, IndiumTinOxide), but not as limit.This second conductive layer 18 comprises Part I 182 and the Part II 184 of separate setting, this Part I 182 correspondence is positioned at above this data wire 146 and this data wire 146 of postponing is arranged, this Part I 182 is specially the list structure corresponding with this data wire 146 and covers this data wire 146, this Part I 182 is also inserted in this first through hole 172 to contact with this conductive connection part 162 and is realized being electrically connected, jointly form the first electrode by the Part I 182 of this first conductive layer 16 and this second conductive layer 18, the first electrode is such as public electrode.This Part II 184 is arranged in corresponding pixel cell P and also inserts this second through hole 174 and contacts with this drain electrode 144 and realize being electrically connected, this Part II 184 forms the second electrode, second electrode such as pixel electrode, this Part II 184 such as comprises main part 1841 and multiple stripes 1842 that is connected with this main part 1841 further, this main part 1841 correspondence is positioned to conduct electricity above this drain electrode 144 and with this drain electrode 144 and is connected, and the plurality of stripes 1842 stretches in pixel cell P.
This Part I 182 of the present invention is inserted in this first through hole 172 to contact with this conductive connection part 162 and is realized being electrically connected, jointly form the first electrode by the Part I 182 of this first conductive layer 16 and this second conductive layer 18, namely the first electrode is formed (ginseng Fig. 6) jointly by the Part I 182 of this first conductive layer 16 and this second conductive layer 18 that are positioned at different layers.This Part II 184 is arranged in corresponding pixel cell P and also inserts this second through hole 174 and contacts with this drain electrode 144 and realize being electrically connected, and this Part II 184 forms the second electrode (ginseng Fig. 5).Except the electric field formed by the Part II 184 of this first conductive layer 16 and this second conductive layer 18 of being positioned at different layers, the Part I 182 being positioned at this second conductive layer 18 of same layer also forms electric field with the Part II 184 of this second conductive layer 18, enhance the electric field strength between the first electrode and the second electrode, light is made to pass the penetration capacity grow of viewing area, effectively improve the penetrance of thin-film transistor array base-plate, and then the liquid crystal indicator making to have this thin-film transistor array base-plate has higher penetrance.
Further; in to should the position of data wire 146; this second insulating protective layer 15 is contacted by this first breach 164 with the 3rd insulating protective layer 17; and this second insulating protective layer 15 and the 3rd insulating protective layer 17 are between this data wire 146 and Part I 182 of this second conductive layer 18 (ginseng Fig. 7); thus the distance between the Part I 182 increasing data wire 146 and this second conductive layer 18, the electric capacity between this second conductive layer 18 and this data wire 146 is reduced.That is, the total capacitance on the electrode of thin-film transistor array base-plate 100 reduces.Timeconstantτ based on signal delay is proportional to the product of total capacitance on electrode and all-in resistance, when the all-in resistance of thin-film transistor array base-plate 100 remains unchanged substantially, when total capacitance reduces, the signal delay of thin-film transistor array base-plate 100 reduces accordingly, thus the signal delay effectively reduced on data wire, improve display quality.
At same pixel area size (as 56.4 μm × 169.2 μm), under the condition of identical box thick (as 3.2 μm) and identical liquid crystal (as MJ131496), with the liquid crystal indicator with existing thin-film transistor array base-plate 1, signal delay test is carried out to the liquid crystal indicator of the thin-film transistor array base-plate 100 with present pre-ferred embodiments, the liquid crystal indicator that result display has the thin-film transistor array base-plate 100 of present pre-ferred embodiments postpones to have dropped 12.02% with the liquid crystal indicator ratioing signal with existing thin-film transistor array base-plate 1.
Above to thin-film transistor array base-plate provided by the present invention and preparation method thereof, and the liquid crystal indicator with this thin-film transistor array base-plate is described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a thin-film transistor array base-plate, is characterized in that, comprising:
Underlay substrate (10);
The first metal layer (11), be formed on this underlay substrate (10), this first metal layer (11) comprises grid (111) and scan line;
First insulating protective layer (12), is formed in this underlay substrate (10) and goes up and cover this first metal layer (11);
Semiconductor layer (13), is formed in this first insulating protective layer (12) and goes up and be positioned at this grid (111) top;
Second metal level (14), be formed on this first insulating protective layer (12), this second metal level (14) comprises source electrode (142), drain electrode (144) and data wire (146), this source electrode (142) is separate with this drain electrode (144) and contact with this semiconductor layer (13) respectively, the part of this semiconductor layer (13) is exposed between this source electrode (142) and this drain electrode (144), this data wire (146) is connected with this source electrode (142), multiple pixel cell (P) is intersected to form by many these scan lines and many these data wires (146),
Second insulating protective layer (15), is formed in this first insulating protective layer (12) and goes up and cover this source electrode (142), this drain electrode (144), this data wire (146) and from this semiconductor layer of part (13) exposed between this source electrode (142) and this drain electrode (144);
First conductive layer (16), be formed on this second insulating protective layer (15), this first conductive layer (16) comprises the conductive connection part (162) across this data wire (146);
3rd insulating protective layer (17), be formed on this first conductive layer (16), 3rd insulating protective layer (17) is in the position of conductive connection part (162) having the first through hole (172) with this conductive connection part (162) of exposed portion, and the 3rd insulating protective layer (17) and this second insulating barrier (15) are in the position of should drain (144) being had to the second through hole (174) with this drain electrode (144) of exposed portion, and second conductive layer (18), be formed on the 3rd insulating protective layer (17), this second conductive layer (18) comprises Part I (182) and the Part II (184) of separate setting, this Part I (182) correspondence is positioned at this data wire (146) top and this data wire (146) of postponing is arranged, this Part I (182) is also inserted in this first through hole (172) to contact with this conductive connection part (162) and is realized being electrically connected, jointly the first electrode is formed by this Part I (182) of this first conductive layer (16) and this second conductive layer (18), this first electrode is public electrode, this Part II (184) is arranged in corresponding pixel cell (P) and also inserts this second through hole (174) and contacts with this drain electrode (144) and realize being electrically connected, this Part II (184) forms the second electrode, this second electrode is pixel electrode.
2. thin-film transistor array base-plate as claimed in claim 1; it is characterized in that; this first conductive layer (16) is in the position of data wire (146) forming the first breach (164) to expose this second insulating protective layer (15) of below, and the 3rd insulating protective layer (17) be formed on this first conductive layer (16) is also inserted in this first breach (164) and contacted with this second insulating protective layer (15).
3. thin-film transistor array base-plate as claimed in claim 1; it is characterized in that; this first conductive layer (16) forms the second breach (166) to expose this second insulating protective layer (15) of below in the position at corresponding thin-film transistor place, the 3rd insulating protective layer (17) be formed on this first conductive layer (16) is also inserted in this second breach (166) and contacted with this second insulating protective layer (15).
4. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, the Part I (182) of this second conductive layer (18) is the list structure corresponding with this data wire (146) and covers this data wire (146).
5. a liquid crystal indicator, is characterized in that, comprises the thin-film transistor array base-plate according to any one of Claims 1-4.
6. a manufacture method for thin-film transistor array base-plate, is characterized in that, comprising:
Form the first metal layer (11) upper making of underlay substrate (10), this first metal layer (11) comprises grid (111) and scan line;
At this underlay substrate (10) upper making formation first insulating protective layer (12), this first insulating protective layer (12) covers this first metal layer (11);
Form semiconductor layer (13) upper making of this first insulating protective layer (12), this semiconductor layer (13) is positioned at this grid (111) top;
At this first insulating protective layer (12) upper making formation second metal level (14), this second metal level (14) comprises source electrode (142), drain electrode (144) and data wire (146), this source electrode (142) is separate with this drain electrode (144) and contact with this semiconductor layer (13) respectively, the part of this semiconductor layer (13) is exposed between this source electrode (142) and this drain electrode (144), this data wire (146) is connected with this source electrode (142), multiple pixel cell (P) is intersected to form by many these scan lines and many these data wires (146),
Make formation second insulating protective layer (15) this first insulating protective layer (12) is upper, this second insulating protective layer (15) covers this source electrode (142), this drain electrode (144), this data wire (146) and from this semiconductor layer of part (13) exposed between this source electrode (142) and this drain electrode (144);
At this second insulating protective layer (15) upper making formation first conductive layer (16), this first conductive layer (16) comprises the conductive connection part (162) across this data wire (146);
At this first conductive layer (16) upper making formation the 3rd insulating protective layer (17), 3rd insulating protective layer (17) is in the position of conductive connection part (162) forming the first through hole (172) with this conductive connection part (162) of exposed portion, and the 3rd insulating protective layer (17) and this second insulating barrier (15) are in the position of should drain (144) being formed to the second through hole (174) with this drain electrode (144) of exposed portion; And
At the 3rd insulating protective layer (17) upper making formation second conductive layer (18), this second conductive layer (18) comprises Part I (182) and the Part II (184) of separate setting, this Part I (182) correspondence is positioned at this data wire (146) top and this data wire (146) of postponing is arranged, this Part I (182) is also inserted in this first through hole (172) to contact with this conductive connection part (162) and is realized being electrically connected, jointly the first electrode is formed by the Part I (182) of this first conductive layer (16) and this second conductive layer (18), this first electrode is public electrode, this Part II (184) is arranged in corresponding pixel cell (P) and also inserts this second through hole (174) and contacts with this drain electrode (144) and realize being electrically connected, this Part II (184) forms the second electrode, this second electrode is pixel electrode.
7. the manufacture method of thin-film transistor array base-plate as claimed in claim 6, it is characterized in that, when the upper making of this second insulating protective layer (15) forms these the first conductive layer (16), be included in this first conductive layer (16) in should data wire (146) position make formation first breach (164) with expose below this second insulating protective layer (15), the 3rd insulating protective layer (17) be formed on this first conductive layer (16) is also inserted in this first breach (164) contact with this second insulating protective layer (15).
8. the manufacture method of thin-film transistor array base-plate as claimed in claim 7, it is characterized in that, when the upper making of this second insulating protective layer (15) forms these the first conductive layer (16), be included in this first conductive layer (16) and make formation second breach (166) to expose this second insulating protective layer (15) of below in the position at corresponding thin-film transistor place, the 3rd insulating protective layer (17) be formed on this first conductive layer (16) is also inserted in this second breach (166) contact with this second insulating protective layer (15).
9. the manufacture method of thin-film transistor array base-plate as claimed in claim 6, it is characterized in that, the Part I (182) of this second conductive layer (18) is the list structure corresponding with this data wire (146) and covers this data wire (146).
10. the manufacture method of thin-film transistor array base-plate as claimed in claim 6, it is characterized in that, this Part I (182) and this Part II (184) be make this second conductive layer (18) with optical cover process in make formed.
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| CN201510514177.8A CN105097844A (en) | 2015-08-20 | 2015-08-20 | Thin film transistor array substrate, manufacture method thereof and liquid crystal display device |
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| CN201788341U (en) * | 2010-08-31 | 2011-04-06 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and liquid crystal display |
| US20120112213A1 (en) * | 2010-11-09 | 2012-05-10 | Samsung Electronics Co., Ltd. | Display substrate, method for manufacturing the same, and display apparatus having the same |
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| CN101625493A (en) * | 2008-07-08 | 2010-01-13 | 三星电子株式会社 | Array substrate and liquid crystal display apparatus having the same |
| CN201788341U (en) * | 2010-08-31 | 2011-04-06 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and liquid crystal display |
| US20120112213A1 (en) * | 2010-11-09 | 2012-05-10 | Samsung Electronics Co., Ltd. | Display substrate, method for manufacturing the same, and display apparatus having the same |
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Application publication date: 20151125 |