CN105095116A

CN105095116A - Cache replacing method, cache controller and processor

Info

Publication number: CN105095116A
Application number: CN201410211355.5A
Authority: CN
Inventors: 张立新; 魏巍; 熊劲; 蒋德钧
Original assignee: Huawei Technologies Co Ltd; Institute of Computing Technology of CAS
Current assignee: Huawei Technologies Co Ltd; Institute of Computing Technology of CAS
Priority date: 2014-05-19
Filing date: 2014-05-19
Publication date: 2015-11-25
Anticipated expiration: 2034-05-19
Also published as: CN105095116B

Abstract

The embodiment of the invention provides a cache replacing method, a cache controller and a processor. The method comprises the following steps that: the cache controller determines an associated cache pool of a cache line to be replaced, wherein each associated cache row in the associated cache pool and the cache row to be replaced belong to the same memory row; a cache row to be written back is further determined from the associated cache pool according to the access information of the associated cache row; and data in the cache row to be replaced and the cache row to be written back are simultaneously written into a memory. The cache row to be replaced and the cache row to be written back belong to the same memory row, so that the hit rate of the cache region can be improved; and the memory access performance is improved. The cache controller further determines the cache row to be written back from the associated cache pool according to the access information of the associated cache row, and only the cache row to be written back in the associated cache pool is written into the memory, so that the number of the memory writing times can be reduced; and the service life of the memory is prolonged.

Description

Method, cache controller and processor that buffer memory is replaced

Technical field

The embodiment of the present invention relates to the communication technology, particularly relates to method, cache controller and processor that a kind of buffer memory is replaced.

Background technology

Along with the development of large market demand, had more and more higher requirement to the capacity of internal memory and access speed, conventional dynamic RAM (DynamicRandom-AccessMemory is called for short DRAM) can not meet the demands.The novel nonvolatile memory (Non-VolatileMemory is called for short NVM) be thereupon born is expected to replace DRAM with its advantage such as Large Copacity, low-power consumption becomes memory system in computer system.But it is high that the read-write of existing NVM postpones comparatively DRAM, and it is limited to write number of times.

The read-write mechanism of NVM inside is similar with DRAM, the data that NVM has a row buffer (Rowbuffer) to be used for preserving in the memory line of the last access, and whether the delay-dependent of NVM access hits in row buffer.If the address of continuous print two memory access request belongs to same memory line, then row buffer hit, when row buffer is hit, after memory access request once do not need to read data from memory array, but directly from row buffer, read data, decrease the delay of internal storage access.Because the read-write of NVM postpones higher, if row buffer is not hit, then need to read data from nvm array, access delay to DRAM array is greater than to the access delay of nvm array, but the two read-write to row buffer postpones substantially identical, therefore, more internal storage access efficiency can be significantly improved for the hit rate improving row buffer NVM.In current mechanism, by the impact of buffer memory (cache) replacement policy, cause the request address mailing to internal memory comparatively random, therefore, row buffer hit rate is poor, affects internal storage access performance.

Summary of the invention

Method, cache controller and processor that the embodiment of the present invention provides a kind of buffer memory to replace, can improve the hit rate in row cache district, thus improve internal storage access performance, and can reduce internal memory write number of times, improve the serviceable life of internal memory.

A kind of method that first aspect present invention provides buffer memory to replace, comprising:

Cache controller receives memory access request, according to the address search buffer memory of described memory access request, if do not find the address of described memory access request in described buffer memory, then from described buffer memory, determines cache lines to be replaced;

If the dirty cache lines of described buffer memory behavior to be replaced, then described cache controller is determined to associate cache pool according to the address of described cache lines to be replaced, described association cache pool comprises at least one association cache lines, described association cache lines and described cache lines to be replaced belong to same memory line, described association cache lines is arranged in described buffer memory, the dirty cache lines of described association buffer memory behavior, the data of described dirty cache lines were modified;

Described cache controller determines cache lines to be write back according to the visit information of described association cache lines from described association cache pool;

Described cache controller by described cache lines to be replaced and described in the address of cache lines to be write back and data send to Memory Controller Hub, with make described Memory Controller Hub according to described cache lines to be replaced and described in cache lines to be write back address by described cache lines to be replaced and described in the data write memory of cache lines to be write back, and the data needed for described memory access request are read in from described internal memory the position of described cache lines to be replaced.

In conjunction with first aspect present invention, in the first possible implementation of first aspect present invention, described cache controller determines cache lines to be write back according to the visit information of described association cache lines from described association cache pool, comprising:

Described cache controller according to the access times of described association cache lines and/or write back indicate from described association cache pool, determine cache lines to be write back, described in write back indicate for representing that described association cache lines is the need of writing back internal memory.

In conjunction with the first possible implementation of first aspect present invention, in the implementation that the second of first aspect present invention is possible, described cache controller determines cache lines to be write back according to the access times of described association cache lines from described association cache pool, comprising:

Described cache controller determines whether described association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, described nearest least referenced buffer memory chained list is used for sorting according to the access times of each cache lines in Preset Time, the cache lines that in Preset Time described in last M buffer memory behavior of described nearest least referenced buffer memory chained list, access times are minimum, M is positive integer;

If described association cache lines belongs to last M cache lines of described nearest least referenced buffer memory chained list, then described cache controller determines cache lines to be write back described in the behavior of described association buffer memory.

In conjunction with the first possible implementation of first aspect present invention, in the third possible implementation of first aspect present invention, described cache controller determines cache lines to be write back according to the sign that writes back of described association cache lines from described association cache pool, comprising:

If the sign that writes back of described association cache lines represents that described association cache lines needs to write back internal memory, then described cache controller determines described association buffer memory behavior to be written time cache lines.

In conjunction with the first possible implementation of first aspect present invention, in the 4th kind of possible implementation of first aspect present invention, described cache controller determines to be write back cache lines with writing back to indicate from described association cache pool according to the access times of described association cache lines, comprising:

According to the access times of described association cache lines, described cache controller judges whether described association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, described nearest least referenced buffer memory chained list is used for sorting according to the access times of each cache lines in Preset Time, the cache lines that in Preset Time described in last M buffer memory behavior of described nearest least referenced buffer memory chained list, access times are minimum, M is positive integer;

If described association cache lines belongs to last M cache lines of described nearest least referenced buffer memory chained list, and the sign that writes back of described association cache lines represents that described association cache lines needs to write back internal memory, then described cache controller determines described association buffer memory behavior to be written time cache lines.

In conjunction with the first of first aspect present invention to the 4th kind of possible implementation, in the 5th kind of possible implementation of first aspect present invention, described cache controller by described after writing back data corresponding to cache lines and writing back described internal memory, described method also comprises:

The value writing back sign of cache lines described to be write back is set to expression by described cache controller not to be needed to write back internal memory.

In conjunction with the first of first aspect present invention to the 5th kind of possible implementation, in the 6th kind of possible implementation of first aspect present invention, described method also comprises:

The value writing back sign of each cache lines is periodically set to expression by described cache controller to be needed to write back internal memory.

In conjunction with the first of first aspect present invention to the 5th kind of possible implementation, in the 7th kind of possible implementation of first aspect present invention, describedly write back the value being denoted as counter, if the value of described counter is not less than write back threshold value, then writes back described in and indicate for representing that described association cache lines needs write memory;

If write back threshold value described in the value of described counter is less than, then write back described in and indicate for representing that described association cache lines does not need write memory.

In conjunction with the 7th kind of possible implementation of first aspect present invention, in the 8th kind of possible implementation of first aspect present invention, when described write back the value being denoted as counter time, the value writing back sign of cache lines described to be write back is set to expression by described cache controller not to be needed to write back internal memory, comprising:

The value of described counter is set to zero by described cache controller.

In conjunction with the 7th kind of possible implementation of first aspect present invention, in the 9th kind of possible implementation of first aspect present invention, if the value of described counter be less than described in write back threshold value, described method also comprises:

The value of described counter is added one by described cache controller.

In conjunction with the first of first aspect present invention to the 9th kind of possible implementation, in the tenth kind of possible implementation of first aspect present invention, described cache controller is determined to associate cache pool according to the address of described cache lines to be replaced, comprising:

Described cache controller determines cache lines for subsequent use according to the address of described cache lines to be replaced, and described cache lines for subsequent use and described cache lines to be replaced belong to same memory line;

Described cache controller judges whether described cache lines for subsequent use is arranged in described buffer memory;

If described cache lines for subsequent use is arranged in described buffer memory, then described cache controller judges whether described cache lines for subsequent use is dirty cache lines;

If the dirty cache lines of described buffer memory behavior for subsequent use, then described cache controller determines described buffer memory behavior association cache lines for subsequent use.

In conjunction with the tenth kind of possible implementation of first aspect present invention, in the 11 kind of possible implementation of first aspect present invention, described cache controller determines cache lines for subsequent use according to the address of described cache lines to be replaced, comprising:

Described cache controller is by the address of described cache lines to be replaced and the first mask phase and the row address obtaining described cache lines to be replaced;

Described cache controller by described row address and the second mask phase with obtain described cache lines for subsequent use, the initial value of described second mask is zero, at every turn by described row address and described second mask phase and after, the value of described second mask is added to the size of a cache lines, until obtain all cache lines for subsequent use.

Second aspect present invention provides a kind of cache controller, comprising:

Receiver module, user receives memory access request;

Search module, for the address search buffer memory according to described memory access request;

First determination module, if for described in search the address that module does not find described memory access request in described buffer memory, then from described buffer memory, determine cache lines to be replaced;

Second determination module, if for the dirty cache lines of described buffer memory behavior to be replaced, then determine to associate cache pool according to the address of described cache lines to be replaced, described association cache pool comprises at least one association cache lines, described association cache lines and described cache lines to be replaced belong to same memory line, described association cache lines is arranged in described buffer memory, the dirty cache lines of described association buffer memory behavior, and the data of described dirty cache lines were modified;

3rd determination module, determines cache lines to be write back for the visit information according to described association cache lines from described association cache pool;

Module for reading and writing, for by described cache lines to be replaced and described in the address of cache lines to be write back and data send to Memory Controller Hub, with make described Memory Controller Hub according to described cache lines to be replaced and described in cache lines to be write back address by described cache lines to be replaced and described in the data write memory of cache lines to be write back, and the data needed for described memory access request are read in from described internal memory the position of described cache lines to be replaced.

In conjunction with second aspect present invention, in the first possible implementation of second aspect present invention, described 3rd determination module specifically for:

According to the access times of described association cache lines and/or write back to indicate determine cache lines to be write back from described association cache pool, described in write back and indicate for representing that described association cache lines is the need of writing back internal memory.

In conjunction with the first possible implementation of second aspect present invention, in the implementation that the second of second aspect present invention is possible, described 3rd determination module is determined in the access times according to described association cache lines in time writing back cache lines from described association cache pool, specifically for:

Determine whether described association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, described nearest least referenced buffer memory chained list is used for sorting according to the access times of each cache lines in Preset Time, the cache lines that in Preset Time described in last M buffer memory behavior of described nearest least referenced buffer memory chained list, access times are minimum, M is positive integer;

If described association cache lines belongs to last M cache lines of described nearest least referenced buffer memory chained list, then determine cache lines to be write back described in the behavior of described association buffer memory.

In conjunction with the first possible implementation of second aspect present invention, in the third possible implementation of second aspect present invention, described 3rd determination module is determined in the sign that writes back according to described association cache lines in time writing back cache lines from described association cache pool, specifically for:

If the sign that writes back of described association cache lines represents that described association cache lines needs to write back internal memory, then determine described association buffer memory behavior to be written time cache lines.

In conjunction with the first possible implementation of second aspect present invention, in the 4th kind of possible implementation of second aspect present invention, described 3rd determination module is determined when writing back cache lines with writing back to indicate from described association cache pool in the access times according to described association cache lines, specifically for:

Judge whether described association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list according to the access times of described association cache lines, described nearest least referenced buffer memory chained list is used for sorting according to the access times of each cache lines in Preset Time, the cache lines that in Preset Time described in last M buffer memory behavior of described nearest least referenced buffer memory chained list, access times are minimum, M is positive integer;

If described association cache lines belongs to last M cache lines of described nearest least referenced buffer memory chained list, and the sign that writes back of described association cache lines represents that described association cache lines needs to write back internal memory, then determine described association buffer memory behavior to be written time cache lines.

In conjunction with the first of second aspect present invention to the 4th kind of possible implementation, in the 5th kind of possible implementation of second aspect present invention, described module for reading and writing also for:

By described after writing back data corresponding to cache lines and writing back described internal memory, the value writing back sign of cache lines described to be write back is set to expression not to be needed to write back internal memory.

In conjunction with the first of second aspect present invention to the 5th kind of possible implementation, in the 6th kind of possible implementation of second aspect present invention, described module for reading and writing also for:

The value writing back sign of each cache lines is periodically set to expression need to write back internal memory.

In conjunction with the first of second aspect present invention to the 5th kind of possible implementation, in the 7th kind of possible implementation of second aspect present invention, describedly write back the value being denoted as counter, if the value of described counter is not less than write back threshold value, then writes back described in and indicate for representing that described association cache lines needs write memory;

In conjunction with the 7th kind of possible implementation of second aspect present invention, in the 8th kind of possible implementation of second aspect present invention, when described write back the value being denoted as counter time, described module for reading and writing the described value writing back sign wait writing back cache lines is set to expression do not need to write back internal memory time, specifically for: the value of described counter is set to zero.

In conjunction with the 7th kind of possible implementation of second aspect present invention, in the 9th kind of possible implementation of second aspect present invention, if write back threshold value described in the value of described counter is less than, then described association cache lines does not need to write back described internal memory, described module for reading and writing also for: the value of described counter is added one.

In conjunction with the first of second aspect present invention to the 9th kind of possible implementation, in the tenth kind of possible implementation of second aspect present invention, described second determination module comprises:

Address calculation, for determining cache lines for subsequent use according to the address of described cache lines to be replaced, described cache lines for subsequent use and described cache lines to be replaced belong to same memory line;

Judging unit, for judging whether described cache lines for subsequent use is arranged in described buffer memory, if described cache lines for subsequent use is arranged in described buffer memory, judge whether described cache lines for subsequent use is dirty cache lines, if the dirty cache lines of described buffer memory behavior for subsequent use, then determine described buffer memory behavior association cache lines for subsequent use.

In conjunction with the tenth kind of possible implementation of second aspect present invention, in the 11 kind of possible implementation of second aspect present invention, described address calculation specifically for:

By the address of described cache lines to be replaced and the first mask phase and the row address obtaining described cache lines to be replaced;

By described row address and the second mask phase with obtain described cache lines for subsequent use, the initial value of described second mask is zero, at every turn by described row address and described second mask phase and after, the value of described second mask is added to the size of a cache lines, until obtain all cache lines for subsequent use.

Third aspect present invention provides a kind of processor, comprise: central processor unit CPU, buffer memory, cache controller, Memory Controller Hub, described buffer memory is connected with described Memory Controller Hub with described CPU respectively by system bus and communicates, and described cache controller is arranged in described buffer memory, wherein:

Described CPU, for sending memory access request to described cache controller;

Described cache controller, for performing the first any one method to the 11 kind of possible implementation of first aspect present invention and first aspect;

Described Memory Controller Hub, for receiving the cache lines to be replaced and the address of cache lines to be write back and data that described cache controller sends, according to described cache lines to be replaced and described in cache lines to be write back address by described cache lines to be replaced and described in the data write memory of cache lines to be write back;

Described Memory Controller Hub also for, receive the address of the memory access request that described cache controller sends, from internal memory, read the data needed for described memory access request according to the address of described memory access request, and the data needed for described memory access request are sent to described cache controller;

Described cache controller also for, the data needed for described memory access request are read in the position of described buffer memory to be replaced.

Method, cache controller and processor that the buffer memory that the embodiment of the present invention provides is replaced, cache controller is by determining the association cache pool of cache lines to be replaced, each association cache lines in association cache pool and cache lines to be replaced belong to same memory line, and from association cache pool, determine cache lines to be write back, by the data write memory together in cache lines to be replaced and cache lines to be write back according to the visit information of association cache lines further.Because cache lines to be replaced and cache lines to be write back belong to same memory line, therefore, the hit rate in row cache district can be improved, thus improve internal storage access performance, in addition, cache controller determines cache lines to be write back according to the visit information of association cache lines further from association cache pool, only the cache lines to be write back in association cache pool is write back internal memory, therefore, it is possible to reduce internal memory write number of times, improve serviceable life of internal memory.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the read-write theory schematic diagram of existing internal memory;

The structural representation of the hardware that Fig. 2 is suitable for by the embodiment of the present invention;

The process flow diagram of the method that Fig. 3 replaces for a kind of buffer memory that the embodiment of the present invention provides;

Fig. 4 is a kind of structural representation of buffer memory;

The process flow diagram of the method that Fig. 5 replaces for the another kind of buffer memory that the embodiment of the present invention provides;

The structural representation of a kind of cache controller that Fig. 6 provides for the embodiment of the present invention;

The structural representation of the another kind of cache controller that Fig. 7 provides for the embodiment of the present invention;

The structural representation of the processor that Fig. 8 provides for the embodiment of the present invention.

Embodiment

For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

Fig. 1 is the read-write theory schematic diagram of existing internal memory, as shown in Figure 1, memory access request address sequence comprises three memory access request, access order is followed successively by: cache lines (cacheline) A0, cache lines B0 and cache lines A1, cache lines A0 and cache lines A1 belong to same memory line A.As Memory Controller Hub access cache row A0, all buffer memory provisional capitals of memory line A in internal memory (Memory) array are read row buffer (Rowbuffer) by Memory Controller Hub, Memory Controller Hub reads with an internal memory behavior least unit when reading data from memory array, and row buffer is used for preserving the data of the memory line of the last access in internal memory.Then, the data of cache lines A0 are read buffer memory (cache) by Memory Controller Hub from row buffer.After cache lines A0 access terminates, Memory Controller Hub wants access cache row B0, cache lines B0 and A1 belongs to different memory line, therefore, row buffer is not hit, and Memory Controller Hub also needs the data reading memory line B from memory array to row buffer, when Memory Controller Hub access cache row A1, because cache lines A1 and B1 belongs to different memory line, so row buffer is not still hit.In situation shown in Fig. 1, the hit rate of row buffer is 0, all needs to read data from memory array at every turn, and memory access latencies is larger.

For the problems referred to above, the embodiment of the present invention is by being polymerized to sequential write by memory access request queue from random write at cache layer, namely increase the memory access request to same memory line in memory access request queue, to improve the hit rate of row buffer, reduce memory access latencies.The hardware configuration of the embodiment of the present invention as shown in Figure 2, comprise: processor and internal memory, this processor inside comprises: one or more CPU (central processing unit) (CentralProcessingUnit is called for short CPU), buffer memory, Memory Controller Hub and cache controller.Processor by cache controller access cache, and passes through Memory Controller Hub access memory.The internal memory of the present embodiment can be DRAM, NVM etc., when interior save as NVM time, NVM can be phase transition storage (PhaseChangeMemory, be called for short PCM), resistive formula storer (ResistiveRandomAccessMemory, be called for short RRAM), spin-transfer torque random access memory (Spintransfertorque-randomaccessmemory, be called for short STT-RAM), magnetic RAM (MagneticRandomAccessMemory, be called for short MRAM) etc.

The process flow diagram of the method that Fig. 3 replaces for a kind of buffer memory that the embodiment of the present invention provides, as shown in Figure 3, the method for the present embodiment can comprise the following steps:

Step 101, cache controller receive memory access request, according to the address search buffer memory of memory access request, if do not find the address of memory access request in the buffer, then from buffer memory, determine cache lines to be replaced.

Memory access request is sent by processor, and processor is not direct access memory, but by buffer memory dereference internal memory.Particularly, processor, first according to the address access cache of memory access request, particular by the whole cache lines controlled in cache controller traversal buffer memory during processor access buffer memory, searches the address of memory access request.If cache controller does not find the address of this memory access request in the buffer, namely buffer memory does not hit, then cache controller starts to carry out buffer memory replacement, data in cache lines in buffer memory are substituted into internal memory, and by the position of the digital independent needed for this memory access request to the cache lines be replaced from internal memory, then from buffer memory, read the data needed for this memory access request.

Usually virtual address is carried in the memory access request that processor sends, this memory access request arrival cache controller before also through memory management unit (MemoryManagementUnit, be called for short MMU), MMU carries out the conversion of virtual address to real address, virtual address is also referred to as virtual address, real address is also referred to as physical address, and therefore, the address of the memory access request that cache controller receives is real address.

When carrying out buffer memory and replacing, cache controller determines cache lines to be replaced from buffer memory, cache controller can adopt any one cache replacement algorithm existing to determine this cache lines to be replaced, conventional cache replacement algorithm has least recently used (LeaseRecentlyUsed, be called for short LRU) replace algorithm, minimum frequency of utilization (LeaseFrequentlyUsed, be called for short LFU), used (LeaseRecentlyUsed recently, be called for short MRU) replace algorithm etc., will not enumerate here.It is that data block least-recently-used in buffer memory is replaced out buffer memory that LRU replaces algorithm, and the data block that MRU replaces algorithms selection accessed recently replaces out buffer memory, and LFU replaces minimum accessed data block in algorithms selection buffer memory and replaces out buffer memory.Wherein, LRU uses more general replacement algorithm, and LRU is used for sorting to cache lines according to access time of each cache lines and method number of times, such as, in Preset Time, according to the access times of each cache lines from how to sort to few.

If the dirty cache lines of step 102 buffer memory to be replaced behavior, then cache controller is determined to associate cache pool according to the address of cache lines to be replaced, association cache pool comprises at least one association cache lines, association cache lines and cache lines to be replaced belong to same memory line, association cache lines is arranged in buffer memory, the dirty cache lines of association buffer memory behavior, the data of dirty cache lines were modified.

Cache controller first judges whether this cache lines to be replaced is dirty cache lines (dirtycacheline), and the data of dirty cache lines were modified.If this cache lines to be replaced is not dirty cache lines, illustrate that data corresponding to cache lines to be replaced are consistent in internal memory with buffer memory, then do not need the data write memory in this cache lines to be replaced, the data needed for this memory access request are directly read in the position of this cache lines to be replaced by cache controller from internal memory.If this cache lines to be replaced is dirty cache lines, illustrate that data corresponding to this cache lines to be replaced are inconsistent in internal memory and buffer memory, cache controller first will by the data write memory from buffer memory in this cache lines to be replaced, then, the data needed for this memory access request could be read in from internal memory the position of this cache lines to be replaced.

The association cache pool of cache lines to be replaced comprises at least one association cache lines, and each association cache lines belongs to same memory line with cache lines to be replaced, and associates cache lines and be arranged in buffer memory, associates the dirty cache lines of buffer memory behavior.Cache controller is determined to associate cache pool according to the address of cache lines to be replaced, is specially:

First, cache controller determines cache lines for subsequent use according to the address of cache lines to be replaced, and cache lines for subsequent use and cache lines to be replaced belong to same memory line, from internal memory, namely find out all cache lines belonging to same memory line with cache lines to be replaced.Particularly, cache controller is by the address of cache lines to be replaced and the first mask phase and the row address obtaining cache lines to be replaced, the figure place of this first mask is identical with the figure place of cache lines to be replaced, address bit corresponding with the row address of cache lines to be replaced in this first mask is 1, and other address bits are 0.Then, cache controller by the row address of cache lines to be replaced and the second mask phase with obtain cache lines for subsequent use, cache lines for subsequent use and cache lines to be replaced belong to same memory line.The initial value of this second mask is 0, at every turn by row address and the second mask phase and the address obtaining a cache lines for subsequent use, behind the address obtaining cache lines for subsequent use, the size value of the second mask being added to a cache lines obtains the second new mask, this second new mask and this row address phase with obtain cache lines for subsequent use.If this row has N number of cache lines, so after N time with computing, obtain all cache lines that cache lines to be replaced with this belongs to same memory line.

Then, cache controller judges whether each cache lines for subsequent use is arranged in buffer memory, can judge successively according to the sequence of addresses of each cache lines, if judge, certain cache lines is arranged in buffer memory, then cache controller judges whether this cache lines for subsequent use is dirty cache lines further.If cache lines for subsequent use is not in the buffer, then Memory Controller Hub continues to judge whether in the buffer next cache lines.If the dirty cache lines of buffer memory behavior for subsequent use, then cache controller determines buffer memory behavior for subsequent use association cache lines.Cache controller is when judging whether cache lines for subsequent use is dirty cache lines, can judge whether this cache lines for subsequent use is dirty cache lines according to the Modify position of cache lines for subsequent use, Modify position is for representing whether current cache row is dirty cache lines, Modify has two kinds of value: dirty and clean, if the data of processor to a certain cache lines in buffer memory have carried out write operation, so cache controller by the Modify of this cache lines for being revised as dirty.

Please refer to Fig. 4, Fig. 4 is a kind of structural representation of buffer memory, this buffer memory has N bar road (way), Mei Tiao road has multiple cache lines, and each cache lines comprises: label (tag), data (data), amendment indicate (Modify) and write back sign (Write-back).Wherein, tag, data and Modify are the parameters that cache lines itself has, and tag is used for marking the address of internal memory corresponding to current cache row, and data represents the data of actual storage in current cache row, and Modify marks whether current cache row is dirty cache lines.Write back and be denoted as newly-increased parameter, need in the embodiment of the present invention to write back sign position for each cache lines increases by one, this writes back and indicates for representing that current cache row is the need of writing back internal memory, such as, represent that this writes back sign with 1 bit, when the value writing back sign position is 1, represent that current cache capable needs writes back internal memory, when the value writing back sign position is 0, represent that current cache row needs to write back internal memory.Carry out unified management by the sign that writes back of cache controller to each cache lines, particularly: after the data in a certain cache lines are write back internal memory by cache controller, the value writing back sign of this cache lines is set to expression by cache controller not to be needed to write back internal memory.Like this, when perform next time memory access request time, cache controller can by this write back indicate judge do not need in this cache lines write memory.The value writing back sign of each cache lines can be periodically set to expression by cache controller to be needed to write back internal memory.

Step 103, cache controller determine cache lines to be write back according to the visit information of association cache lines from association cache pool.

In the present embodiment, cache controller is after determining the association cache pool of cache lines to be replaced, be not that the relevant cache lines in association cache lines is all write back internal memory, but from association cache pool, determine cache lines to be write back according to the visit information of association cache lines, only cache lines to be write back is write back internal memory.Although, by relevant cache lines all write back internal memory and also can increase request of access to same memory line in memory access request queue, and then add the hit rate of row cache.But when associating certain some cache lines in cache lines and being larger by the possibility again write, what can increase internal memory writes number of times.This method, for writing the conditional storer of number of times, can reduce the life-span of this kind of storer, and such as NVM just has the restriction writing number of times, and what increase NVM writes number of times, affects the serviceable life of NVM.Therefore, the present invention is after determining association cache pool, and determine cache lines to be write back according to the visit information of association cache lines further, that can reduce internal memory while improving internal storage access performance writes number of times.

The visit information of association cache lines comprises the access times of association cache lines and writes back sign.Cache controller according to association cache lines visit information from association cache pool determine cache lines to be write back, be specially: cache controller according to association cache lines access times and/or write back indicate from association cache pool determine cache lines to be write back.

The first situation, cache controller determines cache lines to be write back according to the access times of association cache lines from association cache pool, be specially: cache controller determines whether association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, nearest least referenced buffer memory chained list is used for sorting according to the access times of each cache lines in Preset Time, the cache lines that in last M buffer memory behavior Preset Time of this nearest least referenced buffer memory chained list, access times are minimum, M is positive integer.If association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, then cache controller determines association buffer memory behavior to be written time cache lines.It should be noted that, cache controller is that a nearest least referenced buffer memory chained list is set up on each road in buffer memory, and all cache lines of this nearest least referenced buffer memory chained list to this road sort according to access times.Cache controller is when determining whether association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, first according to the nearest least referenced buffer memory chained list that the address of association cache lines finds the road at association cache lines place corresponding, then, search from nearest least referenced buffer memory chained list corresponding to this road.

Second case, cache controller determines cache lines to be write back according to the sign that writes back of association cache lines from association cache pool, be specially: if the sign that writes back of association cache lines represents that association cache lines needs to write back internal memory, then cache controller determines association buffer memory behavior to be written time cache lines.

The third situation, cache controller determines to be write back cache lines with writing back to indicate from associating cache pool according to the access times of association cache lines, is specially: according to the access times of association cache lines, cache controller judges whether association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list; If association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, and the sign that writes back associating cache lines represents that association cache lines needs to write back internal memory, then cache controller determines association buffer memory behavior to be written time cache lines.

The address of cache lines to be replaced and cache lines to be write back and data are sent to Memory Controller Hub by step 104, cache controller, to make Memory Controller Hub according to the data write memory of the address of cache lines to be replaced and cache lines to be write back by cache lines to be replaced and cache lines to be write back, and the data needed for memory access request are read in from internal memory the position of cache lines to be replaced.

Cache controller is being determined after writing back cache lines, and the data in cache lines to be replaced and cache lines to be write back are write back internal memory successively.Particularly, the address of cache lines to be replaced and cache lines to be write back and data are sent to Memory Controller Hub by cache controller, Memory Controller Hub is according to the data write memory of the address of cache lines to be replaced and cache lines to be write back by cache lines to be replaced and cache lines to be write back, then, the address of this memory access request is sent to Memory Controller Hub by cache controller, Memory Controller Hub reads the data needed for memory access request according to the address of this memory access request from internal memory, and the data needed for this memory access request are sent to cache controller, data needed for this memory access request are read in the position of cache lines to be replaced by cache controller.Because cache lines to be replaced and cache lines to be write back belong to same memory line, therefore, when internally depositing into row write operation, Memory Controller Hub only needs to read a secondary data from memory array, all buffer memory provisional capitals of this row are read row buffer, and this row cache district can hit continuously.

The present embodiment, cache controller is by determining the association cache pool of cache lines to be replaced, each association cache lines in association cache pool and cache lines to be replaced belong to same memory line, and from association cache pool, determine cache lines to be write back, by the data write memory together in cache lines to be replaced and cache lines to be write back according to the visit information of association cache lines further.Because cache lines to be replaced and cache lines to be write back belong to same memory line, therefore, the hit rate in row cache district can be improved, thus improve internal storage access performance, in addition, cache controller determines cache lines to be write back according to the visit information of association cache lines further from association cache pool, only the cache lines to be write back in association cache pool is write back internal memory, therefore, it is possible to reduce internal memory write number of times, improve serviceable life of internal memory.

On the basis of above-described embodiment one, in other embodiments of the present invention, at cache controller by after writing back data corresponding to cache lines and writing back internal memory, described method also comprises: the value writing back sign of cache lines to be write back is set to expression by cache controller not to be needed to write back internal memory.

Never need to write back internal memory under the writing back of each cache lines is indicated in following two kinds of situations to become and need to write back internal memory: (1) each cache controller judges that the data of cache lines are the need of when writing back internal memory, if the sign expression that writes back of this cache lines does not need to write back internal memory, and this buffer memory behavior dirty data of the modify bit representation of this cache lines is capable, then the data of this cache lines are not write back internal memory by cache controller, but the sign that writes back of this cache lines are revised as and need to write back internal memory.(2) value writing back sign of each cache lines is periodically set to expression by cache controller needs to write back internal memory.Such as, cache controller inquires about the cache lines in LRU after 1,000 ten thousand accessing operations, represents that not needing the cache lines writing back internal memory to be set to needs to write back internal memory by writing back in LRU to indicate.

The process flow diagram of the method that Fig. 5 replaces for the another kind of buffer memory that the embodiment of the present invention provides, in the present embodiment, according to writing back to indicate, how main explanation cache controller judges that association cache lines is the need of writing back internal memory, be described to write back the value being denoted as counter in the present embodiment, as shown in Figure 5, the method for the present embodiment comprises the following steps:

Step 201, cache controller judge whether the value of the counter associating cache lines is less than and write back threshold value N.

The method of the present embodiment, need for each cache lines arranges a counter, the threshold value N that writes back of this counter is positive integer, if the value of the counter of cache lines is less than write back threshold value N, illustrate that this cache lines last time shorter in writing back the time, be not suitable for again being write back internal memory, if the value of the counter of cache lines is not less than write back threshold value N, then the data in this cache lines write back internal memory.In this step, if the value of the counter of association cache lines is less than write back threshold value N, then perform step 202, if the value of the counter of association cache lines is not less than write back threshold value N, perform step 203.

The value of the counter of association cache lines is added 1 by step 202, cache controller.

When the value of counter associating cache lines be less than write back threshold value N time, do not need the data in association cache lines to write back internal memory, but will this step be performed, the value of the counter of association cache lines is added 1.

Data in cache lines to be replaced are write back internal memory by step 203, cache controller, and the value of the counter of cache lines to be replaced is set to 0.

When cache controller is determined when writing back cache lines with writing back to indicate from associating cache pool according to the access times of association cache lines, according to the access times of association cache lines, cache controller judges whether association cache lines belongs to last M the cache lines of LRU, if association cache lines belongs to last M the cache lines of LRU, and the sign that writes back associating cache lines represents that association cache lines needs to write back internal memory, then cache controller determines connection buffer memory behavior to be written time cache lines.In the present embodiment, the value of M can write back threshold value N dynamic conditioning according to counter, and when N value is larger, illustrate and require comparatively tight to the number of times that writes back of internal memory, in order to improve the hit rate of row buffer, M value can be larger.Correspondingly, when N value is less, illustrate and require not tight to the number of times that writes back of internal memory, M value can be less.

The structural representation of a kind of cache controller that Fig. 6 provides for the embodiment of the present invention, as shown in Figure 6, the cache controller of the present embodiment comprises: receiver module 11, search module 12, first determination module 13, second determination module 14, the 3rd determination module 15 and module for reading and writing 16.

Wherein, receiver module 11, user receives memory access request;

Search module 12, for the address search buffer memory according to described memory access request;

First determination module 13, if for described in search the address that module does not find described memory access request in described buffer memory, then from described buffer memory, determine cache lines to be replaced;

Second determination module 14, if for the dirty cache lines of described buffer memory behavior to be replaced, then determine to associate cache pool according to the address of described cache lines to be replaced, described association cache pool comprises at least one association cache lines, described association cache lines and described cache lines to be replaced belong to same memory line, described association cache lines is arranged in described buffer memory, the dirty cache lines of described association buffer memory behavior, and the data of described dirty cache lines were modified;

3rd determination module 15, determines cache lines to be write back for the visit information according to described association cache lines from described association cache pool;

Module for reading and writing 16, for by described cache lines to be replaced and described in data write memory in cache lines to be write back, and the data needed for described memory access request are read in from described internal memory the position of described cache lines to be replaced.

Described 3rd determination module 15 specifically for: according to the access times of described association cache lines and/or write back to indicate determine cache lines to be write back from described association cache pool, described in write back and indicate for representing that described association cache lines is the need of writing back internal memory.

Alternatively, if described 3rd determination module 15 determines cache lines to be write back according to the access times of described association cache lines from described association cache pool, then the 3rd determination module 15 specifically for: determine whether described association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list, described nearest least referenced buffer memory chained list is used for sorting according to the access times of each cache lines in Preset Time, the cache lines that in Preset Time described in last M buffer memory behavior of described nearest least referenced buffer memory chained list, access times are minimum, M is positive integer; If described association cache lines belongs to last M cache lines of described nearest least referenced buffer memory chained list, then determine cache lines to be write back described in the behavior of described association buffer memory.

Alternatively, if described 3rd determination module 15 determines cache lines to be write back according to the sign that writes back of described association cache lines from described association cache pool, then the 3rd determination module 15 specifically for: if described association cache lines write back indicate represent described association cache lines need to write back internal memory, then determine described association buffer memory behavior to be written time cache lines.

Alternatively, if described 3rd determination module 15 determines to be write back cache lines with writing back to indicate from described association cache pool according to the access times of described association cache lines, then the 3rd determination module 15 specifically for: judge whether described association cache lines belongs to last M cache lines of nearest least referenced buffer memory chained list according to the access times of described association cache lines, described nearest least referenced buffer memory chained list is used for sorting according to the access times of each cache lines in Preset Time, the cache lines that in Preset Time described in last M buffer memory behavior of described nearest least referenced buffer memory chained list, access times are minimum, M is positive integer, if described association cache lines belongs to last M cache lines of described nearest least referenced buffer memory chained list, and the sign that writes back of described association cache lines represents that described association cache lines needs to write back internal memory, then determine described association buffer memory behavior to be written time cache lines.

The cache controller of the present embodiment can be used for the technical scheme of manner of execution embodiment one and embodiment two, and specific implementation and technique effect type, repeat no more here.

The structural representation of the another kind of cache controller that Fig. 7 provides for the embodiment of the present invention, the device of the present embodiment is on the basis of Fig. 6 shown device structure, and further, described second determination module 14 comprises: address calculation 141 and judging unit 142.

Wherein, address calculation 141, for determining cache lines for subsequent use according to the address of described cache lines to be replaced, described cache lines for subsequent use and described cache lines to be replaced belong to same memory line; Judging unit 142, for judging whether described cache lines for subsequent use is arranged in described buffer memory; If described cache lines for subsequent use is arranged in described buffer memory, then judge whether described cache lines for subsequent use is dirty cache lines further; If the dirty cache lines of described buffer memory behavior for subsequent use, then determine described buffer memory behavior association cache lines for subsequent use.

Address calculation 141 specifically for: by the address of described cache lines to be replaced and the first mask phase and the row address obtaining described cache lines to be replaced; After obtaining described row address, by described row address and the second mask phase with obtain described cache lines for subsequent use, the initial value of described second mask is zero, at every turn by described row address and described second mask phase and after, the value of described second mask is added to the size of a cache lines, until obtain all cache lines for subsequent use.

In the present embodiment, described module for reading and writing 16 also for: by described after writing back data corresponding to cache lines and writing back described internal memory, the value writing back sign of cache lines described to be write back is set to expression not to be needed to write back internal memory.

In a kind of feasible implementation, described module for reading and writing 16 also for: the value writing back sign of each cache lines is periodically set to expression to be needed to write back internal memory.When specific implementation, described in write back that to indicate to be the value of counter, if the value of described counter is not less than and writes back threshold value, then write back described in and indicate for representing that described association cache lines needs write memory; If write back threshold value described in the value of described counter is less than, then write back described in and indicate for representing that described association cache lines does not need write memory, module for reading and writing 16 is also for adding one by the value of described counter.When described write back the value being denoted as counter time, described module for reading and writing 16 the described value writing back sign wait writing back cache lines is set to expression do not need to write back internal memory time, specifically for: the value of described counter is set to zero.

It should be noted that, above-mentioned functions Module Division is only a kind of embodiment wherein, in embodiment, those skilled in the art can under the description of reference the various embodiments described above, do different functional modules as the case may be to divide to perform the above method, complete function of the present invention, reach effect of the present invention.

The embodiment of the present invention also provides a kind of processor, the structural representation of the processor that Fig. 8 provides for the embodiment of the present invention, as shown in Figure 8, the processor 200 that the present embodiment provides comprises: central processor unit CPU21, buffer memory 22, cache controller 23, Memory Controller Hub 24, buffer memory 22 is connected with Memory Controller Hub 24 with CPU21 respectively by system bus and communicates, cache controller 23 is arranged in buffer memory 22, and Memory Controller Hub 24 can be communicated with Memory linkage by system bus.

Wherein, CPU21, for sending memory access request to cache controller 23; Cache controller 23, for performing Fig. 3 and method embodiment illustrated in fig. 5; Memory Controller Hub 24, for receiving the cache lines to be replaced and the address of cache lines to be write back and data that cache controller 23 sends, according to the address of cache lines to be replaced and cache lines the to be write back data write memory by cache lines to be replaced and cache lines to be write back; Memory Controller Hub 24 also for, receive the address of the memory access request that cache controller 23 sends, from internal memory, read the data needed for memory access request according to the address of memory access request, and the data needed for memory access request are sent to cache controller 23; Cache controller 23 also for, the data needed for memory access request are read in the position of buffer memory to be replaced.

One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.

Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims

1. a method for buffer memory replacement, is characterized in that, comprising:

2. method according to claim 1, is characterized in that, described cache controller determines cache lines to be write back according to the visit information of described association cache lines from described association cache pool, comprising:

3. method according to claim 2, is characterized in that, described cache controller determines cache lines to be write back according to the access times of described association cache lines from described association cache pool, comprising:

4. method according to claim 2, is characterized in that, described cache controller determines cache lines to be write back according to the sign that writes back of described association cache lines from described association cache pool, comprising:

5. method according to claim 2, is characterized in that, described cache controller determines to be write back cache lines with writing back to indicate from described association cache pool according to the access times of described association cache lines, comprising:

6. the method according to any one of claim 2-5, is characterized in that, described cache controller by described after writing back data corresponding to cache lines and writing back described internal memory, described method also comprises:

7. the method according to any one of claim 2-6, is characterized in that, described method also comprises:

8. the method according to any one of claim 2-6, is characterized in that, described in write back the value being denoted as counter, if the value of described counter is not less than write back threshold value, then write back described in indicate for representing that described association cache lines needs write memory;

9. method according to claim 8, is characterized in that, when described write back the value being denoted as counter time, the value writing back sign of cache lines described to be write back is set to expression by described cache controller not to be needed to write back internal memory, comprising:

The value of described counter is set to zero by described cache controller.

10. method according to claim 8, is characterized in that, if the value of described counter be less than described in write back threshold value, described method also comprises:

The value of described counter is added one by described cache controller.

11. methods according to any one of claim 1-10, is characterized in that, described cache controller is determined to associate cache pool according to the address of described cache lines to be replaced, comprising:

12. methods according to claim 11, is characterized in that, described cache controller determines cache lines for subsequent use according to the address of described cache lines to be replaced, comprising:

13. 1 kinds of cache controllers, is characterized in that, comprising:

Receiver module, user receives memory access request;

14. cache controllers according to claim 13, is characterized in that, described 3rd determination module specifically for:

15. cache controllers according to claim 14, is characterized in that, described 3rd determination module is determined in the access times according to described association cache lines in time writing back cache lines from described association cache pool, specifically for:

16. cache controllers according to claim 14, is characterized in that, described 3rd determination module is determined in the sign that writes back according to described association cache lines in time writing back cache lines from described association cache pool, specifically for:

17. cache controllers according to claim 14, is characterized in that, described 3rd determination module is determined when writing back cache lines with writing back to indicate from described association cache pool in the access times according to described association cache lines, specifically for:

18. cache controllers according to any one of claim 14-17, is characterized in that, described module for reading and writing also for:

19. cache controllers according to any one of claim 14-18, is characterized in that, described module for reading and writing also for:

20. cache controllers according to any one of claim 14-18, it is characterized in that, describedly write back the value being denoted as counter, if the value of described counter is not less than write back threshold value, then writes back described in and indicate for representing that described association cache lines needs write memory;

21. cache controllers according to claim 20, it is characterized in that, when described write back the value being denoted as counter time, described module for reading and writing the described value writing back sign wait writing back cache lines is set to expression do not need to write back internal memory time, specifically for: the value of described counter is set to zero.

22. cache controllers according to claim 20, is characterized in that, if the value of described counter be less than described in write back threshold value, then described association cache lines does not need to write back described internal memory, described module for reading and writing also for: the value of described counter is added one.

23. cache controllers according to any one of claim 13-22, it is characterized in that, described second determination module comprises:

24. cache controllers according to claim 23, is characterized in that, described address calculation specifically for:

25. 1 kinds of processors, comprise: central processor unit CPU, buffer memory, cache controller, Memory Controller Hub, described buffer memory is connected with described Memory Controller Hub with described CPU respectively by system bus and communicates, and described cache controller is arranged in described buffer memory, it is characterized in that:

Described CPU, for sending memory access request to described cache controller;

Described cache controller, requires the method according to any one of 1-12 for enforcement of rights;